MASTERGAN1 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 27
Technical content
Datasheet sections
- 1 Block diagram
- 2 Pin description and connection diagram
- 2.1 Pin list
- 3 Electrical Data
- 3.1 Absolute maximum ratings
- 3.2 Recommended operating conditions
- 3.3 Thermal data
- 4 Electrical characteristics
- 4.1 Driver
- 4.2 GaN power transistor
- 5 Device characterization values
- 6 Functional description
- 6.1 Logic inputs
- 6.2 Bootstrap structure
- 6.3 VCC supply pins and UVLO function
- 6.4 VBO UVLO protection
- 6.5 Thermal shutdown
- 7 Typical application diagrams
- 8 Package information
- 9 Suggested footprint
- 10 Ordering information
Features
- 600 V system-in-package integrating half-bridge gate driver and high-voltage power GaN transistors: – QFN 9 x 9 x 1 mm package – R DS(ON) = 150 mΩ – I DS(MAX) = 10 A
- Reverse current capability
- Zero reverse recovery loss
- UVLO protection on low-side and high-side
- Internal bootstrap diode
- Interlocking function
- Dedicated pin for shutdown functionality
- Accurate internal timing match
- 3.3 V to 15 V compatible inputs with hysteresis and pull-down
- Overtemperature protection
- Bill of material reduction
- Very compact and simplified layout
- Flexible, easy and fast design. Application
- Switch-mode power supplies
- Chargers and adapters
- High-voltage PFC, DC-DC and DC-AC Converters
- UPS Systems
- Solar Power
Description
The MASTERGAN1 is an advanced power system-in-package integrating a gate driver and two enhancement mode GaN transistors in half‑bridge configuration. The integrated power GaNs have RDS(ON) of 150 mΩ and 650 V drain‑source breakdown voltage, while the high side of the embedded gate driver can be easily supplied by the integrated bootstrap diode. The MASTERGAN1 features UVLO protection on both the lower and upper driving sections, preventing the power switches from operating in low efficiency or dangerous conditions, and the interlocking function avoids cross-conduction conditions. The input pins extended range allows easy interfacing with microcontrollers, DSP units or Hall effect sensors. The MASTERGAN1 operates in the industrial temperature range, -40°C to 125°C. The device is available in a compact 9x9 mm QFN package. Product status link MASTERGAN1 Product label High power density 600V Half bridge driver with two enhancement mode GaN HEMT MASTERGAN1 Datasheet DS13417 - Rev 3 - October 2020 For further information contact your local STMicroelectronics sales office.
1 Block diagram
Figure 1. Block diagram
2 Pin description and connection diagram
Figure 2. Pin connection (top view)
2.1 Pin list
Table 1. Pin description
22 BOOT Power Supply Gate driver high-side supply voltage
21 OUTb Power Supply Gate driver high-side reference voltage, used only for Bootstrap
capacitor connection. Internally connected to OUT.
27 VCC Power Supply Logic supply voltage
Pin Number Pin Name Type Function
1 PVCC Power Supply Gate driver low-side supply voltage
28, EP1 GND Power Supply Logic ground 3 PGND Power Supply Gate driver low-side driver reference. Internally connected to SENSE.
26 HIN Logic Input High-Side driver logic input
24 LIN Logic Input Low-Side driver logic input
25 SD/OD Logic Input-Output Driver Shutdown input and Over-Temperature
2 GL Output Low-Side GaN gate. 20 GH Output High-Side GaN gate. 23, 29, 30, 31 N.C. Not Connected Leave floating MASTERGAN1 Pin list DS13417 - Rev 3 page 4/27
3 Electrical Data
3.1 Absolute maximum ratings
Table 2. Absolute maximum ratings (each voltage referred to GND unless otherwise specified)
- PGND internally connected to SENSE.
- OUTb internally connected to OUT.
- T CB is temperature of case exposed pad.
- Range estimated by characterization, not tested in production.
- Value specified by design factor, pulse duration limited to 50 µs and junction temperature.
3.2 Recommended operating conditions
Table 3. Recommended operating conditions (Each voltage referred to GND unless otherwise specified)
- PGND internally connected to SENSE.
- OUTb internally connected to OUT.
- 5 V is recommended during high-hide turn-on.
3.3 Thermal data
Table 4. Thermal data
- The junction to ambient thermal resistance is obtained simulating the device mounted on a 2s2p (4 layer) FR4 board as
JESD51-5,7 with 6 thermal vias for each exposed pad. Power dissipation uniformly distributed over the two GaN transistors.
4 Electrical characteristics
4.1 Driver
Table 5. Driver electrical characteristics : VCC = PVCC = 6 V; SENSE = GND; TJ = 25°C, unless otherwise
Electrical characteristics
- VCC UVLO is referred to VCC - GND.
- R BD(on) is tested in the following way:
- Range estimated by characterization, not tested in production.
4.2 GaN power transistor
Table 6. GaN power transistor electrical characteristics (VGS = 6 V; TJ = 25°C, unless otherwise specified. )
Symbol Parameter Test condition Min Typ Max Unit IDSS Zero gate voltage drain current VDS = 600 V VGS = 0 V 0.7 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 2.5 mA (1) 1.7 V IGS Gate to source voltage VDS = 0 V(2) 57 µA RDS(on) Static drain-source on-resistance ID = 3.2 A TJ = 25°C 150 220 mΩ TJ = 125°C (2) 330 1. Tested on wafer. 2. Value estimated by characterization, not tested in production. MASTERGAN1 GaN power transistor DS13417 - Rev 3 page 9/27
5 Device characterization values
and are not subject to the production test. Table 7. GaN power transistor characterization values
- C O(ER) is the fixed capacitance that would give the same stored energy as COSS while VDS is rising from 0 V to the stated
- C O(TR) is the fixed capacitance that would give the same charging time as COSS while VDS is rising from 0 V to the stated
Table 8. Inductive load switching characteristics
- t (on) and t(off) include the propagation delay time of the internal driver
- t C(on) and tC(off) are the switching times of GaN transistor itself under the internally given gate driving conditions
Figure 3. Switching time definition Figure 4. Typ ID vs. VDS at TJ=25°C Figure 5. Typ ID vs. VDS at TJ=125°C
12 TJ=125°C
Figure 6. Typ RDS(on) vs. ID at TJ=25°C Figure 7. Typ RDS(on) vs. ID at TJ=125°C
0.51 TJ=125°C 4V
Figure 8. Typ ID vs. VDS Figure 9. Typ RDS(on) vs. TJ, normalized at 25°C
6 Functional description
6.1 Logic inputs
- SD/OD: Shutdown input, active low;
- LIN: low-side driver inputs, active high;
- HIN: high-side driver inputs, active high.
Table 9. Inputs truth table (applicable when device is not in UVLO) case, for example, there is an interruption in the logic lines or the controller outputs are in tri-state conditions. short propagation delay to output.
6.2 Bootstrap structure
realized by a patented integrated high-voltage DMOS, to reduce the external components. The Boostrap integrated circuit is connected to VCC pin and is driven synchronously with the low-side driver. operating frequency is approximately higher than 500 kHz.
6.3 VCC supply pins and UVLO function
gate charge to the high-side and low-side GaN transistors flows through this pin. each supply pin is highly recommended.
goes above the VCCthON voltage. A VCChys hysteresis is provided for noise rejection purpose. Figure 16. VCC UVLO and Low Side
6.4 VBO UVLO protection
order to avoid intermittent operation, a hysteresis sets the turn-off threshold with respect to the turn-on threshold. the HIN pin's rising edge, that activates the high side transistor's turn-on. Figure 17. VBO UVLO and High Side
6.5 Thermal shutdown
The integrated gate driver has a thermal shutdown protection. junction temperature is below TTSD-THYS and SD/OD is below VTSD. GaN are driven again according to inputs when SD/OD rises above Vih. Figure 18. Thermal shutdown timing waveform
7 Typical application diagrams
Figure 19. Typical application diagram – Resonant LLC converter Figure 20. Typical application diagram – Active clamp flyback
8 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 8.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information Table 10. QFN 9 x 9 x 1 mm package dimensions Note: 1. Dimensioning and tolerances conform to ASME Y14.5-2009.
- All dimensions are in millimeters.
- N total number of terminals.
- Dimensions do not include mold protrusion, not to exceed 0.15 mm.
- Package outline exclusive of metal burr dimensions.
Package information
DS13417 - Rev 3 page 19/27
Figure 21. QFN 9 x 9 x 1 mm package dimensions
9 Suggested footprint
provides the following footprint design, which is suitable for the largest variety of PCBs. copper layers. A PCB layout example is available with the MASTERGAN1 evaluation board. Figure 22. Suggested footprint (top view drawing)
Table 11. Order codes
Ordering information
DS13417 - Rev 3 page 22/27
Revision history
Table 12. Document revision history 15-Jul-2020 1 Initial release.
Table 5. Driver electrical characteristics : VCC = PVCC = 6 V; SENSE = GND; TJ = 25°C, unless otherwise specified (Each