MAR2901CB

MA2901 ZARLINK | Alldatasheet

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The MA2901 is an industry standard 4-bit microprocessor slice It provides a set of ALU functions selected by microcode data applied to the inputs. The device is cascadable to handle any word length. It can be used as a building block in the construction of microcomputers and controllers tailored to meet specialised applications. Dual Address Architecture Machine cycles are saved by simultaneous, independent access to two working registers. ALU has Eight Functions Operations performed are addition, two subtractions and five logic functions on two source operands. Four State Flags Zero, negative, carry and overflow. Left / Right Shift is Independent of ALU Only one cycle taken for add and shift operations. Expandable Any number of MA2901 units can be connected together to achieve longer word lengths. Micro Programmable Three groups, each of three bits, for ALU function, source operand and destination control. DS3576-3.3 MA2901 RADIATION HARD 4-BIT MICROPROCESSOR SLICE OPERATION A detailed block diagram of the microprogrammable microprocessor structure is shown in figure 1. The circuit is a four-bit slice, cascadable to any number of bits. Therefore, all data paths within the circuit are four bits wide. The two key elements in the figure 1 are the 16-word by 4-bit 2-port RAM and the high speed ALU. Data from any of the 16 words of the Random Access Memory (RAM) can be read from the A-port of the RAM as controlled by the 4-bit A-address field input. Likewise, data from any of the 16 words of the RAM as defined by the B- address field input can be simultaneously read from the B-port of the RAM. The same code can be applied to the A-select field and B-select field in which case the identical file data will appear at both the RAM A-port and B-port outputs simultaneously. When enabled by the RAM write enable (RAM EN), new data is always written into the file (word) defined by the B- address field of the RAM. The RAM data input field is driven by a 3-input multiplexer. This configuration is used to shift the ALU output data (F) if desired. This three-input multiplexer scheme allows the data to be shifted up one bit position, shifted down one bit position, or not shifted in either direction. The RAM A-port data outputs and RAM B-port data outputs drive separate 4-bit latches. These latches hold the RAM data while the clock input is LOW. This eliminates any possible race conditions that could occur while new data is being written into the RAM. The high-speed Arithmetic Logic Unit (ALU) can perform three binary arithmetic and five logic operations on the two 4- bit input words R and S. The R input field is driven from a 2- input multiplexer, while S input field is driven from a 3-input multiplexer. Both multiplexers also have an inhibit capability; that is, no data is passed. This is equivalent to a “zero” source operand. The ALU R-input multiplexer has the RAM A-port and the direct data inputs (D) connected as inputs. Likewise, the ALU S-input multiplexer has the RAM A-port, the RAM B-port and the Q register connected as inputs.

FEATURES

n Fully Compatible with Industry Standard 2901 n CMOS SOS Technology n High SEU Immunity and Latch-up Free n High Speed n Low Power FEBRUARY 1995

Figure 1: Block Diagram C n OE G P C n+4 OVR F=0

In the shift up mode, the RAM3 buffer is enabled and the RAM 0 multiplexer input is enabled. Likewise, in the shift down mode, the RAM0 buffer and RAM3 input are enabled. In the no- shift mode, both buffers are in the high-impedance state and the multiplexer inputs are not selected. The shifter is controlled from the I6, I7 and I8 microinstruction inputs as defined in Figure Similarly, the Q register is driven from a 3-input multiplexer. In the non-shift mode, the multiplexer enters the ALU data into the Q register. In either the shift-up or shift-down mode, the multiplexer selects the Q register data appropriately shifted up or down. The Q shifter also has two ports; one is labeled Q0 and the other is Q3. The operation of these two ports is similar to the RAM shifter and is also controlled from I6, I7 and I8 as shown in Figure 4. The clock input shown in Figure 1 controls the RAM, the Q resister and the A and B data latches. When enabled, data is clocked into the Q register on the LOW-to-HlGH transition of the clock. When the clock input is HIGH, the A and B latches are open and will pass whatever data is present at the RAM outputs. When the clock input is LOW, the latches are closed and will retain the last data entered. If the RAM-EN is enabled new data will be written into the RAM file (word) defined by the B address field when the clock input is LOW. SOURCE OPERANDS & ALU FUNCTION Any one of eight source operand pairs can be selected by instruction inputs lo, l1 and I2 for use by the ALU; instruction inputs I3, I4, and I5 then control function selection for the ALU - five logic and three arithmetic functions. In the arithmetic mode, the carry input (Cn) also affects the ALU functions; the carry input has no effect on the ‘F’ result in the logic mode. These control parameters (I6 - l0 and Cn) are summarised in Figure 5 to completely define the ALU/source operand functions. The ALU functions can also be examined on a task basis: that is, add, subtract, AND, OR, and so on. Again, in the arithmetic mode, the carry input still affects the result, whereas in the logic mode it will not. Figures 6 and 7, respectively, define the various logic and arithmetic functions of the ALU; both carry states (Cn = 0 / Cn = 1) are defined in the function matrices. X = Don't Care. Electrically, the shift pin is a TTL input internally connected to a TRI-STATE output which is in the high-impedance state. B = Register addressed by 8 inputs. Up is towards MSB, Down is towards LSB. Figure 4: ALU Destination Control I2,1,0 Octal 0 1 2 3 4 5 6 7 Octal I5,4,3 ALU Source /ALU Function A,Q A,B 0,Q 0,B 0,A D,A D,Q D,0 C n=L R plus S C n=H A+Q A+Q+1 A+B A+B+1 Q Q +1 B B + 1 A A + 1 D + A D + A + 1 D + Q D + Q + 1 D D + 1 Cn=L S minus R C n=H Q-A-1 Q-A B-A-1 B-A Q -1 Q B - 1 B A - 1 A A - D1 A - D Q - D - 1 Q - D -D - 1 - D C n=L R minus S C n=H A-Q-1 A-Q A-B-1 A-B -Q-1 - Q - B - 1 - B - A - 1 - A D - A -1 D - A D - Q - 1 D - Q D - 1 D

3 R or S A V Q A V B Q B A D V A D V Q D

4 R and S A Λ Q A Λ B 0 0 0 D Λ A D Λ Q 0

5 RN and S AN Λ Q AN Λ B Q B A DN Λ A DN Λ Q 0

6 R EX-OR S A ∇ Q A ∇ B Q B A D ∇ A D ∇ Q D

7 R EX NOR S AN ∇ QN AN ∇ BN Q B A DN ∇ AN DN ∇ QN DN

+ = plus; - = minus; V = OR; Λ = AND; ∇ = EX-OR Figure 5: Source Operand and ALU Function Matrix Microcode RAM Function Q-Reg Function Y RAM Shifter Q Shifter I8 I7 I6 Octal Code Shift Load Shift Load Output RAM 0 RAM 3 Q 0 Q 3 L L L 0 X None None F→ Q F X X X X L L H 1 X None X None F X X X X L H L 2 None F→ B X None A X X X X L H H 3 None F→ B X None F X X X X H L L 4 Down F/2→ B Q/2→ Q F - F0 IN3 Q 0 IN3 H L H 5 Down F/2→ B X None F F0 IN3 Q 0 X H H L 6 Up 2F→ B Up 2Q → Q F IN0 F3 IN3 Q 3 H H H 7 Up 2F→ B X None F IN0 F3 X Q 3

Figure 8: Pin Description Name I/O Description A0-3 I The four address inputs to the register stack used to select one register whose contents are displayed through the A port B0-3 I The four address inputs to the register stack used to select one register whose contents are displayed through the B port and into which new data can be written when the clock goes LOW I0-8 I The nine instruction control lines. Used to determine what data sources will be applied to the ALU(I 0,1,2 ), what function the ALU will perform (I 3,4,5 ), and what data is to be deposited in the Q-register or the register stack (I6,7,8 ) Q 3 RAM 3 I/O The shift line at the MSB of the Q-register (Q3) and the register stack (RAM3). Electrically these lines are three-state outputs connected to TTL inputs internal to the device. When the destination code on I6,7,8 indicates an up shift (Octal 6 or 7) the three state outputs are enabled and the MSB of the Q-register is available on the Q3 pin and the MSB of the ALU output is available on the RAM 3 pin. Otherwise, the three state outputs are electrically OFF (high impedance) and the pins are electrically LS-TTL inputs. When the destination code calls for a down shift, the pins are used as the data inputs to the MSB of the Q-register (Octal 4) and RAM (Octal 4 or 5) Q 0 RAM 0 I/O Shift lines like Q3 and RAM 3, but at the LSB of the Q-register and RAM. These pins are tied to the Q 3 and RAM 3 pins of the adjacent device to transfer data between devices for up and down shifts of the Q-register and ALU data. D0-3 I Direct data inputs. A four-bit data field which may be selected as one of the ALU data sources for entering data into the device D0 is the LSB Y0-3 O The four data outputs. These are three-state output lines. When they are enabled, they display either the four outputs of the ALU or the data on the A-port of the register stack, as determined by the destination code I6,7,8. OEN I Output enable. When OEN is HIGH, the Y outputs are OFF; when OEN is LOW, the Y outputs are active (HIGH or LOW) GN,PN O The carry generate and propagate outputs of the internal ALU. These signals are used with the MA2901 for carry lookahead. OVR O Overflow. This pin is logically the Exclusive OR of the carry-in and carry-out of the MSB of the ALU. At the most significant end of the word, this pin indicates that the result of an arithmetic two’s complement operation has overflowed into the sign-bit F = 0 O This is an open collector output which goes HIGH(OFF) if the data on the four ALU outputs F0-3 are all LOW. In positive logic, it indicates that the result of the ALU operation is zero F3 O The most significant ALU output bit. Cn I The carry-in to the internal ALU. Cn + 4 O The carry-out of the ALU internal ALU. CP I The clock input. The Q-register and register stack outputs change on the clock LOW - to HIGH transition. The clock LOW time is internally the write enable to the 16 x 4 RAM which compromises the “master” latches of the register stack. While the clock is LOW, the “slave” latches on the RAM outputs are closed, storing the data previously on the RAM outputs. This allows synchronous master-slave operation of the register stack.

DC CHARACTERISTICS AND RATINGS Parameter Min Max Units Supply Voltage -0.5 7 V Input Voltage -0.3 VDD +0.3 V Current Through Any Pin -20 +20 mA Operating Temperature -55 125 °C Storage Temperature -65 150 °C Note: Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions, or at any other condition above those indicated in the operations section of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 9: Absolute Maximum Ratings Total dose radiation not exceeding 3x105 Rad(Si) Symbol Parameter Conditions Min Typ Max Units VDD Supply Voltage - 4.5 5.0 5.5 V VIH Input High Voltage - 2.4 - - V VIL Input Low Voltage - - - 0.8 V VOH Output High Voltage IOH = -6mA 2.4 - - V VOL Output Low Voltage IOL = 10mA - - 0.4 V IIN Input Leakage Current (Note 1) VDD = 5.5V, - - ±10 µA VIN = VSS or VDD IOZ Output Leakage Current (Note 1) VDD = 5.5V, - - ±50 µA VIN = VSS or VDD IDD Power Supply Current Static, VDD = 5.5V - 0.1 10 mA VDD = 5V±10%, over full operating temperature range. Mil-Std-883, method 5005, subgroups 1, 2, 3 Notes:1. Guaranteed but not measured at -55°C Figure 11: Operating Electrical Characteristics Subgroup Definition

1 Static characteristics specified in Figure 11 at +25°C

2 Static characteristics specified in Figure 11 at +125°C

3 Static characteristics specified in Figure 11 at -55°C

7 Functional characteristics at +25°C

8A Functional characteristics at +125°C 8B Functional characteristics at -55°C

9 Switching characteristics specified in Figures 12, 13 and 14 at +25°C

10 Switching characteristics specified in Figures 12, 13 and 14 at +125°C

11 Switching characteristics specified in Figures 12, 13 and 14 at -55°C

Figure 10: Definition of Subgroups

OUTLINES AND PIN ASSIGNMENTS Ref Millimetres Inches A1 0.38 - 1.53 0.015 - 0.060 b 0.35 - 0.59 0.014 - 0.023 c 0.20 - 0.36 0.008 - 0.014 e1 - 15.24 Typ. - - 0.600 Typ. - H 4.71 - 5.38 0.185 - 0.212 XG405 1A3 2A2 3A1 4A0 5I6 6I8 7I7 8RAM3 9RAM0 10VDD Top View 11F = 0 12I0 13I1 14I2 15CP 16Q3 17B0 18B1 19B2 20B3 40 OE 39 Y3 38 Y2 37 Y1 36 Y0 35 P

34 OVR

33 Cn+4

30 VSS

D W A e b Z H A 1 15° M E C Seating Plane 120 4021 Figure 15: 40-Lead Ceramic DIL (Solder Seal) - Package Style C

Min. Max. Min. Max. A 1.75 2.49 0.070 0.098 b 0.43 0.53 0.017 0.023 c 0.15 0.25 0.006 0.010 D 26.67 27.69 1.050 1.080 E 15.75 16.76 0.620 0.660 E1 - 17.27 - 0.630 E2 13.21 - 0.520 - E3 0.76 - 0.030 - e 1.14 1.40 0.045 0.055 L 7.87 9.40 0.310 0.370 L1 32.51 34.54 1.250 1.360 Q 0.76 1.52 0.030 0.060 S - 1.14 - 0.045 S1 0.13 - 0.005 - XG136 1I8 42 I6 2I7 41 A0 3RAM3 40 A1 4NC 39 A2 5RAM0 38 A3 6VCC 37 OE 7F=0 36 Y3 8I0 35 Y2 9I1 34 Y1 10I2 33 Y0 11CP 32 P 12NC 31 OVR 13Q3 30 Cn+4 14B0 29 G 15B1 28 F3 16B2 27 GND 17B3 26 Cn 18Q0 25 I4 19D3 24 I5 20D2 23 I3 21D1 22 D0 E L cQ A e b S D H Figure 16: 42-Lead Flatpack (Solder Seal)

Total Dose Radiation Testing For product procured to guaranteed total dose radiation levels, each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test. The sample devices will be subjected to the total dose radiation level (Cobalt-60 Source), defined by the ordering code, and must continue to meet the electrical parameters specified in the data sheet. Electrical tests, pre and post irradiation, will be read and recorded. GEC Plessey Semiconductors can provide radiation testing compliant with Mil-Std-883 method 1019 Ionizing Radiation (total dose) test.

ORDERING INFORMATION

For details of reliability, QA/QC, test and assembly options, see ‘Manufacturing Capability and Quality Assurance Standards’ Section 9. Unique Circuit Designator S R Q Radiation Hard Processing 100 kRads (Si) Guaranteed 300 kRads (Si) Guaranteed Radiation Tolerance C F Ceramic DIL (Solder Seal) Flatpack (Solder Seal) Package Type QA/QCI Process (See Section 9 Part 4) Test Process (See Section 9 Part 3) Assembly Process (See Section 9 Part 2) L C D E B S Rel 0 Rel 1 Rel 2 Rel 3/4/5/STACK Class B Class S Reliability Level MAx2901xxxxx Total Dose (Function to specification)*3x105 Rad(Si) Transient Upset (Stored data loss) 5x1010 Rad(Si)/sec Transient Upset (Survivability) >1x1012 Rad(Si)/sec Neutron Hardness (Function to specification)>1x1015 n/cm2 Single Event Upset** 1x10-10 Errors/bit day Latch Up Not possible * Other total dose radiation levels available on request ** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit Figure 17: Radiation Hardness Parameters

This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request. HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire, SN2 2QW, United Kingdom. Tel: (01793) 518000 Fax: (01793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017,

1500 Green Hills Road, Scotts Valley,

California 95067-0017, United States of America. Tel: (408) 438 2900 Fax: (408) 438 5576 CUSTOMER SERVICE CENTRES

• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07
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• ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993
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• UK, EIRE, DENMARK, FINLAND & NORWAY Swindon, UK Tel: (01793) 518527/518566 Fax: (01793) 518582 These are supported by Agents and Distributors in major countries world-wide. © GEC Plessey Semiconductors 1995 Publication No. DS3576-3.3 February 1995 TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED