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© 2011 Freescale Semiconductor, Inc. All rights reserved. This document provides an overview of the MPC8306S PowerQUICC II Pro processor features. The MPC8306S is a cost-effective, highly integrated communications processor that addresses the requirements of several networking applications, including residential gateways, modem/routers, industrial control, and test and measurement applications. The MPC8306S extends current PowerQUICC offerings, adding higher CPU performance, additional functionality, and faster interfaces, while addressing the requirements related to time-to-market, price, power consumption, and board real estate. This document describes the electrical characteristics of MPC8306S. To locate published errata or updates for this document, refer to the MPC8306S product summary page on our website listed on the back cover of this document or contact your local Freescale sales office. Document Number: MPC8306SEC Rev. 1, 09/2011
Contents
- I MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications
2 Freescale Semiconductor
1 Overview
16-bit DDR2 memory controller. communication controllers (UCCs). A block diagram of the MPC8306S is shown in the following figure. Figure 1. MPC8306S Block Diagram
3 RMII/MII2x TDM Ports
16 KB Multi-User RAM
48 KB Instruction RAM
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 Freescale Semiconductor 3 Overview In summary, the MPC8306S provides users with a highly integrated, fully programmable communications processor. This helps to ensure that a low-cost system solution can be quickly developed and offers flexibility to accommodate new standards and evolving system requirements.
1.1 Features
The major features of the device are as follows:
- e300c3 Power Architecture processor core — Enhanced version of the MPC603e core — High-performance, superscalar processor core with a four-stage pipeline and low interrupt latency times — Floating-point, dual integer units, load/store, system register, and branch processing units — 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities — Dynamic power management — Enhanced hardware program debug features — Software-compatible with Freescale proces sor families implementing Power Architecture technology — Separate PLL that is clocked by the system bus clock — Performance monitor
- QUICC Engine block — 32-bit RISC controller for flexible support of the communications peripherals with the following features: – One clock per instruction – Separate PLL for operating frequency that is independent of system’s bus and e300 core frequency for power and performance optimization – 32-bit instruction object code – Executes code from internal IRAM – 32-bit arithmetic logi c unit (ALU) data path – Modular architecture allowing for easy functional enhancements – Slave bus for CPU access of regi sters and multiuser RAM space – 48 Kbytes of instruction RAM – 16 Kbytes of multiuser data RAM – Serial DMA channel for receive and transmit on all serial channels — Five unified communication controllers (UCC s) supporting the following protocols and interfaces: – 10/100 Mbps Ethernet/IEEE Std. 802.3® through MII and RMII interfaces. – HDLC/Transparent (bit rate up to QUICC Engine operating frequency / 8) – HDLC Bus (bit rate up to 10 Mbps) – Asynchronous HDLC (bit rate up to 2 Mbps)
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
4 Freescale Semiconductor
– Two TDM interfaces supporting up to 128 QUICC multichannel controller channels, each running at 64 kbps For more information on QUICC Engine sub-modules, see QUICC Engine Block Reference Manual with Protocol Interworking.
- DDR SDRAM memory controller — Programmable timing supporting DDR2 SDRAM — Integrated SDRAM clock generation — 16-bit data interface, up to 266-MHz data rate — 14 address lines — The following SDRAM configurations are supported: – Up to two physical banks (chip selects), 256-Mbyte per chip select for 16 bit data interface. – 64-Mbit to 2-Gbit devices with x8/ x16 data ports (no direct x4 support) – One 16-bit device or two 8-bit devices on a 16-bit bus, — Support for up to 16 simultaneous open pages for DDR2 — One clock pair to support up to 4 DRAM devices — Supports auto refresh — On-the-fly power management using CKE
- Enhanced local bus controller (eLBC) — Multiplexed 26-bit addr ess and 8-/16-bit data operating at up to 66 MHz — Eight chip selects supporting eight external slaves – Four chip selects dedicated – Four chip selects offered as multiplexed option — Supports boot from parallel NOR Flash and parallel NAND Flash — Supports programmable clock ratio dividers — Up to eight-beat burst transfers — 16- and 8-bit ports, separate LWE for each 8 bit — Three protocol engines availabl e on a per chip select basis: – General-purpose chip select machine (GPCM) – Three user programmable machines (UPMs) – NAND Flash control machine (FCM) — Variable memory block sizes for FCM, GPCM, and UPM mode — Default boot ROM chip select with configurable bus width (8 or 16) — Provides two Write Enable signals to allow si ngle byte write access to external 16-bit eLBC slave devices
- Integrated programmable in terrupt controller (IPIC) — Functional and programming compatibility with the MPC8260 interrupt controller — Support for external and intern al discrete interrupt sources — Programmable highest priority request
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 Freescale Semiconductor 5 Overview — Six groups of interrupts with programmable priority — External and internal interrupt s directed to host processor — Unique vector number fo r each interrupt source
- Universal serial bus (U SB) dual-role controller — Designed to comply with Universal Serial Bus Revision 2.0 Specification — Supports operation as a stand-alone USB host controller — Supports operation as a stand-alone USB device — Supports high-speed (480-Mbps), full-speed (12-Mbps), and low-speed (1.5-Mbps) operations. Low speed is only supported in host mode.
- Dual I 2C interfaces — Two-wire interface — Multiple-master support — Master or slave I 2C mode support — On-chip digital filtering rejects spikes on the bus 2C1 can be used as the boot sequencer
- DMA Engine — Support for the DMA e ngine with the following features: – Sixteen DMA channels – All data movement vi a dual-address transfers: read from source, write to destination – Transfer control descriptor (T CD) organized to support two-deep, nested transfer operations – Channel activation via one of two methods (for both the methods, one activation per execution of the minor loop is required): – Explicit software initiation – Initiation via a channel-to-channel li nking mechanism for continuous transfers (independent channel linking at end of minor loop and/or major loop) – Support for fixed-priority and round-robin channel arbitration – Channel completion reported vi a optional interrupt requests — Support for scatter/ga ther DMA processing
- DUART — Two 2-wire interfaces (RxD, TxD) – The same can be configured as one 4-wire interface (RxD, TxD, RTS, CTS) — Programming model compat ible with the original 16450 UART and the PC16550D
- Serial peripheral interface (SPI) — Master or slave support
- Power managemnt controller (PMC) — Supports core doze/nap/sleep/ power management — Exits low power state and re turns to full-on mode when – The core internal time base unit i nvokes a request to exit low power state
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
6 Freescale Semiconductor
Electrical Characteristics
– The power management contro ller detects that the system is not idle and there are outstanding transactions on the internal bus or an external interrupt.
- Parallel I/O — General-purpose I/O (GPIO) – 56 parallel I/O pins multiple xed on various chip interfaces – Interrupt capability
- System timers — Periodic interrupt timer — Software watchdog timer — Eight general-purpose timers
- Real time clock (RTC) module — Maintains a one-second count, unique over a period of thousands of years — Two possible clock sources: – External RTC clock (RTC_PIT_CLK) – CSB bus clock
- IEEE Std. 1149.1™ compliant JTAG boundary scan
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8306S. The MPC8306S is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications.
2.1 Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1 Absolute Maximum Ratings
The following table provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings1
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 Freescale Semiconductor 7 Input voltage DDR2 DRAM signals MV IN –0.3 to (GVDD +0 . 3 ) V 3 DDR2 DRAM reference MV REF –0.3 to (GVDD +0 . 3 ) V 3 Local bus, DUART, SYS_CLK_IN, system control and power management, I2C, SPI, and JTAG signals OVIN –0.3 to (OVDD +0 . 3 ) V 4 Storage temperature range T STG – 5 5t o1 5 0 C— Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. OVDD here refers to NVDDA, NVDDB, NVDDC, NVDDF, NVDDG, and NVDDH from the ball map. 3. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 4. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. Table 1. Absolute Maximum Ratings1 (continued)
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
8 Freescale Semiconductor
2.1.2 Power Supply Voltage Specification
The following table provides the recommended operating conditions for the MPC8306S. Note that these values are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. The following figure shows the undershoot and overshoot voltages at the interfaces of the MPC8306S Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD Table 2. Recommended Operating Conditions
1.0 V ± 50 mV V 1
- GVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative
- Minimum temperature is specified with TA(Ambient Temperature); maximum temperature is specified with TJ(Junction
- OVDD here refers to NVDDA, NVDDB, NVDDC, NVDDF, NVDDG, and NVDDH from the ball map.
- tinterface refers to the clock period associated with the bus clock interface.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 Freescale Semiconductor 9
2.1.3 Output Driver Characteristics
The following table provides information on the characteristics of the output driver strengths.
2.1.4 Input Capacitance Specification
The following table describes the input capacitance for the SYS_CLK_IN pin in the MPC8306S.
2.2 Power Sequencing
The device does not require the core supply voltage (VDD) and I/O supply voltages (GVDD and OVDD) to be applied in any particular order. Note that during power ramp-up, before the power supplies are stable and if the I/O voltages are supplied before the core voltage, there might be a period of time that all input and output pins are actively driven and cause contention and excessive current. In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD) before the I/O voltage (GVDD and OVDD) and assert PORESET before the power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before the I/O supplies reach 0.7 V; see Figure 3. Once both the power supplies (I/O voltage and core voltage) are stable, wait for a minimum of 32 clock cycles before negating PORESET. NOTE There is no specific power down sequence requirement for the device. I/O voltage supplies (GVDD and OVDD) do not have any ordering requirements with respect to one another. Table 3. Output Drive Capability Table 4. Input Capacitance Specification
- The external clock generator should be able to drive 10 pF.
10 Freescale Semiconductor
Figure 3. MPC8306S Power-Up Sequencing Example
3 Power Characteristics
The typical power dissipation for this family of MPC8306S devices is shown in the following table. Table 5. MPC8306S Power Dissipation
- The values do not include I/O supply power (OV
- Typical power is based on a nominal voltage of VDD = 1.0 V, ambient temperature, and the core running a Dhrystone
benchmark application. The measurements were taken on the evaluation board using WC process silicon.
- Maximum power is based on a voltage of VDD = 1.05 V, WC process, a junction TJ = 105C, and a smoke test code.
The following table shows the estimated typical I/O power dissipation for the device.
4 Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8306S.
4.1 DC Electrical Characteristics
specifications are also applicable for QE_CLK_IN. Table 6. Typical I/O Power Dissipation
66 MHz, 26 bits
- Typical I/O power is based on a nominal voltage of VDD = 3.3V, ambient temperature, and the core running a Dhrystone
benchmark application. The measurements were taken on the evaluation board using WC process silicon. Table 7. SYS_CLK_IN DC Electrical Characteristics
12 Freescale Semiconductor
4.2 AC Electrical Characteristics
5 RESET Initialization
Table 8. SYS_CLK_IN AC Timing Specifications
- Caution: The system, core and QUICC Engine block must not exceed their respective maximum or minimum operating
- Rise and fall times for SYS_CLK_IN are measured at 0.33 and 2.97 V.
- Timing is guaranteed by design and characterization.
- This represents the total input jitter—short term and long term—and is guaranteed by design.
- The SYS_CLK_IN driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.
- Spread spectrum is allowed up to 1% down-spread @ 33kHz (max rate).
Table 9. RESET Initialization Timing Specifications
- tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN. For more details, see the MPC8306S PowerQUICC
II Pro Integrated Communications Processor Family Reference Manual.
- POR configuration signals consist of CFG_RESET_SOURCE[0:3].
The following table provides the PLL lock times.
5.1 Reset Signals DC Electrical Characteristics
MPC8306S. Note that DDR2 SDRAM is GVDD(typ) = 1.8 V .
6.1 DDR2 SDRAM DC Electrical Characteristics
of the MPC8306S when GVDD(typ) = 1.8 V. Table 10. PLL Lock Times Table 11. Reset Signals DC Electrical Characteristics
- This specification applies when operating from 3.3 V supply.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
14 Freescale Semiconductor
The following table provides the DDR2 capacitance when GVDD(typ) = 1.8 V .
6.2 DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR2 SDRAM interface.
6.2.1 DDR2 SDRAM Input AC Timing Specifications
This table provides the input AC timing specifications for the DDR2 SDRAM (GVDD(typ) = 1.8 V). The following table provides the input AC timing specifications for the DDR2 SDRAM interface.
- GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
- MVREF is expected to be equal to 0.5 GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
- VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
- Output leakage is measured with all outputs disabled, 0 V VOUT GVDD.
Table 13. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V
- This parameter is sampled. GVDD = 1.8 V ± 0.100 V, f = 1 MHz, TA =2 5° C , VOUT = GVDD 2,
VOUT (peak-to-peak) = 0.2 V. Table 14. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface At recommended operating conditions with GVDD of 1.8 V± 100mV. Table 15. DDR2 SDRAM Input AC Timing Specifications At recommended operating conditions with GVDD of 1.8V ± 100mV. Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V (continued)
The following figure shows the input timing diagram for the DDR controller. Figure 4. DDR Input Timing Diagram
6.2.2 DDR2 SDRAM Output AC Timing Specifications
The following table provides the output AC timing specifications for the DDR2 SDRAM interfaces.
266 MHz –750 750
- tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This should be subtracted from the total timing budget.
- The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
Table 16. DDR2 SDRAM Output AC Timing Specifications At recommended operating conditions with GVDD of 1.8V ± 100mV. Table 15. DDR2 SDRAM Input AC Timing Specifications (continued) At recommended operating conditions with GVDD of 1.8V ± 100mV.
16 Freescale Semiconductor
266 MHz 1100 —
- The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
- All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
- ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MDM/MDQS. For the ADDR/CMD
- Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
Manual for a description and understanding of the timing modifications enabled by use of these bits.
- Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), or data
mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
- tDDKHMP follows the symbol conventions described in note 1.
Table 16. DDR2 SDRAM Output AC Timing Specifications (continued) At recommended operating conditions with GVDD of 1.8V ± 100mV.
18 Freescale Semiconductor
7 Local Bus
7.1 Local Bus DC Electrical Characteristics
The following table provides the DC electrical characteristics for the local bus interface.
7.2 Local Bus AC Electrical Specifications
The following table describes the general timing parameters of the local bus interface of the MPC8306S. Table 17. Local Bus DC Electrical Characteristics Table 18. Local Bus General Timing Parameters
- The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
- All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
- All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 OVDD of the signal in question for 3.3-V
- Input timings are measured at the pin.
- For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
20 Freescale Semiconductor
Figure 9. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2
Figure 10. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4
8 Ethernet and MII Management
This section provides the AC and DC electrical characteristics for Ethernet interfaces.
8.1 Ethernet Controller (10/ 100 Mbps)—MII/RMII Electrical
8.1.1 DC Electrical Characteristics
22 Freescale Semiconductor
8.2 MII and RMII AC Timing Specifications
The AC timing specifications for MII and RMII are presented in this section.
8.2.1 MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.1.1 MII Transmit AC Timing Specifications
The following table provides the MII transmit AC timing specifications. Table 19. MII and RMII DC Electrical Characteristics Table 20. MII Transmit AC Timing Specifications At recommended operating conditions with OVDD of 3.3 V ± 300mV.
- The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. used with the appropriate letter: R (rise) or F (fall).
The following figure provides the AC test load. Figure 11. AC Test Load The following figure shows the MII transmit AC timing diagram. Figure 12. MII Transmit AC Timing Diagram
8.2.1.2 MII Receive AC Timing Specifications
The following table provides the MII receive AC timing specifications. Table 21. MII Receive AC Timing Specifications At recommended operating conditions with OVDD of 3.3 V ± 300mV.
- The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
with the appropriate letter: R (rise) or F (fall).
24 Freescale Semiconductor
The following figure shows the MII receive AC timing diagram. Figure 13. MII Receive AC Timing Diagram
8.2.2 RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
8.2.2.1 RMII Transmit AC Timing Specifications
The following table provides the RMII transmit AC timing specifications. The following figure provides the AC test load. Figure 14. AC Test Load Table 22. RMII Transmit AC Timing Specifications At recommended operating conditions with OVDD of 3.3 V ± 300mV.
- The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for
convention is used with the appropriate letter: R (rise) or F (fall).
The following figure shows the RMII transmit AC timing diagram. Figure 15. RMII Transmit AC Timing Diagram
8.2.2.2 RMII Receive AC Timing Specifications
The following table provides the RMII receive AC timing specifications. Table 23. RMII Receive AC Timing Specifications At recommended operating conditions with OVDD of 3.3 V ± 300mV.
- The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for
the latter convention is used with the appropriate letter: R (rise) or F (fall).
26 Freescale Semiconductor
The following figure shows the RMII receive AC timing diagram. Figure 16. RMII Receive AC Timing Diagram
8.3 Ethernet Management Interface Electrical Characteristics
8.3.1 MII Management DC El ectrical Characteristics
MDIO and MDC are provided in the following table.
8.3.2 MII Management AC El ectrical Specifications
The following table provides the MII management AC timing specifications. Table 24. MII Management DC Electrical Characteristics When Powered at 3.3 V Table 25. MII Management AC Timing Specifications At recommended operating conditions with OVDD is 3.3 V ± 300mV.
The following figure shows the MII management AC timing diagram. Figure 17. MII Management Interface Timing Diagram
- The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
latter convention is used with the appropriate letter: R (rise) or F (fall). Table 25. MII Management AC Timing Specifications (continued) At recommended operating conditions with OVDD is 3.3 V ± 300mV.
28 Freescale Semiconductor
9.1 TDM/SI DC Electrical Characteristics
The following table provides the DC electrical characteristics for the MPC8306S TDM/SI.
9.2 TDM/SI AC Timing Specifications
The following table provides the TDM/SI input and output AC timing specifications. The following figure provides the AC test load for the TDM/SI. Figure 18. TDM/SI AC Test Load Table 26. TDM/SI DC Electrical Characteristics Table 27. TDM/SI AC Timing Specifications1
- Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal.
Timings are measured at the pin.
- The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
Figure 19. TDM/SI AC Timing (External Clock) Diagram
10 HDLC
10.1 HDLC DC Electrical Characteristics
The following table provides the DC electrical characteristics for the MPC8306S HDLC protocol.
10.2 HDLC AC Timing Specifications
The following table provides the input and output AC timing specifications for HDLC protocol. Table 28. HDLC DC Electrical Characteristics Table 29. HDLC AC Timing Specifications1 Note: The clock edge is selectable on TDM/SI.
30 Freescale Semiconductor
The following figure provides the AC test load. Figure 20. AC Test Load The following figure shows the timing with external clock. Figure 21. AC Timing (External Clock) Diagram
- Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal.
Timings are measured at the pin.
- The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Table 29. HDLC AC Timing Specifications1 (continued) Note: The clock edge is selectable.
The following figure shows the timing with internal clock. Figure 22. AC Timing (Internal Clock) Diagram
11 USB
11.1 USB Controller
This section provides the AC and DC electrical specifications for the USB (ULPI) interface.
11.1.1 USB DC Electrical Characteristics
The following table provides the DC electrical characteristics for the USB interface.
11.1.2 USB AC Electrical Specifications
The following table describes the general timing parameters of the USB interface. Table 30. USB DC Electrical Characteristics Table 31. USB General Timing Parameters Note: The clock edge is selectable.
32 Freescale Semiconductor
The following figures provide the AC test load and signals for the USB, respectively. Figure 23. USB AC Test Load Figure 24. USB Signals
- The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
Table 31. USB General Timing Parameters (continued)
12 DUART
This section describes the DC and AC electrical specifications for the DUART interface of the MPC8306S.
12.1 DUART DC Electrical Characteristics
The following table provides the DC electrical characteristics for the DUART interface of the MPC8306S.
12.2 DUART AC Electrical Specifications
The following table provides the AC timing parameters for the DUART interface of the MPC8306S. Table 32. DUART DC Electrical Characteristics
- Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
Table 33. DUART AC Timing Specifications
- Actual attainable baud rate is limited by the latency of interrupt processing.
- The middle of a start bit is detected as the 8
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13 I 2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8306S.
13.1 I 2C DC Electrical Characteristics
The following table provides the DC electrical characteristics for the I2C interface of the MPC8306S.
13.2 I 2C AC Electrical Specifications
The following table provides the AC timing parameters for the I2C interface of the MPC8306S. Table 34. I2C DC Electrical Characteristics At recommended operating conditions with OVDD of 3.3 V ± 300mV.
- Output voltage (open drain or open collector) condition = 3 mA sink current.
B = capacitance of one bus line in pF.
- Refer to the MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Reference Manual for information
- I/O pins obstructs the SDA and SCL lines if OVDD is switched off.
Table 35. I2C AC Electrical Specifications All values refer to VIH (min) and VIL (max) levels (see Table 34).
36 Freescale Semiconductor
14 Timers
This section describes the DC and AC electrical specifications for the timers of the MPC8306S.
14.1 Timer DC Electrical Characteristics
TIN, TOUT, TGATE, and RTC_PIT_CLK.
14.2 Timer AC Timing Specifications
The following table provides the timer input and output AC timing specifications. The following figure provides the AC test load for the timers. Figure 27. Timers AC Test Load Table 36. Timer DC Electrical Characteristics Table 37. Timer Input AC Timing Specifications1
- Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN.
Timings are measured at the pin.
- Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by any
external synchronous logic. Timer inputs are required to be valid for at least tTIWID ns to ensure proper operation.
15 GPIO
This section describes the DC and AC electrical specifications for the GPIO of the MPC8306S.
15.1 GPIO DC Electrical Characteristics
The following table provides the DC electrical characteristics for the MPC8306S GPIO.
15.2 GPIO AC Timing Specifications
The following table provides the GPIO input and output AC timing specifications. The following figure provides the AC test load for the GPIO. Figure 28. GPIO AC Test Load Table 38. GPIO DC Electrical Characteristics
- This specification applies when operating from 3.3-V supply.
Table 39. GPIO Input AC Timing Specifications1
- Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN.
Timings are measured at the pin.
- GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation.
38 Freescale Semiconductor
16 IPIC
16.1 IPIC DC Electrical Characteristics
16.2 IPIC AC Timing Specifications
The following table provides the IPIC input and output AC timing specifications.
17 SPI
This section describes the DC and AC electrical specifications for the SPI of the MPC8306S.
17.1 SPI DC Electrical Characteristics
The following table provides the DC electrical characteristics for the MPC8306S SPI. Table 40. IPIC DC Electrical Characteristics1,2
- This table applies for pins IRQ, MCP_OUT, and QE ports Interrupts.
- MCP_OUT is open drain pins, thus VOH is not relevant for those pins.
Table 41. IPIC Input AC Timing Specifications1
- Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN.
Timings are measured at the pin.
- IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any
17.2 SPI AC Timing Specifications
The following table and provide the SPI input and output AC timing specifications. The following figure provides the AC test load for the SPI. Figure 29. SPI AC Test Load Table 42. SPI DC Electrical Characteristics Table 43. SPI AC Timing Specifications1
- Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal. Timings
- The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
- All units of output delay must be enabled for 8306S output port spimosi (SPI Master Mode)
- delay units must not be enabled for Slave Mode.
40 Freescale Semiconductor
The following figure shows the SPI timing in slave mode (external clock). Figure 30. SPI AC Timing in Slave Mode (External Clock) Diagram The following figure shows the SPI timing in master mode (internal clock). Figure 31. SPI AC Timing in Master Mode (Internal Clock) Diagram
18 JTAG
18.1 JTAG DC Electrical Characteristics
Table 44. JTAG Interface DC Electrical Characteristics Note: The clock edge is selectable on SPI. Note: The clock edge is selectable on SPI.
18.2 JTAG AC Electrical Characteristics
Table 45. JTAG AC Timing Specifications (Independent of SYS_CLK_IN)1 At recommended operating conditions (see Table 2). Table 44. JTAG Interface DC Electrical Characteristics (continued)
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The following figure provides the AC test load for TDO and the boundary-scan outputs of the MPC8306S. Figure 32. AC Test Load for the JTAG Interface The following figure provides the JTAG clock input timing diagram. Figure 33. JTAG Clock Input Timing Diagram The following figure provides the TRST timing diagram. Figure 34. TRST Timing Diagram
- All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-load (see Figure 32). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
- The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
latter convention is used with the appropriate letter: R (rise) or F (fall).
- TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
- Non-JTAG signal input timing with respect to tTCLK.
- Non-JTAG signal output timing with respect to tTCLK.
- Guaranteed by design and characterization.
Table 45. JTAG AC Timing Specifications (Independent of SYS_CLK_IN)1 (continued) At recommended operating conditions (see Table 2).
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This section details package parameters, pin assignments, and dimensions. The MPC8306S is available in a thermally enhanced MAPBGA (mold array process-ball grid array); see Section 19.1, “Package Parameters for the MPC8306S,” and Section 19.2, “Mechanical Dimensions of the MPC8306S MAPBGA,” for information on the MAPBGA.
19.1 Package Parameters for the MPC8306S
The package parameters are as provided in the following list. Package outline 19 mm 19 mm Package Type MAPBGA Interconnects 369 Pitch 0.80 mm Module height (typical) 1.48 mm; Min = 1.31mm and Max 1.61mm Solder Balls 96 Sn / 3.5 Ag / 0.5 Cu (VM package) Ball diameter (typical) 0.40 mm
19.2 Mechanical Dimensions of the MPC8306S MAPBGA
The following figure shows the mechanical dimensions and bottom surface nomenclature of the MPC8306S, 369-MAPBGA package.
Figure 37. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8306S MAPBGA
- All dimensions are in millimeters.
- Dimensions and tolerances per ASME Y14.5M-1994.
- Maximum solder ball diameter measured parallel to datum A.
- Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
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19.3 Pinout Listings
Following table shows the pin list of the MPC8306S. Table 46. MPC8306S Pinout Listing
Table 46. MPC8306S Pinout Listing (continued)
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50 Freescale Semiconductor
52 Freescale Semiconductor
- This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD
- This pin is an open drain signal. A weak pull-up resistor (2-10 kΩ) should be placed on this pin to OVDD
- This pin has weak pull-up that is always enabled.
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20 Clocking
The following figure Figure 39 shows the internal distribution of clocks within the MPC8306S. Figure 38. MPC8306S Clock Subsystem Figure 39. MPC8306S Clock Subsystem The primary clock source for MPC8306S is SYS_CLK_IN.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 Freescale Semiconductor 55 Clocking
20.1 System Clock Domains
As shown in Figure 38, the primary clock input (frequency) is multiplied up by the system phase-locked loop (PLL) and the clock unit to create four major clock domains:
- The coherent system bus clock (csb_clk)
- The QUICC Engine clock ( qe_clk)
- The internal clock for the DDR controller ( ddr_clk)
- The internal clock for the local bus controller ( lbc_clk) The csb_clk frequency is derived from the following equation: csb_clk = SYS_CLK_IN × SPMF Eqn. 1 The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL) which is loaded at power-on reset or by one of the hard-coded reset options. For more information, see the Reset Configuration chapter in the MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Reference Manual. The qe_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF]) and the QUICC Engine PLL division factor (RCWL[CEPDF]) as the following equation: qe_clk = (QE_CLK_IN × CEPMF) (1 + CEPDF) Eqn. 2 qe_clk = (QE_CLK_IN × CEPMF) (1 + CEPDF) Eqn. 3 For more information, see the QUICC Engine PLL Multiplication Factor section and the “QUICC Engine PLL Division Factor” section in the MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Reference Manual for more information. The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk. Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider (2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the same frequency as ddr_clk. The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the external local bus clock outputs (LCLK). The LBC clock divider ratio is controlled by LCRR[CLKDIV]. For more information, see the LBC Bus Clock and Clock Ratios section in the MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Reference Manual.
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register after the device comes out of reset. Integrated Communications Processor Family Reference Manual. recommended operating conditions (see Table 2).
20.2 System PLL Configuration
encodings for the system PLL. VCO frequency is in the range of 450–750 MHz. Table 47. Configurable Clock Units Table 48. Operating Frequencies for MAPBGA
- The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting
- The DDR2 data rate is 2× the DDR2 memory bus frequency.
- The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2×
the csb_clk frequency (depending on RCWL[LBCM]).
frequency for selected csb_clk to SYS_CLK_IN ratios.
20.3 Core PLL Configuration
values not listed, and should be considered reserved. Table 49. System PLL Multiplication Factors
0000 Reserved
0001 Reserved
Table 50. CSB Frequency Options Table 51. e300 Core PLL Configuration
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frequency is in the range of 400–800 MHz.
20.4 QUICC Engine PLL Configuration
following table shows the multiplication factor encodings for the QUICC Engine PLL. Table 52. QUICC Engine PLL Multiplication Factors Table 51. e300 Core PLL Configuration (continued)
QUICC Engine frequency is not restricted by the CSB and core frequencies. according to the performance requirements.
20.5 Suggested PLL Configurations
domains are independent, and each of their PLLs is configured separately. The following table shows suggested PLL configurations for 33 and 66 MHz input clocks. Table 53. QUICC Engine PLL VCO Divider
11 Reserved
Table 52. QUICC Engine PLL Multiplication Factors (continued)
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Table 54. Suggested PLL Configurations
21 Thermal
This section describes the thermal specifications of the MPC8306S.
21.1 Thermal Characteristics
21.1.1 Thermal Manage ment Information
21.1.2 Estimation of Junction Temp erature with Junction-to-Ambient
Table 55. Package Thermal Characteristics for MAPBGA
- Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
- Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
- Per JEDEC JESD51-6 with the board horizontal.
- Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
- Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
- Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
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TA = ambient temperature for the package (C) RJA = junction-to-ambient thermal resistance (C/W) PD = power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. As a general statement, the value obtained on a single layer board is appropriate for a tightly packed printed-circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Test cases have demonstrated that errors of a factor of two (in the quantity TJ – TA) are possible.
21.1.3 Estimation of Junction Te mperature with Junction-to-Board
The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal resistance. The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ =T B +( RJB PD) Eqn. 2 where: TJ = junction temperature (C) TB = board temperature at the package perimeter (C) RJB = junction-to-board thermal resistance (C/W) per JESD51-8 PD = power dissipation in package (W) When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes.
21.1.4 Experimental Determinati on of Junction Temperature
To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ =T T +( JT PD) Eqn. 3 where: TJ = junction temperature (C)
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 Freescale Semiconductor 63 Thermal TT = thermocouple temperature on top of package (C) JT = thermal characterization parameter (C/W) PD = power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
21.1.5 Heat Sinks and Juncti on-to-Case Thermal Resistance
In some application environments, a heat sink is required to provide the necessary thermal management of the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case to ambient thermal resistance as shown in the following equation: RJA =R JC +R CA Eqn. 4 where: RJA = junction-to-ambient thermal resistance (C/W) RJC = junction-to-case thermal resistance (C/W) RCA = case-to-ambient thermal resistance (C/W) RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed-circuit board, or change the thermal dissipation on the printed-circuit board surrounding the device. To illustrate the thermal performance of the devices with heat sinks, the thermal performance has been simulated with a few commercially available heat sinks. The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because there is not a standard application environment, a standard heat sink is not required. Accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the conduction cooling and the convection cooling of the air moving through the application. Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More detailed thermal models can be made available on request.
21.2 Heat Sink Attachment
When attaching heat sinks to these devices, an interface material is required. The best method is to use thermal grease and a spring clip. The spring clip should connect to the printed-circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces which would lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint
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lifetime of the package. Recommended maximum force on the top of the package is 10 lb (4.5 kg) force. If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic surfaces and its performance verified under the application requirements.
21.2.1 Experimental Determination of the Junction Temperature with a
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance using the following equation: TJ = TC +( RJC PD) Eqn. 5 where: TC = case temperature of the package (C) RJC = junction-to-case thermal resistance (C/W) PD = power dissipation (W)
22 System Design Information
This section provides electrical and thermal design recommendations for successful application of the MPC8306S.
22.1 System Clocking
The MPC8306S includes three PLLs.
- The system PLL (A V DD2) generates the system clock from the externally supplied SYS_CLK_IN input. The frequency ratio between the system and SYS_CLK_IN is selected using the system PLL ratio configuration bits as described in Section 20.2, “System PLL Configuration.”
- The e300 core PLL (A V DD3) generates the core clock as a slave to the system clock. The frequency ratio between the e300 core clock and the system clock is selected using the e300 PLL ratio configuration bits as described in Section 20.3, “Core PLL Configuration.”
- The QUICC Engine PLL (A V DD1) which uses the same reference as the system PLL. The QUICC Engine block generates or uses external sources for all required serial interface clocks.
22.2 PLL Power Supply Filtering
directly from VDD through a low frequency filter scheme such as the following. range. It should be built with surface mount capacitors with minimum effective series inductance (ESL). single large value capacitor. pin, which is on the periphery of package, without the inductance of vias. The following figure shows the PLL power supply filter circuit. Figure 41. PLL Power Supply Filter Circuit
22.3 Decoupling Recommendations
power surges and high frequency noise in its power supply, especially while driving large capacitive loads. designer place at least one decoupling capacitor at each VDD, OVDD, and GVDD pins of the MPC8306S. under the device using a standard escape pattern. Others may surround the part. capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. feeding the VDD, OVDD, and GVDD planes, to enable quick recharging of the smaller chip capacitors.
66 Freescale Semiconductor
22.4 Output Buffer DC Impedance
For all buses, the driver is a push-pull single-ended driver type (open drain for I2C). output impedance is the average of two components, the resistances of the pull-up and pull-down devices. other in value. Then, Z0 =( RP +R N)/2. Figure 42. Driver Impedance Measurement Rsource =R term (V1/V2 – 1). The drive current is then Isource =V 1/Rsource.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 Freescale Semiconductor 67
Ordering Information
The following table summarizes the signal impedance targets. The driver impedance is targeted at minimum VDD, nominal OVDD, 105C.
22.5 Configuration Pin Multiplexing
The MPC8306S provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (Refer to the “Reset, Clocking and Initialization” of MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Reference Manual). These pins are generally used as output only pins in normal operation. While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. This section presents ordering information for the devices discussed in this document, and it shows an example of how the parts are marked. Ordering information for the devices fully covered by this document is provided in Section 23.1, “Part Numbers Fully Addressed by This Document.”
23.1 Part Numbers Fully Addressed by This Document
The following table provides the Freescale part numbering nomenclature for the MPC8306S family. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the maximum processor core frequency, the part numbering scheme also includes the maximum effective DDR memory speed and QUICC Engine bus frequency. Each part number also contains a revision code which refers to the die mask revision number. Table 56. Impedance Characteristics Note: Nominal supply voltages. See Table 1, Tj = 105C.
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23.2 Part Marking
Parts are marked as in the example shown in the following figure. Figure 43. Freescale Part Marking for MAPBGA Devices The following table shows the SVR Settings. Table 57. Part Numbering Nomenclature
- Contact local Freescale office on availability of parts with C temperature range.
- See Section 19, “Package and Pin Listings,” for more information on available package types.
- Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
Table 58. SVR Settings ATWLYYWW is the traceability code. YWWLAZ is the assembly traceability code.
24 Document Revision History
The following table provides a revision history for this document. Table 59. Document Revision History 1 09/2011 • Added Power numbers for core frequency of 333 MHz in Table 5.
- Updated QUICC Engine frequency in Table 5.
- Added SPISEL_BOOT in MPC8306 Pin out Listing Table 46.
- Corrected SPISEL Pin Type in Table 46
- Updated QUICC Engine frequency from 200 MHz to 233 MHz in Table 48.
- Added new PLL configurations as per new core frequency in Table 54.
- Updated CEPMF and CEDF as per new QE frequency in Table 54.
- Added AF to indicate 333 MHz in Table 57
- Updated QE Frequency to 233 MHz in Table 57. 0 03/2011 Initial Release
Document Number: MPC8306SEC Rev. 1 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516
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