MACH211SP-7JC

MACH11SP ETC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 33

Technical content

Publication# 20405 Rev: C Amendment/0 Issue Date: August 1997 1 MACH 1 & 2 Families MACH 1 & 2 FAMILIES MACH211SP-7/10/12/15 High-Performance EE CMOS In-System Programmable Logic DISTINCTIVE CHARACTERISTICS u JTAG-Compatible, 5-V in-system programming u

44 Pins in PLCC and TQFP

u

64 Macrocells

u 7.5 ns t PD Commercial, 10 ns t PD Industrial u

133 MHz f

u

32 I/Os; 2 dedicated inputs/clocks

u

64 Flip-flops; 2 clock choices

u 4 “PALCE26V16” blocks with buried macrocells u Speed Locking™ for guaranteed fixed timing u Bus-Friendly™ Inputs and I/Os u Peripheral Component Interconnect (PCI) compliant (-7/-10/-12) u Programmable power-down mode IN-SYSTEM PROGRAMMING In-system programming allows the MACH211SP to be programmed while soldered onto a system board. Programming the MACH211SP in-system yields numerous benefits at all stages of development: prototyping, manufacturing, and in the field. Since insertion into a programmer isn’t needed, multiple handling steps and the resulting bent leads are eliminated. The design can be modified in-system for design changes and debugging while prototyping, programming boards in production, and field upgrades. The MACH211SP offers advantages with in-system programming. MACH devices have extensive routing resources for pin-out retention; design changes resulting in pin-out changes for many non-Vantis CPLDs cancel the advantages of in-system programming. The MACH211SP can be deployed in any JTAG (IEEE 1149.1) compliant chain. GENERAL DESCRIPTION The MACH211SP is a member of Vantis’ high-performance EE CMOS MACH 1 & 2 families. This device has approximately six times the logic macrocell capability of the popular PALCE22V10 without loss of speed. The MACH211SP consists of four PAL blocks interconnected by a programmable switch matrix. The four PAL blocks are essentially “PALCE26V16” structures complete with product-term arrays and programmable macrocells, which can be programmed as high speed or low power, and buried macrocells. The switch matrix connects the PAL blocks to each other and to all input pins,

2 MACH211SP-7/10/12/15

providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH211SP has two kinds of macrocell: output and buried. The MACH211SP output macrocell provides registered, latched, or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All output macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. The MACH211SP has dedicated buried macrocells which, in addition to the capabilities of the output macrocell, also provide input registers or latches for use in synchronizing signals and reducing setup time requirements. The MACH211SP is an enhanced version of the MACH211, adding the JTAG-compatible in-system programming feature. Vantis offers software design support for MACH devices through its own development system and device fitters integrated into third-party CAE tools. Platform support extends across PCs, Sun and HP workstations under advanced operating systems such as Windows 3.1, Windows 95 and NT, SunOS and Solaris, and HPUX. MACHXL software is a complete development system for the PC, supporting Vantis' MACH devices. It supports design entry with Boolean and behavioral syntax, state machine syntax and truth tables. Functional simulation and static timing analysis are also included in this easy-to-use system. This development system includes high-performance device fitters for all MACH devices. The same fitter technology included in MACHXL software is seamlessly incorporated into third-party tools from leading CAE vendors such as Synario, Viewlogic, Mentor Graphics, Cadence and MINC. Interface kits and MACHXL configurations are also available to support design entry and verification with other leading vendors such as Synopsys, Exemplar, OrCAD, Synplicity and Model Technology. These MACHXL configurations and interfaces accept EDIF 2.0.0 netlists, generate JEDEC files for MACH devices, and create industry-standard SDF, VITAL-compliant VHDL and Verilog output files for design simulation. Vantis offers in-system programming support for MACH devices through its MACHPRO software enabling MACH device programmability through JTAG compliant ports and easy-to-use PC interface. Additionally, MACHPRO generated vectors work seamlessly with HP3070, GenRad and Teradyne testers to program MACH devices or test them for connectivity. All MACH devices are supported by industry standard programmers available from a number of vendors. These programmer vendors include Advin Systems, BP Microsystems, Data I/O Corporation, Hi-Lo Systems, SMS GmbH, Stag House, and System General.

MACH 1 & 2 Families V ANTIS BLOCK DIAGRAM 20405C -1 Switch Matrix I/O Cells Macrocells I/O0–I/O7 Macrocells CLK 0/I0 CLK 1/I1 52 x 68 AND Logic Array and Logic Allocator OE I/O Cells Macrocells I/O8–I/O15 Macrocells 52 x 68 AND Logic Array and Logic Allocator OE I/O Cells Macrocells I/O24–I/O31 Macrocells 52 x 68 AND Logic Array and Logic Allocator OE I/O Cells Macrocells I/O16–I/O23 Macrocells 52 x 68 AND Logic Array and Logic Allocator OE Block A Block B 2 2 Block D Block C

4 MACH211SP-7/10/12/15

CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Block DBlock A Block B Block C 1 44 43 425 4 3 26 41 40 23 24 25 2619 20 21 2218 27 28 I/O5 I/O6 I/O7 TDI CLK0/I0 GND TCK I/O8 I/O9 I/O10 I/O11 I/O27 I/O26 I/O25 I/O24 TDO GND CLK1/I1 TMS I/O23 I/O22 I/O21 I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 20405C -2

MACH 1 & 2 Families CONNECTION DIAGRAM Top View 44-Pin TQFP PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Block B Block C Block DBlock A I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 TDO GND CLK1/I1 TMS I/O23 I/O22 I/O21 I/O5 I/O6 I/O7 TDI CLK0/I0 GND TCK I/O8 I/O9 I/O10 I/O11 20405C -3

6 MACH211SP-7/10/12/15 (Com’l)

ORDERING INFORMATION

Vantis programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: Valid Combinations The Valid Combinations table lists confi gurations planned to be supported in volume for this device. Consult the local Vantis sales of fice to confi rm availability of specifi c valid combinations and to check on newly released combinations. FAMILY TYPE MACH = Macro Array CMOS High-Speed MA CH 211 SP -7 J C DEVICE NUMBER 211 = 64 Macrocells, 44 Pins, Power-Down mode, Bus-Friendly Inputs and I/Os PRODUCT DESIGNATION SP = In-system Programmable OPERATING CONDITIONS C = Commercial (0°C to +70°C) PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) V = 44-Pin Thin Quad Flat Pack (PQT044) SPEED -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD Valid Combinations MACH211SP-7 JC, VC MACH211SP-10 MACH211SP-12 MACH211SP-15

MACH211SP-10/12/14/18 (Ind) 7 MACH 1 & 2 Families Vantis programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: Valid Combinations The Valid Combinations table lists confi gurations planned to be supported in volume for this device. Consult the local Vantis sales of fice to confi rm availability of specifi c valid combinations and to check on newly released combinations. DEVICE NUMBER 11 = 64 Macrocells, 44 Pins, Power-Down mode, Bus-Friendly Inputs and I/Os PRODUCT DESIGNATION P = In-system Programmable FAMILY TYPE MACH = Macro Array CMOS High-Speed MA CH 211 SP -10 J I OPERATING CONDITIONS I = Industrial (–40°C to +85°C) PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) SPEED -10 = 10 ns tPD -12 = 12 ns tPD -14 = 14 ns tPD -18 = 18 ns tPD Valid Combinations MACH211SP-10 JI MACH211SP-12 MACH211SP-14 MACH211SP-18

8 MACH211SP-7/10/12/15

implementation. There are two clock pins that can also be used as dedicated inputs. “PALCE26V16” with 8 buried macrocells. PAL block are initialized together. output enable; one provides asynchronous reset, and one provides asynchronous preset. software automatically configures the logic allocator when fitting the design into the device. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers. Table 1. Logic Allocation

MACH 1 & 2 Families V ANTIS The Macrocell The MACH211SP has two types of macrocell: output and buried. The output macrocells can be configured as either registered, latched, or combinatorial, with programmable polarity. The macrocell provides internal feedback whether configured with or without the flip-flop. The registers can be configured as D-type or T-type, allowing for product-term optimization. The flip-flops can individually select one of two clock/gate pins, which are also available as data inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The latch holds its data when the gate input is HIGH, and is transparent when the gate input is LOW. The flip-flops can also be asynchronously initialized with the common asynchronous reset and preset product terms. The buried macrocells are the same as the output macrocells if they are used for generating logic. In that case, the only thing that distinguishes them from the output macrocells is the fact that there is no I/O cell connection, and the signal is only used internally. The buried macrocell can also be configured as an input register or latch. The I/O Cell The I/O cell in the MACH211SP consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to all I/O cells in a PAL block. These choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus. SpeedLocking for Guaranteed Fixed Timing The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in both raw speed, but even more importantly, guaranteed fixed speed. Using the design of the central switch matrix, the MACH211SP product offers the SpeedLocking feature, which allows a stable fixed pin-to-pin delay, independent of logic paths, routing resources and design refits for up to 16 product terms per output. Other non-Vantis CPLDs incur serious timing delays as product terms expand beyond their typical 4 or 5 product-term limits. Speed and SpeedLocking combine for continuous, high performance required in today's demanding designs. In-System Programming Programming is the process where MACH devices are loaded with a pattern defined in a JEDEC file obtained from MACHXL software or third-party software. Programming is accomplished through four JTAG pins: Test Mode Select (TMS), Test Clock (TCK), Test Data In (TDI), and Test Data Out (TDO). The MACH211SP can be deployed in any JTAG (IEEE 1149.1) compliant chain. While the MACH211SP is fully JTAG compatible, it supports the BYPASS instruction, not the EXTEST and SAMPLE/PRELOAD instructions. The MACH211SP can be programmed across the commercial temperature range. Programming the MACH device after it has been placed on a circuit board is easily accomplished. Programming is initiated by placing the device into programming mode, using the MACHPRO programming software provided by Vantis. The device is bulk erased and the JEDEC file is then loaded. After the data is transferred into the device, the PROGRAM instruction is loaded.

10 MACH211SP-7/10/12/15

Bus-Friendly Inputs and I/Os The MACH211SP inputs and I/Os include two inverters in series which loop back to the input. This double inversion reinforces the state of the input and pulls the voltage away from the input threshold voltage. Unlike a pull-up, this configuration cannot cause contention on a bus. For an illustration of this configuration, please turn to the Input/Output Equivalent Schematics section. PCI Compliant The MACH211SP-7/10/12 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The MACH211SP-7/10/12’s predictable timing ensures compliance with the PCI AC specifications independent of the design. Power-Down Mode The MACH211SP features a programmable low-power mode in which individual signal paths can be programmed as low power. These low-power speed paths will be slightly slower than the non-low-power paths. This feature allows speed critical paths to run at maximum frequency while the rest of the paths operate in the low-power mode, resulting in power savings of up to 75%. If all signals in a PAL block are low-power, then total power is reduced further. On-Board Programming Options Since the MACHPRO software performs these steps automatically, the following programming options are published for reference. The configuration file, which is also known as the chain file, defines the MACH device JTAG chain. The file contains the information concerning which JEDEC file is to be placed into which device, the state which the outputs should be placed, and whether the security fuses should be programmed. The configuration file is discussed in detail in the MACHPRO software manual. The MACH211SP devices tristate the outputs during programming. They have one security bit which inhibits program and verify. This allows the user to protect proprietary patterns and designs. Program verification of a MACH device involves reading back the programmed pattern and comparing it with the original JEDEC file. The Vantis method of program verification performed on the MACH devices permits the verification of one device at a time. Accidental Programming or Erasure Protection It is virtually impossible to program or erase a MACH device inadvertently. The following conditions must be met before programming actually takes place: u The device must be in the password-protected program mode u The programming or bulk erase instruction must be in the instruction register If the above conditions are not met, the programming circuitry cannot be activated.

Figure 1. MA CH211SP P AL Block

12 MACH211SP-7/10/12/15 (Com’l)

Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposur e to Absolute Maximum Ratings for extended periods may af fect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) Supply Voltage (VCC) Operating ranges defi ne those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is measured in low-power mode with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled and reset. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL 2.4 3.3 V VOL Output LOW Voltage IOL = 16 mA, VCC = Min, VIN = VIH or VIL 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) 2.0 V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Current VIN = 5.25 V, VCC = Max (Note 2) 10 mA IIL Input LOW Current VIN = 0 V, VCC = Max (Note 2) –10 mA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 mA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –10 mA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA ICC Supply Current (Static) VCC = 5 V, TA = 25°C, f = 0 MHz (Note 4) 40 mA Supply Current (Active) VCC = 5 V, TA = 25°C, f = 1 MHz (Note 4) 45 mA

MACH211SP-7/10/12/15 (Com’l) 13 MACH 1 & 2 FamiliesCAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25°C f = 1 MHz 6 pF COUT Output Capacitance VOUT = 2.0 V 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description -7 -10 -12 -15 UnitMin Max Min Max Min Max Min Max tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) 7.5 10 12 15 ns tS Setup Time from Input, I/O, or Feedback to Clock (Note 3) D-type 5.5 6.5 7 10 ns T-type 6.5 7.5 8 11 ns tH Register Data Hold Time 0 0 0 0 ns tCO Clock to Output (Note 3) 4.5 6 8 10 ns tWL Clock Width LOW 3 5 6 6 ns tWH HIGH 3 5 6 6 ns fMAX Maximum Frequency (Note 1) External Feedback 1/(tS + tCO) D-type 100 80 66.7 50 MHz T-type 91 74 62.5 47.6 MHz Internal Feedback (fCNT) D-type 133 100 83.3 66.6 MHz T-type 125 91 76.9 62.5 MHz No Feedback 1/(tWL + tWH) 166.7 100 83.3 83.3 MHz tSL Setup Time from Input, I/O, or Feedback to Gate 5.5 6.5 7 10 ns tHL Latch Data Hold Time 0 0 0 0 ns tGO Gate to Output 7 7 10 11 ns tGWL Gate Width LOW 3 5 6 6 ns tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 9.5 12 14 17 ns tSIR Input Register Setup Time 2 2 2 2 ns tHIR Input Register Hold Time 2 2 2 2.5 ns tICO Input Register Clock to Combinatorial Output 11 13 15 18 ns tICS Input Register Clock to Output Register Setup D-type 9 10 12 15 ns T-type 10 11 13 16 ns tWICL Input Register Clock Width LOW 3 5 6 6 ns tWICH HIGH 3 5 6 6 ns fMAXIR Maximum Input Register Frequency 166.7 100 83.3 83.3 MHz tSIL Input Latch Setup Time 2 2 2 2 ns tHIL Input Latch Hold Time 2 2 2 2.5 ns tIGO Input Latch Gate to Combinatorial Output 12 14 17 20 ns

14 MACH211SP-7/10/12/15 (Com’l)

Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter. tIGOL Input Latch Gate to Output Through Transparent Output Latch 14 16 19 22 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 7.5 8.5 9 12 ns tIGS Input Latch Gate to Output Latch Setup 10 11 13 16 ns tWIGL Input Latch Gate Width LOW 3 5 6 6 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 12.5 14 16 19 ns tAR Asynchronous Reset to Registered or Latched Output 9.5 15 16 20 ns tARW Asynchronous Reset Width (Note 1) 5 10 12 15 ns tARR Asynchronous Reset Recovery Time (Note 1) 5 10 8 10 ns tAP Asynchronous Preset to Registered or Latched Output 9.5 15 16 20 ns tAPW Asynchronous Preset Width (Note 1) 5 10 12 15 ns tAPR Asynchronous Preset Recovery Time (Note 1) 5 10 8 10 ns tEA Input, I/O, or Feedback to Output Enable (Note 1) 9.5 12 15 15 ns tER Input, I/O, or Feedback to Output Disable (Note 1) 9.5 12 15 15 ns tLP tPD Increase for Powered-down Macrocell (Note 3) 10 10 10 10 ns tLPS tS Increase for Powered-down Macrocell (Note 3) 10 10 10 10 ns tLPCO tCO Increase for Powered-down Macrocell (Note 3) 0 0 0 0 ns tLPEA tEA Increase for Powered-down Macrocell (Note 3) 10 10 10 10 ns SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description -7 -10 -12 -15 UnitMin Max Min Max Min Max Min Max

MACH211SP-10/12/14/18 (Ind) 15 MACH 1 & 2 FamiliesABSOLUTE MAXIMUM RATINGS Ambient Temperature Supply Voltage with DC Output or Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposur e to Absolute Maximum Ratings for extended periods may af fect device reliability. OPERATING RANGES Industrial (I) Devices Temperature (TA) Supply Voltage (VCC) Operating ranges defi ne those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over INDUSTRIAL operating ranges Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is measured in low-power mode with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled and reset. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL 2.4 3.3 V VOL Output LOW Voltage IOL = 16 mA, VCC = Min, VIN = VIH or VIL 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) 2.0 V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 mA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –10 mA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 mA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –10 mA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA ICC Supply Current (Static) VCC = 5 V, TA = 25°C, f = 0 MHz (Note 4) 40 mA Supply Current (Active) VCC = 5 V, TA = 25°C, f = 1 MHz (Note 4) 45 mA

16 MACH211SP-10/12/14/18 (Ind)

CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25°C f = 1 MHz 6 pF COUT Output Capacitance VOUT = 2.0 V 8 pF SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) Parameter Symbol Parameter Description -10 -12 -14 -18 UnitMin Max Min Max Min Max Min Max tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) 10 12 14 18 ns tS Setup Time from Input, I/O, or Feedback to Clock D-type 6.5 8 8.5 12 ns T-type 7.5 9 10 13.5 ns tH Register Data Hold Time 0 0 0 0 ns tCO Clock to Output (Note 3) 6 7.5 10 12 ns tWL Clock Width LOW 5 6 7.5 7.5 ns tWH HIGH 5 6 7.5 7.5 ns fMAX Maximum Frequency (Note 1) External Feedback 1/(tS + tCO) D-type 80 64 53 40 MHz T-type 74 59 50 38 MHz Internal Feedback (fCNT) D-type 100 80 61.5 53 MHz T-type 91 72.5 57 44 MHz No Feedback 1/(tWL + tWH) 100 80 66.5 66.5 MHz tSL Setup Time from Input, I/O, or Feedback to Gate 6.5 8 8.5 12 ns tHL Latch Data Hold Time 0 0 0 0 ns tGO Gate to Output 8 8.5 12 13.5 ns tGWL Gate Width LOW 5 6 7.5 7.5 ns tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 12 14.5 17 20.5 ns tSIR Input Register Setup Time 2 2.5 2.5 2.5 ns tHIR Input Register Hold Time 2 3 3 3.5 ns tICO Input Register Clock to Combinatorial Output 13 16 18 22 ns tICS Input Register Clock to Output Register Setup D-type 10 12 14.5 18 ns T-type 11 13 16 19.5 ns tWICL Input Register Clock Width LOW 5 6 7.5 7.5 ns tWICH HIGH 5 6 7.5 7.5 ns fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH) 100 80 66.5 66.5 MHz tSIL Input Latch Setup Time 2 2.5 2.5 2.5 ns

MACH211SP-10/12/14/18 (Ind) 17 MACH 1 & 2 Families V ANTIS Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit for test conditions. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter. tHIL Input Latch Hold Time 2 3 3 3.5 ns tIGO Input Latch Gate to Combinatorial Output 14 17 20.5 24 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 16 19.5 23 26.5 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 8.5 10.5 11 14.5 ns tIGS Input Latch Gate to Output Latch Setup 11 13.5 16 19.5 ns tWIGL Input Latch Gate Width LOW 5 6 7.5 7.5 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 14 17 19.5 23 ns tAR Asynchronous Reset to Registered or Latched Output 15 19.5 19.5 24 ns tARW Asynchronous Reset Width (Note 1) 10 12 14.5 18 ns tARR Asynchronous Reset Recovery Time (Note 1) 10 10 10 12 ns tAP Asynchronous Preset to Registered or Latched Output 15 18 19.5 24 ns tAPW Asynchronous Preset Width (Note 1) 10 12 14.5 18 ns tAPR Asynchronous Preset Recovery Time (Note 1) 10 10 10 12 ns tEA Input, I/O, or Feedback to Output Enable (Note 1) 15 15 14.5 18 ns tER Input, I/O, or Feedback to Output Disable (Note 1) 15 15 14.5 18 ns tLP tPD Increase for Powered-down Macrocell (Note 3) 10 10 10 10 ns tLPS tS Increase for Powered-down Macrocell (Note 3) 10 10 10 10 ns tLPCO tCO Increase for Powered-down Macrocell (Note 3) 0 0 0 0 ns tLPEA tEA Increase for Powered-down Macrocell (Note 3) 10 10 10 10 ns SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) Parameter Symbol Parameter Description -10 -12 -14 -18 UnitMin Max Min Max Min Max Min Max

18 MACH211SP-7/10/12/15

TYPICAL CURRENT vs. VOLTAGE (I-V) CHARACTERISTICS VCC = 5.0 V, TA = 25°C -20 -40 -60 -80 20405C -5Output, LOW VOL (V) IOL (mA) 20405C -6Output, HIGH IOH (mA) VOH (V) -50 -75 -100 -3 -2 -1 1 2 3 -25 -125 -150 4 5 20405C -7 Input II (mA) VI (V) -40 -60 -80 -2 -1 1 2 3 -20 4 5 -100

MACH 1 & 2 Families V ANTIS TYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25°C The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. High Speed 150 125 100 0 10 20 30 40 50 60 70 80 90 ICC (mA) Frequency (MHz) Low Pow er 100 110 120 130 140 150 20405C -8

20 MACH211SP-7/10/12/15

TYPICAL THERMAL CHARACTERISTICS Measured at 25°C ambient. These parameters are not tested. Plastic qjc Considerations The data listed for plastic qjc are for r eference only and ar e not r ecommended for use in calculating junction temperatur es. The heat-flow paths in plastic- encapsulated devices ar e complex, making the qjc measur ement r elative to a specifi c location on the package surface. Tests indicate this measur ement reference point is dir ectly below the die-attach area on the bottom center of the package. Furthermore, qjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar envir onment. The thermal measurements are taken with components on a six-layer printed circuit board. SWITCHING WAVEFORMS Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. Parameter Symbol Parameter Description Typ UnitTQFP PLCC qjc Thermal impedance, junction to case 11 4 °C/W qja Thermal impedance, junction to ambient 41 30 °C/W qjma Thermal impedance, junction to ambient with air flow 200 lfpm air 35 19 °C/W 400 lfpm air 34 16 °C/W 600 lfpm air 33 14 °C/W 800 lfpm air 32 13 °C/W 20405C -9 Combinatorial Output tPD Input, I/O, or Feedback Combinatorial Output VT VT 20405C -10 20405C -11 Registered Output Latched Output VT Input, I/O, or Feedback Registered Output tS tCO VT tH VTClock tPDL Input, I/O, or Feedback Latched Out Gate VT tHLtSL tGO VT VT

MACH 1 & 2 Families V ANTIS SWITCHING WAVEFORMS Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. 20405C -12 20405C -13 Clock Width Gate Width tWH Clock tWL Gate tGWL VT 20405C -14 20405C -15 Registered Input Input Register to Output Register Setup VT Combinatorial Output tSIR tICO VT tHIR VT Input Register Clock Registered Input VT VT VT tICSOutput Register Clock Input Register Clock Registered Input 20405C -16 Latched Input Combinatorial Output Gate tHILtSIL tIGO Latched In VT VT VT

22 MACH211SP-7/10/12/15

Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. 20405C -17 Latched Input and Output Latched In Output Latch Gate Latched Out tSLL tPDLL tIGOL tIGS Input Latch Gate VT VT VT 20405C -18 20405C -19 Input Register Clock Width Input Latch Gate Width tWICH Clock VT tWICL Input Latch Gate tWIGL VT

MACH 1 & 2 Families V ANTIS SWITCHING WAVEFORMS Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. 20405C -20 20405C -21 Asynchronous Reset Asynchronous Preset VT VT tARW VT tAR Input, I/O, or Feedback Registered Output or Latched Output Clock or Input Latch Gate tARR Input, I/O, or Feedback VT VT tAPW VT tAP tAPR Registered Output or Latched Output Clock or Input Latch Gate 20405C -22 Output Disable/Enable VT VTOutputs tER tEA VOH – 0.5 V VOL + 0.5 V Input, I/O, or Feedback

24 MACH211SP-7/10/12/15

KEY TO SWITCHING WAVEFORMS SWITCHING TEST CIRCUIT* * Switching several outputs simultaneously should be avoided for accurate measurement. Specification S1 C L Commer cial Measured Output ValueR1 R 2 tPD, tCO Closed 35 pF

300 W 390 W

1.5 V tEA Z fi H: Open Z fi L: Closed tER H fi Z: Open L fi Z: Closed 5 pF H fi Z: VOH – 0.5 V L fi Z: VOL + 0.5 V Must be Steady Ma y Change from H to L Ma y Change from L to H Does Not Apply Don’t Care, Any Change Permitted Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is High- Impedance “Off” State WAVEFORM INPUTS OUTPUTS KS000010-PAL 20405C -23 C L Output R 1 R 2 Test Point 5 V

MACH 1 & 2 Families V ANTIS fMAX PARAMETERS The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated “fMAX external.” The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is designated “fMAX internal”. A simple internal counter is a good example of this type of design; therefore, this parameter is sometimes called “fCNT.” The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (tS + tH). However, a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum clock period determines the period for the third fMAX, designated “fMAX no feedback.” For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this involves no feedback, it is calculated the same way as fMAX no feedback. The minimum period will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that fMAXIR is specified as 1/(tWICL + tWICH). Note that if both input and output registers are used in the same path, the overall frequency will be limited by tICS. All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX internal is measured directly. LOGIC REGISTER CLK LOGIC REGISTER CLK tCOtS tS tS fMAX Internal (fCNT ) fMAX External 1/(ts + tCO ) LOGIC REGISTER CLK fMAX No Feedback; 1/(ts + tH ) or 1/(tWH + tWL ) (SECOND CHIP) REGISTER LOGIC CLK fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH ) tSIR tHIR 20405C -24

26 MACH211SP-7/10/12/15

The MACH families are manufactured using Vantis’ advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Endurance Characteristics INPUT/OUTPUT EQUIVALENT SCHEMATICS Parameter Symbol Parameter Description Units Test Conditions tDR Min Pattern Data Retention Time

10 Years Max Storage Temperature

20 Years Max Operating Temperature

N Max Reprogramming Cycles 100 Cycles Normal Programming Conditions 20405C -25 VCC ESD Protection 1 kW Input VCC 100 kW Preload Circuitry Feedback Input I/O VCCVCC 100 kW 1 kW

MACH 1 & 2 Families V ANTIS POWER-UP RESET The MACH devices have been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Symbol Parameter Descriptions Max Unit tPR Power-Up Reset Time 10 ms tS Input or Feedback Setup Time See Switching Characteristics tWL Clock Width LOW 20405C -26 Power-Up Reset Waveform tPR tWL tS 4 V VCC Pow er Registered Output Clock

28 MACH211SP-7/10/12/15

DEVELOPMENT SYSTEMS (subject to change) For more information on the products listed below, please consult the local Vantis sales office. MANUF ACTURER SOFTW ARE DEVELOPMENT SYSTEMS Vantis Corporation P.O. Box 3755

920 DeGuigne Drive

Sunnyvale, CA 94088 (408) 732-0555 or 1(888) 826-8472 (VANTIS2) http://www.vantis.com MACHXL Software Vantis-ABEL Software Vantis-Synario Software Aldec, Inc.

3 Sunset Way, Suite F

Henderson, NV 89014 (702) 456-1222 or (800) 487-8743 ACTIVE-CAD Cadence Design Systems

555 River Oaks Pkwy

San Jose, CA 95134 (408) 943-1234 or (800) 746-6223 PIC Designer Concept/Composer Synergy Leapfrog/Verilog-XL Exemplar Logic, Inc.

815 Atlantic Avenue, Suite 105

Alameda, CA 94501 (510) 337-3700 Leonardo™ Galileo™ Logic Modeling 19500 NW Gibbs Dr. P.O. Box 310 Beaverton, OR 97075 (800) 346-6335 SmartModel ® Library Mentor Graphics Corp. 8005 S.W. Boeckman Rd. Wilsonville, OR 97070-7777 (800) 547-3000 or (503) 685-7000 Design Architect, PLDSynthesis™ II Autologic II Synthesizer, QuickSim Simulator, QuickHDL Simulator MicroSim Corp.

20 Fairbanks

Irvine, CA 92718 (714) 770-3022 MicroSim Design Lab PLogic, PLSyn MINC Inc.

6755 Earl Drive, Suite 200

Colorado Springs, CO 80918 (800) 755-FPGA or (719) 590-1155 PLDesigner-XL™ Softwar e Model Technology 8905 S.W. Nimbus Avenue, Suite 150 Beaverton, OR 97008 (503) 641-1340 V-System/VHDL OrCAD, Inc. 9300 S.W. Nimbus Avenue Beaverton, OR 97008 (503) 671-9500 or (800) 671-9505 OrCAD Express Synario ® Design Automation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 332-8246 or (206) 881-6444 ABEL™ Synario™ Softwar e

MACH 1 & 2 Families V ANTIS Vantis is not responsible for any information relating to the products of third parties. The inclusion of such information is not a rep- resentation nor an endorsement by Vantis of these products. Synopsys 700 E. Middlefield Rd. Mountain View, CA 94040 (415) 962-5000 or (800) 388-9125 FPGA or Design Compiler (Requires MINC PLDesigner-XL™) VSS Simulator Synplicity, Inc. 624 East Evelyn Ave. Sunnyvale, CA 94086 (408) 617-6000 Synplify Teradyne EDA 321 Harrison Ave. Boston, MA 02118 (800) 777-2432 or (617) 422-2793 MultiSIM Interactive Simulator LASAR VeriBest, Inc.

6101 Lookout Road, Suite A

Boulder, CO 80301 (800) 837-4237 VeriBest PLD Viewlogic Systems, Inc.

293 Boston Post Road West

Marlboro, MA 01752 (800) 873-8439 or (508) 480-0881 Viewdraw, ViewPLD, Viewsynthesis Speedwave Simulator, ViewSim Simulator, VCS Simulator MANUF ACTURER TEST GENERA TION SYSTEM Acugen Software, Inc. 427-3 Amherst St., Suite 391 Nashua, NH 03063 (603) 881-8821 ATGEN™ T est Generation Software iNt GmbH Busenstrasse 6 D-8033 Martinsried, Munich, Germany (87) 857-6667 PLDCheck 90 MANUF ACTURER SOFTW ARE DEVELOPMENT SYSTEMS

30 MACH211SP-7/10/12/15

APPROVED PROGRAMMERS (subject to change) For more information on the products listed below, please consult the local Vantis sales office. MANUF ACTURER PR OGRAMMER CONFIGURA TION Advin Systems, Inc. 1050-L East Duane Ave. Sunnyvale, CA 940 86 (408) 243-7000 or (800) 627-2456 BBS (408) 737-9200 Fax (408) 736-2503 Pilot-U40 Pilot-U84 MVP BP Microsystems 1000 N. Post Oak Rd., Suite 225 Houston, TX 77055-7237 (800) 225-2102 or (713) 688-4600 BBS (713) 688-9283 Fax (713) 688-0920 BP1200 BP1400 BP2100 BP2200 Data I/O Corporation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 426-1045 or (206) 881-6444 BBS (206) 882-3211 Fax (206) 882-1043 UniSite™ Model 2900 Model 3900 AutoSite Hi-Lo Systems 4F, No. 2, Sec. 5, Ming Shoh E. Road Taipei, Taiwan (886) 2-764-0215 Fax (886) 2-756-6403 or Tribal Microsystems / Hi-Lo Systems 44388 South Grimmer Blvd. Fremont, CA 94538 (510) 623-8859 BBS (510) 623-0430 Fax (510) 623-9925 ALL-07 FLEX-700 SMS GmbH Im Grund 15

88239 Wangen

(49) 7522-97280 Fax (49) 7522-972850 or SMS USA 544 Weddell Dr. Suite 12 Sunnyvale, CA 94089 (408) 542-0388 Sprint Expert Sprint Optima Multisite Stag House Silver Court Watchmead, Welwyn Garden City Herfordshire UK AL7 1LT 44-1-707-332148 Fax 44-1-707-371503 Stag Quazar

MACH 1 & 2 Families V ANTIS APPROVED ADAPTER MANUFACTURERS APPROVED ON-BOARD ISP PROGRAMMING TOOLS System General 1603A South Main Street Milpitas, CA 95035 (408) 263-6667 BBS (408) 262-6438 Fax (408) 262-9220 or 3F, No. 1, Alley 8, Lane 45 Bao Shing Road, Shin Diau Taipei, Taiwan (886) 2-917-3005 Fax (886) 2-911-1283 Turpro-1 Turpro-1/FX Turpro-1/TX MANUF ACTURER PR OGRAMMER CONFIGURA TION California Integration Coordinators, Inc.

656 Main Street

Placerville, CA 95667 (916) 626-6168 Fax (916) 626-7740 MACH/PAL Programming Adapters Emulation Technology, Inc. 2344 Walsh Ave., Bldg. F Santa Clara, CA 95051 (408) 982-0660 Fax (408) 982-0664 Adapt-A-Socket Programming Adapters MANUF ACTURER PR OGRAMMER CONFIGURA TION Corelis, Inc.

12607 Hidden Creek Way, Suite H

Cerritos, California 70703 (310) 926-6727 JTAGPROG™ Vantis Corporation P.O. Box 3755 Sunnyvale, CA 94088 (408) 732-0555 or 1(888) 826-8472 (VANTIS2) http://www.vantis.com MACHPRO MANUF ACTURER PR OGRAMMER CONFIGURA TION

32 MACH211SP-7/10/12/15

44-Pin Plastic Leaded Chip Carrier (measured in inches) TOP VIEW SEATING PLANE .685 .695 .650 .656Pin 1 I.D. .685 .695 .650 .656 .026 .032 .050 REF .042 .056 .062 .083 .013 .021 .590 .630 .500 REF .009 .015 .165 .180 .090 .120 16-038-SQ PL 044 DA78 6-28-94 ae SIDE VIEW

MACH 1 & 2 Families V ANTIS PHYSICAL DIMENSIONS PQT044 44-Pin Thin Quad Flat Pack (measured in millimeters) Trademarks Copyright © 1997 Advanced Micr o Devices, Inc. All rights r eserved. AMD, Vantis, the Vantis logo and combinations ther eof, SpeedLocking and Bus-Friendly ar e trademarks, MACH, MACHXL, MACHPRO and P AL are registered trademarks of Advanced Micr o Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 1.00 REF.

1.20 MAX

11° – 13° 11° – 13°

0.80 BSC

0.95 1.05 11.80 12.20 9.80 10.20 11.80 12.20 9.80 10.20 0.30 0.45 16-038-PQT-2 PQT 44 7-11-95 ae