MAC8S ONSEMI | Alldatasheet

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Technical content

Features

  • Sensitive Gate Allows Triggering by Microcontrollers and other Logic Circuits
  • Uniform Gate Trigger Currents in Three Quadrants; Q1, Q2, and Q3
  • High Immunity to dv/dt − 25 V//C0109s Minimum at 110°C
  • High Commutating di/dt − 8.0 A/ms Minimum at 110°C
  • Maximum Values of IGT, VGT and IH Specified for Ease of Design
  • On-State Current Rating of 8 Amperes RMS at 70°C
  • High Surge Current Capability − 70 Amperes
  • Blocking V oltage to 800 V olts
  • Rugged, Economical TO−220AB Package
  • Pb−Free Packages are Available* MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Peak Repetitive Off−State Voltage (Note 1) (TJ = −40 to 110°C, Sine Wave, 50 to 60 Hz, Gate Open) MAC8SD MAC8SM MAC8SN VDRM, VRRM 400 600 800 V On-State RMS Current (Full Cycle Sine Wave, 60 Hz, T C = 70°C) IT(RMS) 8.0 A Peak Non-Repetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, T J = 110°C) ITSM 70 A Circuit Fusing Consideration (t = 8.3 ms) I2t 20 A2sec Peak Gate Power (Pulse Width ≤ 1.0 /C0109s, TC = 70°C) PGM 16 W Average Gate Power (t = 8.3 ms, TC = 70°C) PG(AV) 0.35 W Operating Junction Temperature Range TJ −40 to +110 °C Storage Temperature Range Tstg −40 to +150 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. V DRM and VRRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. TRIACS

8 AMPERES RMS

TO−220AB CASE 221A−09 STYLE 4 http://onsemi.com MAC8SxG AYWW MARKING DIAGRAM x = D, M, or N A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package 2 3 Preferred devices are recommended choices for future use and best overall value. Device Package Shipping

ORDERING INFORMATION

MAC8SD TO−220AB 50 Units / Rail MAC8SN TO−220AB 50 Units / Rail MAC8SDG TO−220AB (Pb−Free)

50 Units / Rail

MAC8SNG TO−220AB (Pb−Free) MAC8SM TO−220AB 50 Units / Rail MAC8SMG TO−220AB (Pb−Free) G MT2 PIN ASSIGNMENT

3 Gate

4 Main Terminal 2

MAC8SD, MAC8SM, MAC8SN http://onsemi.com THERMAL CHARACTERISTICS Characteristic Symbol Value Unit Thermal Resistance, Junction−to−Case Junction−to−Ambient R/C0113JC R/C0113JA 2.2 62.5 °C/W Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds TL 260 °C ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted; Electricals apply in both directions) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) T J = 25°C TJ = 110°C IDRM, IRRM − 0.01 2.0 mA ON CHARACTERISTICS Peak On-State Voltage (Note ) (ITM = /C000611A) VTM − − 1.85 V Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 /C0087) MT2(+), G(+) MT2(+), G(−) MT2(−), G(−) IGT 2.0 3.0 3.0 5.0 5.0 5.0 mA Holding Current (VD = 12V, Gate Open, Initiating Current = /C0006150mA) IH − 3.0 10 mA Latching Current (VD = 24V, IG = 5mA) MT2(+), G(+) MT2(−), G(−) MT2(+), G(−) IL 5.0 5.0 mA Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100/C0087) MT2(+), G(+) MT2(+), G(−) MT2(−), G(−) VGT 0.45 0.45 0.45 0.62 0.60 0.65 1.5 1.5 1.5 V DYNAMIC CHARACTERISTICS Rate of Change of Commutating Current VD = 400 V, ITM = 3.5 A, Commutating dv/dt = 10 V /C0109/sec, Gate Open, TJ = 110°C, f = 500 Hz, Snubber: CS = 0.01 /C0109F, RS =15 /C0087, See Figure 16.) di/dt(c) 8.0 10 − A/ms Critical Rate of Rise of Off-State Voltage (VD = Rate VDRM, Exponential Waveform, RGK = 510 /C0087, TJ = 110°C) dv/dt 25 75 − V//C0109s 2. Indicates Pulse Test: Pulse Width ≤ 2.0 ms, Duty Cycle ≤ 2%.

MAC8SD, MAC8SM, MAC8SN http://onsemi.com + Current + Voltage VTM IH Symbol Parameter VDRM Peak Repetitive Forward Off State Voltage IDRM Peak Forward Blocking Current VRRM Peak Repetitive Reverse Off State Voltage IRRM Peak Reverse Blocking Current Voltage Current Characteristic of Triacs (Bidirectional Device) IDRM at VDRM on state off state IRRM at VRRM Quadrant 1 MainTerminal 2 + Quadrant 3 MainTerminal 2 − VTM IH VTM Maximum On State Voltage IH Holding Current MT1 (+) IGT GATE (+) MT2 REF MT1 (−) IGT GATE (+) MT2 REF MT1 (+) IGT GATE (−) MT2 REF MT1 (−) IGT GATE (−) MT2 REF MT2 NEGATIVE (Negative Half Cycle) MT2 POSITIVE (Positive Half Cycle) Quadrant III Quadrant IV Quadrant II Quadrant I Quadrant Definitions for a Triac IGT − + IGT All polarities are referenced to MT1. With in−phase signals (using standard AC lines) quadrants I and III are used.

Figure 7. Typical Gate Trigger Current Versus Figure 8. Typical Gate Trigger Voltage Versus Figure 9. Typical Exponential Static dv/dt Versus Figure 10. Typical Exponential Static dv/dt Versus Figure 11. Typical Exponential Static dv/dt Versus Figure 12. Typical Exponential Static dv/dt Versus

600 V800 V

Figure 13. Typical Exponential Static dv/dt Versus Figure 14. Typical Exponential Static dv/dt Versus Figure 15. Critical Rate of Rise of Figure 16. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Current (di/dt)c

200 VRMS

Note: Component values are for verification of rated (di/dt) c. See AN1048 for additional information.

MAC8SD, MAC8SM, MAC8SN http://onsemi.com PACKAGE DIMENSIONS TO−220AB CASE 221A−09 ISSUE AA NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.570 0.620 14.48 15.75 B 0.380 0.405 9.66 10.28 C 0.160 0.190 4.07 4.82 D 0.025 0.035 0.64 0.88 F 0.142 0.147 3.61 3.73 G 0.095 0.105 2.42 2.66 H 0.110 0.155 2.80 3.93 J 0.018 0.025 0.46 0.64 K 0.500 0.562 12.70 14.27 L 0.045 0.060 1.15 1.52 N 0.190 0.210 4.83 5.33 Q 0.100 0.120 2.54 3.04 R 0.080 0.110 2.04 2.79 S 0.045 0.055 1.15 1.39 T 0.235 0.255 5.97 6.47 U 0.000 0.050 0.00 1.27 B Q H Z L V G N A K F 12 3 D SEATING PLANE−T− C ST U R J STYLE 4: PIN 1. MAIN TERMINAL 1 2. MAIN TERMINAL 2 3. GATE 4. MAIN TERMINAL 2 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 MAC8S/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.