MAC7121VVF50

MAC7100 FREESCALE | Alldatasheet

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• Preliminary Freescale Semiconductor Advance Information MAC7100EC Rev. 1.2, 02/2006 This document contains information on a new product under development. Freescale Semiconductor reserves the right to change or discontinue this product without notice. Table of Contents 3.6 Power Dissipation and Thermal Characteristics..8 MAC7100 Microcontroller Family Hardware Specifications Covers MAC7101, MAC7106, MAC7111, MAC7116, MAC7121, MAC7126, MAC7131, MAC7136, MAC71411 32-bit Embedded Controller Division 1. With preliminary information on MAC7112, MAC7122, MAC7142 devices. This document provides electrical specifications, pin assignments, and package diagrams for MAC7100 family of microcontroller devices. For functional characteristics, refer to the MAC7100 Microcontroller Family Reference Manual (MAC7100RM).

1 Overview

The MAC7100 Family of microcontrollers (MCUs) are members of a pin-compatible family of 32-bit Flash-memory-based devices developed specifically for embedded automotive applications. The pin-compatible family concept enables users to select between different memory and peripheral options for scalable designs. All MAC7100 Family members are composed of a 32-bit ARM7TDMI-S™ central processi ng unit, up to 1 Mbyte of embedded Flash EEPROM for program storage, up to

32 Kbytes of embedded Flash for data and/or program

storage, and up to 48 Kbytes of RAM. The family is implemented with an enhanced DMA (eDMA) controller to improve performance for transfers between memory and many of the on-chip peripherals. The peripheral set includes asynchronous serial communications interfaces (eSCI), serial peripheral interfaces (DSPI),

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary

Ordering Information

inter-integrated circuit (I2C™) bus controllers, FlexCAN interfaces , an enhanced modular I/O subsystem (eMIOS), 10-bit analog-to-digital converter (ATD) module(s), general-purpose timers (PIT) and two special-purpose timers (RTI and SWT). The peripherals share a large number of general purpose input-output (GPIO) pins, all of which are bidirectional and available with interrupt capability to trigger wake-up from low-power chip modes. Refer to Table 2 for a comparison of family members and availability of peripheral modules on each device. The use of a PLL allows power drain and performance to be balanced to best fit requirements. The operating frequency of devices in the family is up to a maximum of 50 MHz. The internal data paths between the CPU core, eDMA, memory and peripherals are all 32 bits wide, further improving performance for 32-bit applications. The MAC7111, MAC7116, MAC7131 and MAC7136 also offer a 16-bit wide external data bus with 22 address lines. The family of devices is capable of operating over a junction temperature range of –40° C to 150° C.

2 Ordering Information

Figure 1. Order Part Number Example optional numerical digit preceding the standard four-character code, for example 0L49P. Table 1. MAC7100 Family Mask Set to Part Number Correspondence

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 PreliminaryFreescale Semiconductor 3 Table 2. MAC7100 Family Device Derivatives

1. 16 channels, 8/10-bit, per module.
2. Four additional chip selects available.
3. PB11 / PCS2_B not available on non-L49P-mask devices; PB10 / PCS5_B / PCSS_B not available on mask L47W devices.
4. Reduce these values by one for mask set L49P devices (PD2 is not available for general-purpose use).

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary

Electrical Characteristics

3 Electrical Characteristics

This section contains electrical information for MAC7100 Family microcontrollers. The information is preliminary and subject to change without notice. MAC7100 Family devices are specified and tested over the 5 V and 3.3 V ranges. For operation at any voltage within that range, the 3.3 V specifications generally apply. However, no production testing is done to verify operation at intermediate supply voltage levels.

3.1 Parameter Classification

The electrical parameters shown in this appendix are derived by various methods. To provide a better understanding to the designer, the following classification is used. Parameters are tagged accordingly in the column labeled “C” of the parametric tables, as appropriate.

3.2 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only. Functional operation outside these maximums is not guaranteed. Stress beyond these limits may affect reliability or cause permanent damage to the device. MAC7100 Family devices contain circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either VSS51 or VDD51). Table 3. Parametric Value Classification P Parameters guaranteed during production testing on each individual device. (unless otherwise noted). All values shown in the typical column are within this classification, even if not so tagged. D Parameters derived mainly from simulations.

1. Refer to Section 3.7, “Power Supply,” for definition of VSS5 and VDD5.

Table 4. Absolute Maximum Ratings

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 PreliminaryFreescale Semiconductor 5

3.3 ESD Protection and Latch-up Immunity

All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise. A9 Voltage difference V DDA – VRH VDDA – VRH –0.3 +6.0 V A10 Digital I/O Input Voltage V IN –0.3 +6.0 V A11 XFC, EXTAL, XTAL inputs V ILV –0.3 +3.0 V A12 TEST input V TEST –0.3 — 2 V Instantaneous Maximum Current 3 A13 Single pin limit for XFC, EXTAL, XTAL 4 IDL –25 +25 mA A14 Single pin limit for all digital I/O pins 5 ID –25 +25 mA A15 Single pin limit for all analog input pins 5 IDA –25 +25 mA A16 Single pin limit for TEST 2 IDT –0.25 0 mA A17 Storage Temperature Range T stg –65 +155 °C NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply from the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 2. This pin is clamped low to VSSX, but not clamped high, and must be tied low in applications. 3. Input must be current limi ted to the value specified. To determine the value of the required current-limiting resistor, use the larger of the calculated values using VPOSCLAMP = VDDA + 0.3V and VNEGCLAMP = –0.3 V. 4. These pins are internally clamped to V SSPLL and VDDPLL. 5. All I/O pins are internally clamped to V SSX and VDDX, VSSR and VDDR or VSSA and VDDA. Table 5. ESD and Latch-up Test Conditions Table 4. Absolute Maximum Ratings (continued)

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary

3.4 Operating Conditions

Unless otherwise noted, the following conditions apply to all parametric data. Refer to the temperature rating of the device (C, V , M) with respect to ambient temperature (TA) and junction temperature (TJ). For power dissipation calculations refer to Section 3.6, “Power Dissipation and Thermal Characteristics.”

3.4.1 Input/Output Pins

The I/O pins operate at a nominal level of 3.3 V to 5 V . This class of pins is comprised of the clocks, control and general purpose/peripheral pins. The internal structure of these pins is identical; however, some functionality may be disabled (for example, for analog inputs the output drivers, pull-up/down resistors are permanently disabled). Table 6. ESD and Latch-Up Protection Characteristics Table 7. MAC7100 Family Device Operating Conditions

1. These ratings apply only when the VREG is disabled and the device is powered from an external source.
2. Throughout this document, t OSC refers to 1 ÷ fOSC, and tSYS refers to 1 ÷ fSYS.
3. Refer to Section 3.6, “Power Dissipation and Thermal Characteristics,” for more details about the relation between

ambient temperature TA and device junction temperature TJ.

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 PreliminaryFreescale Semiconductor 7

3.4.2 Oscillator Pins

The pins XFC, EXTAL, XTAL are dedicated to the oscillator and operate at a nominal level of 2.5V .

3.5 Input/Output Characteristics

This section describes the characteristics of all I/O pins in both 3.3 V and 5 V operating conditions. All parameters are not always applicable; for example, not all pins feature pull up/down resistances. Table 8. 5.0 V I/O Characteristics

1. Refer to Section 3.7, “Power Supply,” for definition of VSS5 and VDD5.
2. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half

for each 8°C to 12°C in the temperature range from 50°C to 125°C.

1. Refer to Section 3.7.1, “Current Injection,” for more details
2. Parameter only applies in STOP or Pseudo STOP mode.

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary

3.6 Power Dissipation and Thermal Characteristics

Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. Table 9. 3.3 V I/O Characteristics Conditions shown in Table 7, with VDDX = 3.3 V –5%/+10% and a temperature maximum of +140°C unless otherwise noted.

1. Refer to Section 3.7, “Power Supply,” for definition of VSS5 and VDD5.
2. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half

for each 8°C to 12°C in the temperature range from 50°C to 125°C.

1. Refer to Section 3.7.1, “Current Injection,” for more details
2. Parameter only applies in STOP or Pseudo STOP mode.

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 PreliminaryFreescale Semiconductor 9 Note that the JEDEC specification reserves the symbol RθJA or θJA (Theta-JA) strictly for junction-to- ambient thermal resistance on a 1s test board in natural convection environment. RθJMA or θJMA (Theta-JMA) will be used for both junction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is anticipated that the generic name, θJA, will continue to be commonly used. The average chip-junction temperature (TJ) in °C is obtained from the formula: Eqn. 1 where The total power dissipation is calculated as: Eqn. 2 where Two cases must be considered for PINT: 1. Internal voltage regulator enabled: Eqn. 3 2. Internal voltage regulator disabled (V DDR = VSSR = system ground): Eqn. 4 PIO is the sum of all output currents on input/output pins associated with VDDX: Eqn. 5 where Eqn. 6 or Eqn. 7 Table 10. Thermal Resistance 1/8 Simulation Model Packaging Parameters

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary

3.6.1 Thermal Resistance Simulation Details

Comments: 1. Junction temperature is a function of di e size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal. 3. Per JEDEC JESD51-6 with t he board (JESD51-7) horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board at the center lead. For fused lead packages, the adjacent lead is used. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperatur e difference between package top and junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. Table 11. Thermal Resistance for Case Outline 983–02, 100 Lead 14x14 mm LQFP, 0.5 mm Pitch Table 12. Thermal Resistance for Case Outline 987–01, 112 Lead 20x20 mm LQFP, 0.65 mm Pitch Table 13. Thermal Resistance for Case Outline 918–03, 144 Lead 20x20 mm LQFP, 0.5 mm Pitch Table 14. Thermal Resistance for Case Outline 1159A-01, 208 Lead 17x17 mm MAP BGA, 1.0 mm Pitch

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3.7 Power Supply

The MAC71xx Family utilizes several pins to supply power to the oscillator, PLL, digital core, I/O ports and ATD. In the context of this section, VDD5 is used for VDDA, VDDR or VDDX; VSS5 is used for VSSA, VSSR or VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX, and VDDR. VDD is used for VDD2.5, and VDDPLL, VSS is used for VSS2.5 and VSSPLL. IDD is used for the sum of the currents flowing into VDD2.5 and VDDPLL.

3.7.1 Current Injection

The power supply must maintain regulation within the VDD5 or VDD2.5 operating range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in the external power supply going out of regulation. It is important to ensure that the external VDD5 load will shunt current greater than the maximum injection current. The greatest risk will be when the MCU is consuming very little power (for example, if no system clock is present, or if the clock rate is very low).

3.7.2 Power Supply Pins

The VDDR – VSSR pair supplies the internal voltage regulator. The VDDA – VSSA pair supplies the A/D converter and the reference circuit of the internal voltage regulator. The VDDX – VSSX pair supplies the I/O pins. VDDPLL – VSSPLL pair supplies the oscillator and PLL. All VDDX pins are internally connected by metal. All VSSX pins are internally connected by metal. All VSS2.5 pins are internally connected by metal. VDDA, VDDX and VDDR as well as VSSA, VSSX and VSSR are connected by anti-parallel diodes for ESD protection.

3.7.3 Supply Current Characteristics

Table 15 and Table 16 list supply current characteristics for MAC71x1 and MAC71x6 devices at 40 MHz and 50 MHz operation, respectively. Characteristics for MAC71x2 devices are to be determined (TBD). All current measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled at the specified system frequency, using a 4 MHz oscillator in low power mode. Production testing is performed using a square wave signal at the EXTAL input. In expanded modes, the currents are highly dependent on the load and duty cycle on the address, data and control signals, thus no general numbers can be given. A good estimate is to take the single chip currents and add the currents due to the external loads.

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary Table 15. MAC71x1/6 1 Device Supply Current Characteristics – 40 MHz

1. MAC71x2 characteristics are to be determined (TBD).

Conditions shown in Table 7, with fSYS = 40 MHz.

1. 85 °C, 105°C, and 125°C refer to the "C", "V", and "M" Temperature Options, respectively.

Table 16. MAC71x1/6 1 Device Supply Current Characteristics – 50 MHz

1. MAC71x2 characteristics are to be determined (TBD).

Conditions shown in Table 7, with fSYS = 50 MHz.

1. 85 °C, 105°C, and 125°C refer to the "C", "V", and "M" Temperature Options, respectively.

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 PreliminaryFreescale Semiconductor 13

3.7.4 Voltage Regulator Characteristics

Table 17. VREG Operating Conditions

1. Current I DDPLL = 1 mA (Low Power Oscillator).
2. Current I DDPLL = 3 mA (Standard Oscillator).
3. Monitors V DDA, active only in full performance mode. This interrupt indicates that I/O and ATD performance may be

degraded due to low supply voltage.

1. Monitors V DD2.5, active only in full performance mode. Only POR is active in reduced performance mode.
2. Monitors V DD2.5, active in all modes.

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary

3.7.5 Chip Power Up and Voltage Drops

The VREG sub-modules LVI (low voltage interrupt), POR (power on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Refer to Figure 2. Figure 2. VREG Chip Power-up and Voltage Monitoring

3.7.6 Output Loads

Table 18. VREG Recommended Load Capacitances

1. Refer to Table 38 for the specific number of VDD2.5 pins on various packages. Each VDD2.5 pin should have the

Reference Manual (MAC7100RM).

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 PreliminaryFreescale Semiconductor 15

3.8 Clock and Reset Generator

This section describes the electrical characteristics for the oscillator, phase-locked loop, clock monitor and reset generator.

3.8.1 Oscillator Characteristics

The MAC7100 Family features an internal low power loop controlled Pierce oscillator and a full swing Pierce oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing Pierce oscillator/external clock depends on the level of the XCLKS signal at the rising edge of the RESET signal. Before asserting the oscillator to the internal system clock distribution subsystem, the quality of the oscillation is checked for each start from either power on, STOP or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Clock Monitor Assert Frequency fCMFA. Table 19. Oscillator Characteristics

1. If CLKSEL[PLLSEL] is clear then the system clock (fSYS) is equal to fOSC, otherwise it is equal to fVCO (table

Table 20, K3). Throughout this document, tSYS is used to specify a unit of time equal to 1 ÷ fSYS.

1. Depending on the crystal; a damping series resistor might be necessary
2. XCLKS asserted (low) during reset
3. fOSC = 4 MHz, C = 22 pF (refer to the MAC7100 Microcontroller Family Reference Manual (MAC7100RM) for circuit

board layout recommendations, including oscillator capacitor placement and values).

1. Maximum value is for extreme cases using high Q, low frequency crystals

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary

3.8.2 PLL Filter Characteristics

The oscillator provides the reference clock for the PLL as shown in Figure 3. The voltage controlled oscillator (VCO) of the PLL is also the system clock source in self clock mode. In order to operate reliably, care must be taken to select proper values for external loop filter components. Figure 3. Basic PLL Functional Diagram

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 PreliminaryFreescale Semiconductor 17 The capacitance CP should be chosen in the range of: Eqn. 14 The stabilization delays shown in Table 20 are dependant on PLL operational settings and external component selection (for example, the crystal and XFC filter).

3.8.2.1 Jitter Information

With each transition of the clock fCMP, the deviation from the reference clock fREF is measured and input voltage to the VCO is adjusted accordingly. The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure 4. It is important to note that the pre-scaler used by timers and serial modules will eliminate the effect of PLL jitter to a large extent. Figure 4. Jitter Definitions Figure 5. Maximum Bus Clock Jitter Approximation

123 N – 1 N

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary

3.8.3 PLL Characteristics

3.8.4 Crystal Monitor Time-out

The time-out Table 21 shows the delay for the crystal monitor to trigger when the clock stops, either at the high or at the low level. The corresponding clock period with an ideal 50% duty cycle is twice this time-out value.

3.8.5 Clock Quality Checker

The timing for the clock quality check is derived from the oscillator and the VCO frequency range in Table 20. These numbers define the upper time limit for the individual check windows to complete. Table 20. PLL Characteristics

1. If CLKSEL[PLLSEL] is set then the system clock (fSYS) is equal to fVCO, otherwise it is equal to fOSC (table Table 19,

J1a or J1b). Throughout this document, tSYS is used to specify a unit of time equal to 1 ÷ fSYS.

1. Percentage deviation from target frequency
2. PLL stabilization delay is highly dependent on operational requirement and external component values (for

configurations. Appropriate XFC filter values should be chosen based on operational requirement of system. Table 21. Crystal Monitor Time-Outs Table 22. CRG Maximum Clock Quality Check Timings

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 PreliminaryFreescale Semiconductor 19

3.8.6 Startup

Table 23 summarizes several startup characteristics. Refer to Section 4.3.6.10, “CRG Operating Mode Details,” in the MAC7100 Microcontroller Family Reference Manual (MAC7100RM) for details.

3.8.6.1 Power On and Low Voltage Reset (POR and LVR)

The VPORR and VPORA levels are derived from VDD2.5. The VLVRA level is derived from VDD2.5. They are also valid if the device is powered externally. After releasing a POR or LVR reset, the oscillator and clock quality checks start. After tCQOUT (Table 19, J4) if no valid oscillation is detected, the MCU will start using the internal self-generated clock. The minimum startup time is given by tuposc (Table 19, J3).

3.8.6.2 SRAM Data Retention

SRAM content integrity is guaranteed if the CRGFLG[PORF] bit is not set following a reset operation.

3.8.6.3 External Reset

When external reset is asserted for a time greater than PWRSTL, the CRG generates an internal reset and the CPU fetches the reset vector without a clock quality check, if there was stable oscillation before reset.

3.8.6.4 Stop Recovery

The MCU can return from stop to run mode in response to an external interrupt or an API. Two delays occur before the MCU resumes execution. First, the voltage regulator must exit reduced power mode and return to full performance mode (this assumes that the internal regulator is used rather than driving VDD2.5 and VDDPLL with an external regulator). Second, a clock quality check is performed in the same manner as for a power-on reset before releasing the clocks to the system.

3.8.6.5 Pseudo Stop Recovery

Recovery from pseudo stop mode is similar to stop mode in that the VREG must return to FPM, but since the oscillator is not stopped there is no delay for clock stabilization. The MCU is returned to run mode by internal or external interrupts.

3.8.6.6 Doze Recovery

Recovery from doze mode avoids both the VREG and oscillator recovery periods. The MCU is returned to run mode by internal or external interrupts. Table 23. CRG Startup Characteristics

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary

3.9 External Bus Timing

Table 24 lists processor bus input timings, which are shown in Figure 6, Figure 7 and Figure 8. NOTE All processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. The reference clock is the CLKOUT output. All other timing relationships can be derived from these values. Figure 6. General Input Timing Requirements Table 24. External Bus Input Timing Specifications 1

1. Assumes CLKOUT is configured for full drive strength (via the PIM CONFIG2_D[RDS] bit).
2. CLKOUT is equal to the system clock, fSYS. If CLKSEL[PLLSEL] is set then fSYS is equal to fVCO (table Table 20,

specify a unit of time equal to 1 ÷ CLKOUT (which is equal to tfsys).

1. The TA pin is the only control input on MAC7100 family devices.

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 PreliminaryFreescale Semiconductor 21

3.9.1 Read and Write Bus Cycles

Table 25 lists processor bus output timings. Read/write bus timings listed in Table 25 are shown in Figure 7 and Figure 8. Table 25. External Bus Output Timing Specifications 1

1. Assumes CLKOUT, CSn, BSn, OE, AS, ADDR[21:0] and DATA[15:0] are configured for full drive strength (via the PIM).
2. The CS n, BSn, OE and AS signals are synchronous to the falling edge of CLKOUT. Therefore, changes on these

signals are triggered by the falling edge of CLKOUT, even though they are specified in relation to the rising edge.

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary Figure 7. Read/Write Bus Cycles, Internal Termination

1. The TA / AS signals are multiplexed on a single pin, so only one function may be used during bus transactions.

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 PreliminaryFreescale Semiconductor 23 Figure 8. Read Bus Cycle, External Termination

1. The TA / AS signals are multiplexed on a single pin, so AS is not available when external cycle termination is used.

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary

3.10 Analog-to-Digital Converter

Table 26 and Table 27 show conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists because the sample buffer amplifier cannot drive beyond the ATD power supply levels. If the input level goes outside of this range it will effectively be clipped. Table 26. ATD Operating Characteristics in 5.0 V Range

1. Full accuracy is not guaranteed when differential voltage is less than 4.50 V
2. Minimum time assumes a sample period of 2 ATD clocks; maximum time assumes a sample period of 16 ATD clocks.

Table 27. ATD Operating Characteristics in 3.3 V Range

1. Full accuracy is not guaranteed when differential voltage is less than 3.15 V
2. Minimum time assumes a sample period of 2 ATD clocks; maximum time assumes a sample period of 16 ATD clocks.

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 PreliminaryFreescale Semiconductor 25

3.10.1 Factors Influencing Accuracy

Three factors—source resi stance, source capacitance and current injection—ha ve an influence on the accuracy of the ATD.

3.10.1.1 Source Resistance

Due to the input pin leakage current as specified in Table 8 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum specified source resistance RS, results in an error of less than 1/2 LSB (2.5 mV) at the maximum leakage current. If the device or operating conditions are less than the worst case, or leakage-induced errors are acceptable, larger values of source resistance are allowed.

3.10.1.2 Source Capacitance

When sampling, an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external capacitance and the pin capacitance. For a maximum sampling error of the input voltage ≤ 1 LSB, then the external filter capacitor must be calculated as, Cf ≥ 1024 × (CINS – CINN).

3.10.1.3 Current Injection

There are two cases to consider: 1. A current is injected into the channel being converted. The channel being stressed has conversion values of 0x3FF (0xFF in 8-bit mode) for analog inputs greater than VRH and 0x000 for values less than VRL unless the current is higher than specified as disruptive condition. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as VERR = K × RS × IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. Table 28. ATD Electrical Characteristics

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary

3.10.2 ATD Accuracy

Table 29 and Table 30 specify the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. For the following definitions, see Figure 9. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps: Eqn. 17 The Integral Non-Linearity (INL) is defined as the sum of all DNLs: Eqn. 18 Table 29. ATD Conversion Performance in 5.0 V Range

1. Assumes V REF = VRH – VRL = 5.12 V, other VREF conditions result in different LSB resolutions.
2. These values include the quantization error which is inherently ½ count for any A/D converter.

Table 30. ATD Conversion Performance in 3.3 V Range

1. Assumes V REF = VRH – VRL = 3.33 V, other VREF conditions result in different LSB resolutions.
2. These values include the quantization error which is inherently ½ count for any A/D converter.

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary

3.10.3 ATD Timing Specifications

Figure 10. ATD External Trigger Timing Diagram Table 31. ATD External Trigger Timing Specifications

1. N CONVn denotes 8- or 10-bit conversion time (refer to specifications N4, N5, P4 and P5). In order to achieve the

minimum period between conversions when using level-sensitive triggering, ETRIG must remain asserted this long.

1. Time prior to the end of a conversion that ETRIG must be negated in order to prevent the start of another conversion.

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 PreliminaryFreescale Semiconductor 29

3.11 Serial Peripheral Interface

3.11.1 Master Mode

Master mode timing values are shown in Table 32 and illustrated in Figure 11 and Figure 12.

3.11.2 Slave Mode

Slave mode timing values are shown in Table 33 and illustrated in Figure 13 and Figure 14. Table 32. SPI Master Mode Timing Characteristics

1. Refer to MAC7100 Microcontroller Family Reference Manual (MAC7100RM) Chapter 22 for all available baud rates.
2. On mask set L49P and L47W devices, U1a maximum = ¼ and U1b minimum = 4.

Table 33. SPI Slave Mode Timing Characteristics

1. On mask set L49P and L47W devices, V1a maximum = ¼ and V1b minimum = 4.

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary

3.12 FlexCAN Interface

3.13 Common Flash Module

Unless otherwise noted the abbreviation NVM (Non-V olatile Memory) is used for both program Flash and data Flash. The time base for all program and data Flash operations, fNVMOP, is derived from the IPS bus clock, fIPS, using the CFMCLKD register to control the divider ratio. Throughout this section, tIPS refers to 1 ÷ fIPS, and tNVMOP refers to 1 ÷ fNVMOP. An fNVMOP frequency range limit is imposed for performing program or erase operations. The CFM does not monitor the frequency and will not prevent program or erase operation at frequencies above or below the following limits: Eqn. 19 fNVMOP = 200 KHz gives the fastest program and erase performance. Setting CFMCLKD to a value such that fNVMOP < 150 KHz should be avoided, as this can damage the Flash memory due to overstress. Setting CFMCLKD to a value such that fNVMOP > 200 KHz can result in incomplete programming or erasure of the Flash memory array cells.

3.13.1 Mass Erase Timing

The time required to erase the entire NVM array (both program and data) is calculated using the formula: Eqn. 20 The setup time can be ignored for this operation.

3.13.2 Blank Check Timing

The time it takes to perform a blank check on the program or data Flash is dependant on the location of the first non-blank word, starting from relative address zero. One fIPS cycle is required per word to be verified, and the time required for the operation is calculated using the formula: Eqn. 21 Table 34. FlexCAN Wake-up Pulse Characteristics

150 KHz fNVMOP 200 KHz≤<

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 PreliminaryFreescale Semiconductor 33

3.13.3 Page Erase Timing

The time required to erase a 4 Kbyte program or 1 Kbyte data Flash logical page is calculated using the formulas: Eqn. 22 Eqn. 23

3.13.4 Page Erase Verify Timing

The time required to verify that a program Flash page is erased depends on the location of the first non-blank word. The time required for the operation is calculated using the formula: Eqn. 24 The time required to verify that a data Flash page is erased is calculated using the formula: Eqn. 25

3.13.5 Programming Timing

Programming time is dependant on the fIPS and fNVMOP frequencies, and is calculated for a single word using the formula: Eqn. 26 Burst programming can be utilized with the program Flash, where up to 32 words in a row can be programmed consecutively by keeping the command pipeline filled. The time to program a consecutive word is calculated using the formula: Eqn. 27 Therefore, the time to program a 32-word row is calculated using the formula: Eqn. 28 Note that burst programming is more than 2 times faster than single word programming.

3.13.6 Data Signature Timing 1

The time required to perform a data signature command is dependant on the number of words or half-words compressed during the operation, and is calculated using the formula: Eqn. 29 1. This feature is not available on mask set L49P and L47W devices. terap 4096 t NVMOP⋅ 15+ tIPS⋅= terad 1024 t NVMOP⋅ 15+ tIPS⋅= tpevp 4 1024× ⎛⎞ 15+ tIPS×= tpevd 1 1024× ⎛⎞ 15+ tIPS×= tswpgm 9t NVMOP⋅ 25 t IPS⋅+= tbwpgm 4t NVMOP⋅ 9t IPS⋅+= tbrpgm tswpgm 31 t bwpgm⋅+= tdsig Words or Half-Words 15+() tIPS⋅=

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary

3.13.7 CFM Timing Specifications

Table 35 lists the time required to execute various operations described in the Section 3.13.1 through Section 3.13.6. For operating conditions other than those assumed below, Equation 19 through Equation 29 must be used to calculate the timing for specific commands under those conditions. Table 35. CFM Timing Characteristics

1. Subject to restrictions in Table 19 and Table 20 for operating characteristics of the oscillator and PLL.
2. Minimum erase and programming times are achieved with the indicated maximum fSYS (which is fIPS × 2, and subject to the

dependent on the combination of fNVMOP and fIPS; values shown are calculated for fIPS = 2 MHz and fNVMOP = 154 KHz.

1. Minimum blank check or page erase verify time assumes the first word in the array is blank and the second is not. Maximum

blank check or page erase verify time assumes the entire block or page is blank.

1. Data signature timing is dependant on the number of words or half-words compressed for the program and data arrays,

respectively. Minimum time is for two words or half-words; maximum time is for the entire array.

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 PreliminaryFreescale Semiconductor 35

3.13.8 NVM Reliability

The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase cycling are specified at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. NOTE All values shown in Table 36 are target values and subject to characterization. For Flash cycling performance, each program operation must be preceded by an erase. Table 36. NVM Reliability Characteristics Conditions shown in Table 7 unless otherwise noted.

4 Device Pin Assignments

path. Refer to Table 2 for a comparison of the peripheral sets and package options for each device. Figure 22 show the pin assignments for various devices and packages. Table 37. Signal Pin Assignments

Table 37. Signal Pin Assignments (continued)

1. The MAC7100 family maximum peripheral configurations are listed in these columns. Some family members do not implement the full

complement of ATD, CAN, DSPI and eSCI peripherals. Refer to Table 2 on page 3 for availability of peripheral functions on various devices.

1. AS function not available on mask set L49P devices.
2. The MCKO function cannot be used on MAC7121 devices (the alternate Nexus port must be used).
3. On MAC7121 mask set L49P devices, PB11 / PCS2_B is bonded out on pin 57.
4. PD2 function not available on mask set L49P devices.
5. Optional debug status port not available on mask set L49P devices.
6. CAN C, CAN D and eSCI D not available on MAC7112, MAC7122 and MAC7142 devices.

Table 38. Power Supply, Voltage Regulator and Reference Pin Assignments

1. This pin is reserved for Freescale factory testing, and must be tied to system ground in all applications.

4.1 MAC7141 Pin Diagram

Figure 15. Pin Assignments for MAC7141 in 100-pin LQFP

100 LQFP

1. PD2 function not available on L49P mask set devices.

4.2 MAC7142 Pin Diagram

Figure 16. Pin Assignments for MAC7142 in 100-pin LQFP

4.3 MAC7121 / MAC7126 Pin Diagram

Figure 17. Pin Assignments for MAC7121 / MAC7126 in 112-pin LQFP

112 LQFP

57 PB10

85 VDDA

1. PD2 function not available on L49P mask set devices.

2 On L49P mask set devices, PB11 / PCS2_B is bonded out on pin 57.

4.4 MAC7122 Pin Diagram

Figure 18. Pin Assignments for MAC7122 in 112-pin LQFP

4.5 MAC7101 / MAC7106 Pin Diagram

Figure 19. Pin Assignments for MAC7101 / MAC7106 in 144-pin LQFP

144 LQFP

1. PD2 function not available on L49P mask set devices.

4.6 MAC7111 / MAC7116 Pin Diagram

Figure 20. Pin Assignments for MAC7111 / MAC7116 in 144-pin LQFP

1. PD2 function not available on L49P mask set devices.

4.7 MAC7112 Pin Diagram

Figure 21. Pin Assignments for MAC7112 in 144-pin LQFP

4.8 MAC7131 Pin Diagram

1. AS and PD2 functions not available on L49P mask set devices.

Figure 22. Pin Assignments for MAC7131 in 208-pin MAP BGA

4.9 MAC7136 Pin Diagram

Figure 23. Pin Assignments for MAC7136 in 208-pin MAP BGA

5 Mechanical Information

below lists available package identifiers and Freescale document numbers for reference. Table 39. Package Identifiers and Mechanical Specifications

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 PreliminaryFreescale Semiconductor 51

Revision History

Version No. Release Date Description of Changes Page Numbers v0.1 29-Oct-03 First public customer release (preliminary). v1.0 14-Sep-04 General  Converted to Freescale identity, with blue cross-reference highlights for enhanced PDF navigation, and miscellaneous updates for presentation consistency.  The order of Section 3.5 and Section 3.6 were reversed for better content flow. This has caused specification numbering to change as detailed below. Note: Content consolidation and reorganization has resulted in the following table and specification number changes (the first spec number of each table is shown): 7, 8 Section 2, “Ordering Information”  Added Table 1, mask set information  Updated Table 2 with expanded port pin counts, MAC71x2 and MAC71x6 family members  Pin assignment changes for mask set L47W devices: —I n Table 37, PB10 / PCS5_B / PCSS_B changed to pin 57, footnote for L49P Table Title Rev. 1.0 Rev. 0.1

5.0 V I/O Characteristics Table 8 D1a Table 15 F1

3.3 V I/O Characteristics Table 9 E1a Table 16 G1

Section 3.6, “Power Dissipation and Thermal Characteristics” Table 10 to Table 14 Table 7 to Table 11 MAC71x1/6 Device Supply Current Characteristics – 40 MHz Table 15 F1 Table 12 D1a MAC71x1/6 Device Supply Current Characteristics – 50 MHz Table 16 G1 N/A VREG Operating Conditions Table 17 H1 Table 13 E1 VREG Recommended Load Capacitances Table 18 Table 14 Oscillator Characteristics Table 19 J1a Table 17 H1a PLL Characteristics Table 20 K1 Table 18 J1 Crystal Monitor Time-Outs Table 21 Table 19 CRG Maximum Clock Quality Check Timings Table 22 Table 20 CRG Startup Characteristics Table 23 L1 Table 21 K1 External Bus Input Timing Specifications Table 24 M1 Table 22 L1 External Bus Output Timing Specifications Table 25 M6a Table 23 L6a ATD Operating Characteristics in 5.0 V Range Table 26 N1 Table 24 M1 ATD Operating Characteristics in 3.3 V Range Table 27 P1 Table 25 N1 ATD Conversion Performance in 5.0 V Range Table 29 R1 Table 27 Q1 ATD Conversion Performance in 3.3 V Range Table 30 S1 Table 28 R1 ATD Performance Specifications N/A Table 30 T1 ATD Timing Specifications N/A Table 31 U1 ATD External Trigger Timing Specifications Table 31 T1 Table 32 V1 SPI Master Mode Timing Characteristics Table 32 U1a Table 33 W1a SPI Slave Mode Timing Characteristics Table 33 V1a Table 34 X1a FlexCAN Wake-up Pulse Characteristics Table 34 W1 Table 35 Y1 CFM Timing Characteristics Table 35 X1 Table 36 Z1 NVM Reliability Characteristics Table 36 X9b Table 37 Z10

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary Mechanical Information Freescale Semiconductor52 v1.0 14-Sep-04 (continued) Section 3, “Electrical Characteristics”  Section 3.2, “Absolute Maximum Ratings” — A1a renamed to VDDX — A4 “rating” changed to Analog (from ATD) — A9 minimum changed to –0.3 — A12 maximum value removed, footnote reference added — Table 8, Table 9 footnotes added regarding VDD5/VSS5  Section 3.4, “Operating Conditions” — C1 renamed to VDDX — C4 added (C5 to C11b renumbered) — C8 maximum changed from 40 MHz to 50 MHz  Section 3.5, “Input/Output Characteristics” — Table 8 spec D4 updated (from TBD) — Table 9 spec E4 changed to 1 μA to match D4  Section 3.6, “Power Dissipation and Thermal Characteristics” — Reworked Equation 1 through Equation 4 and supporting text  Section 3.7, “Power Supply” — Added MAC71 x1 designation and footnotes to Table 15 / Table 16 — Table 15 designated for 40 MHz, and – Numerous TBD entries replaced with values – Run Supply Current collapsed from fifteen spec items to one – Removed separate Core/Regulator/Pins specs for Run/Pseudo Stop/Stop modes – F1 and F3 descriptions changed – F1, F2, F3 and F4 values updated — Table 16 added for 50 MHz specifications — Table 17, deleted I REG spec (Regulator Current in Reduced Power, Shutdown Modes) — Table 18, VDD2.5 load capacitance typical changed, with clarification footnote  Section 3.8, “Clock and Reset Generator” — Table 19 updates – Changed specs J1b and J6 maximum from 40 MHz to 50 MHz – Reversed polarity of XCLKS reference in footnote (3) – J1b maximum changed to 40 MHz –V DCBIAS removed – Added footnote to define t fsys as 1 ÷ fSYS for use elsewhere in the document — Updated Section 3.8.2, “PLL Filter Characteristics” — Table 20 updates – Changed spec K3 maximum from 40 MHz to 50 MHz – Added footnote to define t fsys as 1 ÷ fSYS for use elsewhere in the document — Table 23 updates –R e m o v e d VPORR and VPORA, as they duplicated H6 –R e m o v e d tWRS  Section 3.9, “External Bus Timing” — Table 24 updates – M1 minimum changed from 25 ns to 20 ns (Figure 6 also updated) – Reworded footnote ( 1) – Added footnote ( 2) to define tCYC as 1 ÷ CLKOUT — Table 25 updates – Added footnote ( 1) – Consolidated previous NOTES into footnote ( 2), (Figure 7, Figure 8 also updated) 7, 8 Revision History (continued) Version No. Release Date Description of Changes Page Numbers

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 PreliminaryFreescale Semiconductor 53 v1.0 14-Sep-04 (continued) Section 3, “Electrical Characteristics” (continued)  Section 3.10, “Analog-to-Digital Converter” — Rev. 0.1 redundant and su perfluous content deleted – Section 3.10.3, “ATD Electrical Specifications,” (included Table 29 and Table 30) – Table 31, “ATD Performance Specifications” (redundant with v0.1 Table 27 and Table 28, now Table 29 and Table 30) — Table 26 updates – Deleted previous spec M6 – Changed spec N7 and N8 values — Table 27 updates – Deleted previous spec N6 – Changed spec P7 and P8 values – Changed spec P2 and footnote (1) to specify 3.15 V — Table 28 updates – Changed spec Q2 parameter classification from T to C and 10 pF and 22 pF values moved from maximum to typical — Table 29 updates – Operating conditions V DDA minimum changed to 4.5 V –V REF description moved from “conditions” header to new footnote (1) — Table 30 updates – Operating conditions V DDA minimum changed to 3.15 V –V REF description moved from “conditions” header to new footnote (1) — Table 31 updates – Spec T1 description clarified, max removed, min added with footnote – Spec T2 modified to show both edge- and level-sensitive modes — Figure 10 modified to remove “Max Frequency” label and clearly separate edge- and level-sensitive mode timing examples  Section 3.11, “Serial Peripheral Interface” — Table 32 updates – Changed specs U1a, U1b and U4 to use fIPS and tIPS for clarity and consistency with MAC7100RM – Changed U1a max to ½ and U1b min to 2 to account for the DBR bit — Table 33 updates – Changed specs V1a, V1b, V2, V3, V4, V7, V8 to use fIPS and tIPS for clarity and consistency with MAC7100RM – Changed V1a max to ½ and V1b min to 2 to account for the DBR bit  Section 3.13, “Common Flash Module” — Significant rework to match MAC7100RM clock naming, references and timing calculations for clarity and consistency — Changed X1 maximum from 40 MHz to 50 MHz (Table 35) 32 to 35 Revision History (continued) Version No. Release Date Description of Changes Page Numbers

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2 Preliminary Mechanical Information Freescale Semiconductor54 v1.0 14-Sep-04 (continued) Section 4, “Device Pin Assignments”  Table 37 and Table 38 added  Added PD2 label / footnote to Figure 15, Figure 17, Figure 19, Figure 20 and Figure 22  Section 4.2, “MAC7142 Pin Diagram” / Figure 16 added  Section 4.3, “MAC7121 / MAC7126 Pin Diagram” / Figure 17 updated — PB10 / PCS5_B / PCSS_B bonded out on pin 57, footnote for L49P — Added MAC71 x6 device information  Section 4.4, “MAC7122 Pin Diagram” / Figure 18 added  Section 4.5, “MAC7101 / MAC7106 Pin Diagram” / Figure 19 updated — Added MAC71 x6 device information  Section 4.6, “MAC7111 / MAC7116 Pin Diagram” / Figure 20 updated — Added AS to TA pin — Added MAC71 x6 device information  Section 4.7, “MAC7112 Pin Diagram” / Figure 21 added  Section 4.8, “MAC7131 Pin Diagram” / Figure 22 corrected, updated — Changed pins C8 & P8 from V SS2.5 to VDD2.5 — Changed pin T8 from V SSPLL to VDDPLL — Added AS to TA pin  Section 4.9, “MAC7136 Pin Diagram” / Figure 23 added 36, 40 41, 43, 45, 46, 48 v1.1 1-Dec-04 Section 3, “Electrical Characteristics”  Section 3.7, “Power Supply” — Table 15 spec F4 –40° C and 25° C max value changed — Table 16 spec G4 –40° C and 25° C max value changed  Section 3.8, “Clock and Reset Generator” — Table 19 spec J3 typical TBD entry replaced with value — Table 20 specs K15 and K16 maximum TBD entries replaced with values v1.1.1 3-Dec-04 Section 3, “Electrical Characteristics”  Section 3.7, “Power Supply” — Table 15 spec F3 –40° C, 25° C and 125° C typ and max values and unit changed — Table 16 spec G3 –40° C, 25° C and 125° C typ and max value and unit changed v1.2 10-Feb--06 Section 1, “Overview”  Moved 71x6 device numbers from footnote to “covered” list Section 2, “Ordering Information”  Added AF , AG and VM package identifiers to Figure 1  Added 1L38Y to Table 1 Section 3, “Electrical Characteristics”  Replaced TBD values in Table 15 and Table 16 with final qualification data, changed table titles and footnotes to reflect 71x6 inclusion. Section 5, “Mechanical Information”  Removed obsolete package diagrams, replaced with document IDs available on web site. Revision History (continued) Version No. Release Date Description of Changes Page Numbers

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