MAC7100 MOTOROLA | Alldatasheet
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE This document provides electrical specifications, pin assignments, and package diagrams for MAC7100 family of microcontro ller devices. For functional ch aracteristics of the family, refer to the MAC7100 Microcontroller Family Reference Manual (MAC7100RM/D). This document contains the following topics: Topic Page Section 1, “Overview” 1 Section 2, “Ordering Information” 2 Section 3, “Electrical Characteristics” 3 Section 4, “Device Pin Assignments” 36 Section 5, “Mechanical Information” 41 1O v e r v i e w The MAC7100 Family of microcontrollers (MCUs) are members of a pin-compatible family of 32-bit Flash-memory-based devices develo ped specifically for embedded automotive applications. The pin-compatible family concept enables users to select between different memory and peripheral options for scalable designs. All MAC7100 Family members are composed of a 32-bit central processing unit (ARM7TDMI-S), up to 512Kbytes of embedded Flash EEPROM for program storage, up to 32 Kbytes of embedded Flash for data and/or program storage, and up to 32Kbytes of RAM. The family is implemented with an enhanced DMA (eDMA) controller to improve performance for transfers between memory and many of the on-chip peripherals. The peripheral set includes asynchronous serial communications interfaces (eSCI), serial peripheral interfa ces (DSPI), inter-integrated circuit (I 2C) bus controllers, FlexCAN interfaces, an enhan ced modular I/O subsystem (eMIOS), 10-bit analog-to-digital converter (ATD) channe ls, general-purpose timers (PIT) and two special-purpose timers (RTI and SWT). The pe ripherals share a large number of general purpose input-output (GPIO) pins, all of whic h are bidirectional and available with interrupt capability to trigger wake-up from low-power chip modes. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirem ents. The operating frequency of de vices in the family is up to a maximum of 50 MHz. The internal data pa ths between the CPU core, eDMA, memory and peripherals are all 32 bits wide, further impr oving performance for 32 -bit applications. The Advance Information MAC7100EC/D Rev. 0.1, 10/2003 MAC7100 Microcontroller Family Hardware Specifications 32-bit Embedded Controller Division Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
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Ordering Information
MAC7111 and MAC7131 also offer a 16-bit wide exte rnal data bus with 22 address lines. The family of devices is capable of operating over a junction temperature range of -40° C to 150° C. Table 1 provides a comparison of members of the MA C7100 Family and the availability of peripheral modules on the various devices.
2 Ordering Information
Figure 1. Order Part Number Example Table 1. MAC7100 Family Device Derivatives Freescale Semiconductor, Inc.
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Electrical Characteristics
3 Electrical Characteristics
This section contains electrical information for MAC7100 Family microcontrollers. The information is preliminary and subject to change without notice. MAC7100 Family devices are specified and tested over the 5 V and 3.3 V ranges. For operation at any voltage within that range, the 3.3 V specifications generally apply. However, no production testing is done to verify operation at intermediate supply voltage levels.
3.1 Parameter Classification
The electrical parameters shown in this appendix are derived by various methods. To provide a better understanding to the designer, the following classification is used. Parameters are tagged accordingly in in the column labeled “C” of the parametric tables, as appropriate.
3.2 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. Fu nctional operation outside these maximums is not guaranteed. Stress beyond these limits may affect reliability or cause permanent damage to the device. MAC7100 Family devices contain circuitry protectin g against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either VSS5 or VDD5). Table 2. Parametric Value Classification P Parameters guaranteed during production testing on each individual device. sample size across process variations. are within this classification, even if not so tagged. D Parameters derived mainly from simulations. Table 3. Absolute Maximum Ratings Freescale Semiconductor, Inc.
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3.3 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. Duri ng the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parame tric and functional testing is pe rformed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise. A11 XFC, EXTAL, XTAL inputs V ILV –0.3 +3.0 V A12 TEST input V TEST –0.3 +10.0 V Instantaneous Maximum Current 2 A13 Single pin limit for XFC, EXTAL, XTAL 3 IDL –25 +25 mA A14 Single pin limit for all digital I/O pins 4 ID –25 +25 mA A15 Single pin limit for all analog input pins 4 IDA –25 +25 mA A16 Single pin limit for TEST 5 IDT –0.25 0 mA A17 Storage Temperature Range T stg –65 +155 °C 1 The device contains an internal voltage regulator to generate the logic and PLL supply from the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 2 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.3 V and VNEGCLAMP = –0.3 V, then use the larger of the calculated values. 3 These pins are internally clamped to VSSPLL and VDDPLL. 4 All I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA. 5 This pin is clamped low to VSSX, but not clamped high, and must be tied low in applications. Table 4. ESD and Latch-up Test Conditions Table 3. Absolute Maximum Ratings (continued) Freescale Semiconductor, Inc.
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3.4 Operating Conditions
Unless otherwise noted, the following conditions apply to all parametric data. Refer to the temperature rating of the device (C, V , M) with respect to ambient temperature (TA) and junction temperature (TJ). For power dissipation calculations refer to Section 3.5, “Power Dissipation and Thermal Characteristics.” Table 5. ESD and Latch-Up Protection Characteristics Table 6. MAC7100 Family Device Operating Conditions absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source. between ambient temperature TA and device junction temperature TJ. Freescale Semiconductor, Inc.
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 3.4.1 5 V I/O Pins The I/O pins operate at a nominal level of 5 V . This class of pins is comprised of the clocks, control and general purpose/peripheral pins. The internal structure of these pins is identical; however, some functionality may be disabled (for example, for analog inputs the output drivers, pull-up/down resistors are permanently disabled).
3.4.2 Oscillator Pins
The pins XFC, EXTAL, XTAL are dedicated to the oscillator and operate at a nominal level of 2.5 V .
3.5 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closel y related. The user must assure that the maximum operating junction temperature is not exceeded. Note that the JEDEC specifi cation reserves the symbol R θJA or θJA (Theta-JA) strictly for junction-to- ambient thermal resistance on a 1s test bo ard in natural convection environment. R θJMA or θJMA (Theta-JMA) will be used for both ju nction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is anticipated that the generic name, θJA, will continue to be commonly used. The average chip-junction temperature (TJ) in °C is obtained from: The total power dissipation is calculated from: Two cases for PIO, with the internal voltage regulator enabled and disabled, must be considered: 1. Internal V oltage Regulator disabled: PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. or 2. Internal voltage regulator enabled: IDDR is the current shown in Table 12 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high. TJ TA ΘJA()+= TJ Junction Temperature (°C)= TA Ambient Temperature (°C)= PD Total Chip Power Dissipation (W)= ΘJA Package Thermal Resistance (°C/W)= PD PINT PIO+= PINT Chip Internal Power Dissipation (W)= PINT IDD VDD×() IDDPLL V DDPLL×() IDDAV DDA×()++= PIO RDSON i ∑ IIOi () 2⋅= RDSON VOL IOL RDSON VDD5V OH– IOL PINT IDDRV DDR×() IDDAV DDA×()+= Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
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3.5.1 Power Dissipation Simulation Details
Comments: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal. 3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board at the center lead. For fused lead packages, the adjacent lead is used. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. Table 7. Thermal Resistance for 100 lead 14x14 mm LQFP, 0.5 mm Pitch 1 Table 8. Thermal Resistance for 112 lead 20x20 mm LQFP, 0.65 mm Pitch 1 Table 9. Thermal Resistance for 144 lead 20x20 mm LQFP, 0.5 mm Pitch 1 Table 10. Thermal Resistance for 208 lead 17x17 mm MAP, 1.0 mm Pitch 1 Freescale Semiconductor, Inc.
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3.6 Power Supply
The MAC7100 Family utilizes several pi ns to supply power to the oscilla tor, PLL, digital core, I/O ports and ATD. In the context of this section, VDD5 is used for VDDA, VDDR or VDDX; VSS5 is used for VSSA, VSSR or VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX, and VDDR. VDD is used for VDD2.5, and VDDPLL, VSS is used for VSS2.5 and VSSPLL. IDD is used for the sum of the currents flowing into VDD2.5 and VDDPLL.
3.6.1 Current Injection
The power supply must mainta in regulation within the V DD5 or V DD2.5 operating range during instantaneous and operating maximum current conditions. If positive injection current (V in > V DD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in the external power supply going out of regulation. It is important to ensure that the external VDD5 load will shunt current greater than the maximum injection current. The greatest risk will be when the MCU is consuming very little power (for example, if no system clock is present, or if the clock rate is very low).
3.6.2 Power Supply Pins
The VDDR – VSSR pair supplies the internal voltage regulator. The V DDA – VSSA pair supplies the A/D converter and the reference circuit of the internal voltage regulator. The VDDX – VSSX pair supplies the I/O pins. VDDPLL – VSSPLL pair supplies the oscillator and PLL. All VDDX pins are internally connected by metal. All V SSX pins are internally co nnected by metal. All VSS2.5 pins are internally connected by metal. VDDA, VDDX and VDDR as well as VSSA, VSSX and VSSR are connected by anti-parallel diodes for ESD protection.
3.6.3 Supply Currents
All current measurements are withou t output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 40MHz bus frequency using a 4MHz oscillator in low power mode. Production testing is performed using a square wave signal at the EXTAL input. In expanded modes, the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of th ose signals. No generally applicable numbers can be given. A good estimate is to take the single chip currents and add the currents due to the external loads. Table 11. Power Dissipation 1/8 Simulation Model Packaging Parameters Freescale Semiconductor, Inc.
MOTOROLA MAC7100 Microcontroller Family Hardware Specifications 9 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Table 12. Supply Current Characteristics 1 At the time of publication, this value is yet to be determined, and will be supplied when device characterization is complete. 2 85°C, 105°C, and 125°C refer to the "C", "V", and "M" Temperature Options, respectively. Freescale Semiconductor, Inc.
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3.6.4 Voltage Regulator Characteristics
Table 13. VREG Operating Conditions 2 Current IDDPLL = 1mA (Low Power Oscillator). 3 Current IDDPLL = 3mA (Standard Oscillator). 5 Monitors VDD2.5, active only in full performance mode. Only POR is active in reduced performance mode. 6 Monitors VDD2.5, active in all modes. Freescale Semiconductor, Inc.
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3.6.5 Chip Power Up and Voltage Drops
The VREG sub-modules LVI (low vol tage interrupt), POR (power on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Refer to Figure 2. Figure 2. VREG Chip Power-up and Voltage Drops
3.6.6 Output Loads
load is allowed. Capacitive loads are specified in Table 14. Capacitors with X7R dielectricum are required. Table 14. VREG Recommended Load Capacitances Freescale Semiconductor, Inc.
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3.7 I/O Characteristics
This section describes the characteristics of all I/O pins in both 3.3 V and 5 V operating conditions. All parameters are not always applicable; for example, not all pins feature pull up/down resistances. Table 15. 5 V I/O Characteristics for each 8°C to 12°C in the temperature range from 50°C to 125°C. 3 Parameter only applies in STOP or Pseudo STOP mode. Freescale Semiconductor, Inc.
Table 16. 3.3 V I/O Characteristics Conditions shown in Table 6, with VDDX = 3.3 V ±10% and a temperature maximum of +140°C unless otherwise noted. for each 8°C to 12°C in the temperature range from 50°C to 125°C. 3 Parameter only applies in STOP or Pseudo STOP mode. Freescale Semiconductor, Inc.
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3.8 Clock and Reset Generator Electrical
This section describes the electrical characteristics for the oscillator, phase-locked loop, clock monitor and reset generator.
3.8.1 Oscillator Characteristics
The MAC7100 Family features an internal low power loop controlled Pierce oscillator and a full swing Pierce oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing Pierce oscillator/external clock depends on the level of the XCLKS signal at the rising edge of the RESET signal. Before asserting the oscillator to the internal syst em clock distribution subsystem, the quality of the oscillation is checked for each start from ei ther power on, STOP or oscillator fail. t CQOUT specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Clock Monitor Assert Frequency fCMFA. Table 17. Oscillator Characteristics
1 Depending on the crystal; a damping series resistor might be necessary
2 XCLKS negated during reset
4 Maximum value is for extreme cases using high Q, low frequency crystals
Freescale Semiconductor, Inc.
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3.8.2 PLL Filter Characteristics
The oscillator provides the reference clock for the PLL. The voltage controlled oscillator (VCO) of the PLL is also the system clock source in self clock mode. In order to operate reliably, care must be taken to select proper values for external loop filter components. Figure 3. Basic PLL Functional Diagram criteria by at least a factor of 10, typical values are 50. ζ = 0.9 ensures a good transient response. component selection (for example, crystal, XFC filter). Freescale Semiconductor, Inc.
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3.8.2.1 Jitter Information
The basic functionality of the PLL is shown in Figure 3. With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly. The adjustment is done continuously with no abrupt changes in the cl ock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control lo op resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure 4. It is important to note that the pre-scaler used by timers and serial modules will eliminate the effect of PLL jitter to a large extent. Figure 4. Jitter Definitions Figure 5. Maximum Bus Clock Jitter Approximation
123 N – 1 N
Freescale Semiconductor, Inc.
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3.8.3 PLL Characteristics
3.8.4 Crystal Monitor Time-out
The time-out Table 19 shows the delay for the crystal monitor to trigger when the clock stops, either at the high or at the low level. The corresponding clock period with an ideal 50% duty cycle is twice this time-out value.
3.8.5 Clock Quality Checker
The timing for the clock quality check is derive d from the oscillator and the VCO frequency range in Table 18. These numbers define the upper time limit for the individual check windows to complete. Table 18. PLL Characteristics
2 Percentage deviation from target frequency
configurations. Appropriate XFC filter values should be chosen based on operational requirement of system. Table 19. Crystal Monitor Time-Outs Table 20. CRG Maximum Clock Quality Check Timings Freescale Semiconductor, Inc.
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3.8.6 Startup
Table 21 summarizes several startup characteristic s explained in this section. Refer to the MAC7100 Microcontroller Family Reference Manual (MAC7100RM/D) for a detailed description of the startup behavior.
3.8.6.1 Power On and Low Vo ltage Reset (POR and LVR)
The release level VPORR and the assert level VPORA are derived from the VDD2.5 supply. The assert level VLVRA is derived from the V DD2.5 supply. They are also valid if th e device is powered externally. After releasing the POR or LVR reset, the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self-generated clock. The fastest startup time possible is given by tuposc (refer to Table 17).
3.8.6.2 SRAM Data Retention
The SRAM contents integrity is guaranteed if the PORF bit in the CRGFLG register is not set following a reset operation.
3.8.6.3 External Reset
When external reset is asserted for a time greater than PWRSTL, the CRG module generates an internal reset and the CPU starts fetching the reset vector with out doing a clock quality check, if there was stable oscillation before reset.
3.8.6.4 Stop Recovery
The MCU can be returned to run mode from the stop mode by an external interrupt. A clock quality check is performed in the same manner as for POR before releasing the clocks to the system.
3.8.6.5 Pseudo Stop and Doze Recovery
Recovery from pseudo stop and doze modes are essentially the same, since the oscillator is not stopped in either mode. The controller is returned to run mode by internal or external interrupts or other wakeup events in the system. After t wrs, the CPU fetches an interrupt vector if the wakeup event was an interrupt, or continues to execute code if the wakeup event was not an interrupt. Table 21. CRG Startup Characteristics Freescale Semiconductor, Inc.
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3.9 External Bus Timing Specifications
Table 22 lists processor bus input timings, which are shown in Figure 6, Figure 7 and Figure 8. NOTE All processor bus timings are synchronou s; that is, input setup/hold and output delay with respect to the risi ng edge of a reference clock. The reference clock is the CLKOUT output. All other timing relationships can be derived from these values. Figure 6. General Input Timing Requirements Table 22. External Bus Input Timing Specifications 1 Timing specifications have been indicated taking into account the full drive strength for the pads. 2 TA pins are being referred to as control inputs. Freescale Semiconductor, Inc.
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3.9.1 Read and Write Bus Cycles
Table 23 lists processor bus output timings. Read/write bus timings listed in Table 23 are shown in Figure 7 and Figure 8. Table 23. External Bus Output Timing Specifications 1 CSn transitions after the falling edge of CLKOUT. 2 BSn transitions after the falling edge of CLKOUT. 3 OE transitions after the falling edge of CLKOUT. Freescale Semiconductor, Inc.
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Figure 7. Read/Write (Internally Terminated) Bus Timing Freescale Semiconductor, Inc.
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Figure 8. Read Bus Cycle Terminated by TA Freescale Semiconductor, Inc.
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3.10 Analog-to-Digital Converter Characteristics
Table 24 and Table 25 show conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists because the sample buffer amplifier cannot drive beyond the ATD power supply levels. If the input level goes outside of this range it will effectively be clipped.
3.10.1 Factors Influencing Accuracy
Three factors — source resistance, source capacitance and current injection — have an influence on the accuracy of the ATD. Table 24. ATD Operating Characteristics in 5 V Range 2 Minimum time assumes final sample period of 2 ATD clocks; maximum time assumes final sample period of 16 ATD clocks. Table 25. ATD Operating Characteristics in 3.3 V Range Conditions shown in Table 6, with VDDX = 3.3 V ±10% and a temperature maximum of +140°C unless otherwise noted. 2 Minimum time assumes final sample period of 2 ATD clocks; maximum time assumes final sample period of 16 ATD clocks. Freescale Semiconductor, Inc.
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3.10.1.1 Source Resistance
Due to the input pin leakage current as specified in Table 15 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum specified source resistance RS, results in an error of less than 1/2 LSB (2.5 mV) at the maximum leakage current. If the device or operating conditions are less than the worst case, or leakage-induc ed errors are acceptable, larger values of source resistance are allowed.
3.10.1.2 Source Capacitance
When sampling, an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external capacitance and the pin capacitance. For a maximum sampling error of the input voltage ≤ 1 LSB, then the external filter capacitor must be calculated as, Cf ≥ 1024 × (CINS – CINN).
3.10.1.3 Current Injection
There are two cases to consider: 1. A current is injected into the channel being converted. The channel being stressed has conversion values of 0x3FF (0xFF in 8-bit mode) for analog inputs greater than VRH and 0x000 for values less than VRL unless the current is higher than specified as disruptive condition. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as VERR =K × RS × IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. Table 26. ATD Electrical Characteristics Freescale Semiconductor, Inc.
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3.10.2 ATD Accuracy
Table 27 and Table 28 specify the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. For the following definitions see also Figure 8. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps. The Integral Non-Linearity (INL) is defined as the sum of all DNLs: Table 27. ATD Conversion Performance in 5 V Range Conditions shown in Table 6 unless otherwise noted. 1 These values include the quantization error which is inherently 1/2 count for any A/D converter. Table 28. ATD Conversion Performance in 3.3 V Range Conditions shown in Table 6 unless otherwise noted. 1 These values include the quantization error which is inherently 1/2 count for any A/D converter. Freescale Semiconductor, Inc.
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Figure 9. ATD Accuracy Definitions Figure 8 shows only definitions, for specification values refer to Table 27. Freescale Semiconductor, Inc.
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3.10.3 ATD Electrical Specifications
Table 29 lists the DC electrical characteristics for the ATD module. Table 27 lists the analog-to-digital conversion performance specifications. Table 29. ATD Electrical Characteristics (Operating) 1 noted. Refer to Table 6 for additional operating conditions. the power supply levels. If the input level goes outside of this range, it will effectively be clipped. 3 Full accuracy is not guaranteed when the differential reference voltage is less than 4.5 V. 4 85°C, 105°C, and 125°C refer to the "C", "V", and "M" Temperature Options, respectively. 5 The input injection current is specified to 1 count of error. Freescale Semiconductor, Inc.
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3.10.4 ATD Timing Specifications
6 Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 to 12 °C, in the ambient temperature range of 50 to 125 °C. 7 Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater than VRH and 0x000 for values less than VRL. This assumes that VDDA ≥ AVRH and VRL ≥ VSSA due to the presence of the sample amplifier. Other channels are not affected by non-disruptive conditions. 8 Coupling Ratio, K, is defined as the ratio of the output current, IOUT, measured on the pin under test to the injection current, IINJ, when both adjacent pins are overstressed with the specified injection current. K = IOUT ÷ IINJ. The input voltage error on the channel under test is calculated as Verr = IINJ x K x RS. 9 Total injection current is determined by the number of channels injecting (for example, 15), external injection voltage (VINJ –V POSCLAMP, or VINJ – VNEGCLAMP), and the external source impedance, Rs, wherein all input channels have the same values. To determine the error voltage on the converted channel, only the two adjacent channels are expected to contribute to the error voltage: Verrj = (VINJ – VCLAMP) × K × 2. 10 For a maximum sampling error of the input voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 × CSAMP. The value of CSAMP in the new design may be reduced, or increased slightly. Table 30. ATD Performance Specifications 1 1 All voltages referred to VSSA, VDDA = 5.0 V±10%, ATD clock = 2.1 Mhz., –40 to 125 °C. 3 These values include quantization error which is inherently 1/2 count for any A/D converter. of source resistance is allowable. Table 31. ATD Timing Specifications Table 32. ATD External Trigger Timing Specifications
1 ATD clock
Freescale Semiconductor, Inc.
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Figure 10. ATD External Trigger Timing Diagram Freescale Semiconductor, Inc.
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3.11 Serial Peripheral Interface Electrical
3.11.1 Master Mode
Figure 11 and Figure 12 illustrate master mode timing. Timing values are shown in Table 33.
3.11.2 Slave Mode
Figure 13 and Figure 14 illustrate the slave mode timing. Timing values are shown in Table 34. Table 33. SPI Master Mode Timing Characteristics 1 between the Master and the Slave timing shown in Table 34. Table 34. SPI Slave Mode Timing Characteristics Freescale Semiconductor, Inc.
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Figure 11. SPI Master Timing (CPHA = 0) Figure 12. SPI Master Timing (CPHA =1) Freescale Semiconductor, Inc.
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Figure 13. SPI Slave Timing (CPHA = 0) Figure 14. SPI Slave Timing (CPHA =1) Freescale Semiconductor, Inc.
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3.12 FlexCAN Electrical Specifications
3.13 Program Flash and Data Flash Timing
Unless otherwise noted the abbreviation NVM (Non-V olatile Memory) is used for both program Flash and data Flash.
3.13.1 NVM timing
The time base for all NVM program or erase operations is derived from the system clock divided by two (Fsys/2). A minimum system frequency f NVMfsys is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured. The Flash and Data Flash program and erase operatio ns are timed using a clock derived from the system frequency using the CFMCLKD register. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in Table 36 are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2 MHz.
3.13.1.1 Single Word Programming
The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula.
3.13.1.2 Burst Programming
This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst programming by keeping the comman d pipeline filled. The time to pr ogram a consecutive word can be calculated as: The time to program a whole row is: Burst programming is more than 2 times faster than single word programming. Table 35. FlexCAN Wake-up Pulse Characteristics Freescale Semiconductor, Inc.
34 MAC7100 Microcontroller Family Hardware Specifications MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
3.13.1.3 Sector Erase
Erasing a 4k byte Flash sector takes: The setup time can be ignored for this operation.
3.13.1.4 Mass Erase
Erasing a NVM block takes: The setup time can be ignored for this operation.
3.13.1.5 Blank Check
The time it takes to perform a blank check on the Flash or Data Flash is depend ant on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command. Table 36. NVM Timing Characteristics 1
1 Conditions are shown in Table 6 unless otherwise noted
3 Minimum programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fbus. 5 Minimum erase times are achieved under maximum NVM operating frequency fNVMOP.
6 Minimum time, if first word in the array is not blank
7 Maximum time to complete check on an erased block
Freescale Semiconductor, Inc.
35 MAC7100 Microcontroller Family Hardware Specifications MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
3.13.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen earl y life failures. The failure rates fo r data retention and program/erase cycling are specified at the oper ating conditions noted. The progra m/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. NOTE All values shown in Table 37 are target values and subject to characterization. For Flash cycling performance, each Program operation must be preceded by an erase. Table 37. NVM Reliability Characteristics Conditions shown in Table 6 unless otherwise noted. Freescale Semiconductor, Inc.
36 MAC7100 Microcontroller Family Hardware Specifications MOTOROLA
4 Device Pin Assignments
path. Refer to Table 1 for a comparison of the peripheral sets and package options for each device. and Figure 19 show the pin assignments for the various packages.
4.1 MAC7141PV Pin Assignments
Figure 15. Pin Assignments for MAC7141 in 100-pin LQFP
100 LQFP
Freescale Semiconductor, Inc.
37 MAC7100 Microcontroller Family Hardware Specifications MOTOROLA
4.2 MAC7121PV Pin Assignments
Figure 16. Pin Assignments for MAC7121 in 112-pin LQFP
112 LQFP
57 PB11
85 VDDA
Freescale Semiconductor, Inc.
38 MAC7100 Microcontroller Family Hardware Specifications MOTOROLA
4.3 MAC7101PV Pin Assignments
Figure 17. Pin Assignments for MAC7101 in 144-pin LQFP
144 LQFP
Freescale Semiconductor, Inc.
39 MAC7100 Microcontroller Family Hardware Specifications MOTOROLA
4.4 MAC7111PV Pin Assignments
Figure 18. Pin Assignments for MAC7111 in 144-pin LQFP
109 PE9
Freescale Semiconductor, Inc.
40 MAC7100 Microcontroller Family Hardware Specifications MOTOROLA
4.5 MAC7131VF Pin Assignments
Figure 19. Pin Assignments for MAC7131 in 208-pin MAP BGA Freescale Semiconductor, Inc.
41 MAC7100 Microcontroller Family Hardware Specifications MOTOROLA
5 Mechanical Information
Figure 20. 100-Pin LQFP Mechanical Dimensions (Case No. 983)
- DIMENSIONING AND TOLERANCING PER
- CONTROLLING DIMENSION: MILLIMETER.
- DATUM PLANE -H- IS LOCATED AT BOTTOM OF
BODY AT THE BOTTOM OF THE PARTING LINE.
- DATUMS -A-, -B- AND -D- TO BE
DETERMINED AT DATUM PLANE -H-.
- DIMENSIONS S AND V TO BE DETERMINED
- DIMENSIONS A AND B DO NOT INCLUDE
AND ARE DETERMINED AT DATUM PLANE -H-.
- DIMENSION D DOES NOT INCLUDE DAMBAR
0.05 A-B
Freescale Semiconductor, Inc.
42 MAC7100 Microcontroller Family Hardware Specifications MOTOROLA
Figure 21. 112-Pin LQFP Mechanical Dimensions (Case No. 987)
20.000 BSC
- DIMENSIONING AND TOLERANCING PER
- DIMENSIONS IN MILLIMETERS.
- DATUMS L, M AND N TO BE DETERMINED AT
- DIMENSIONS S AND V TO BE DETERMINED
- DIMENSIONS A AND B DO NOT INCLUDE
A AND B INCLUDE MOLD MISMATCH.
- DIMENSION D DOES NOT INCLUDE
Freescale Semiconductor, Inc.
43 MAC7100 Microcontroller Family Hardware Specifications MOTOROLA
Figure 22. 144-Pin LQFP Mechanical Dimensions (Case No. 918)
144 PL °
20.00 BSC
- DIMENSIONS AND TOLERANCING PER ASME
- DIMENSIONS IN MILLIMETERS.
- DATUMS L, M, N TO BE DETERMINED AT THE
- DIMENSIONS S AND V TO BE DETERMINED AT
- DIMENSIONS A AND B DO NOT INCLUDE MOLD
DETERMINED AT DATUM PLANE H.
- DIMENSION D DOES NOT INCLUDE DAMBAR
Freescale Semiconductor, Inc.
44 MAC7100 Microcontroller Family Hardware Specifications MOTOROLA
Figure 23. 208-Pin MAP BGA Mechanical Dimensions (Case No. 1159A-01)
0.3 M YXZ
0.1 M Z
ALL DIMENSIONS ARE IN MILLIMETERS. SPHERICAL CROWNS OF THE SOLDER BALLS. EFFECT OF MARK ON TOP SURFACE OF PACKAGE. Freescale Semiconductor, Inc.
45 MAC7100 Microcontroller Family Hardware Specifications MOTOROLA
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MAC7100EC/D , Rev. 0.1, HOW TO REACH US: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo, 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre
2 Dai King Street
Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or in tegrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assu me any liability arising out of the application or use of any product or circuit, and specifica lly disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications c an and do vary in different applications and actual performance may vary over time. All operati ng parameters, including “Typicals” must be validated for each customer application by cust omer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications in tended to support or sustain life, or for any other application in which the failure of the Motoro la product could create a situation where personal injury or death may occur. Should Buyer purc hase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distri butors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such un intended or unauthorized use, even if such claim alleges that Motorola was negligent regardi ng the design or manufacture of the part. MOTOROLA and the Stylized M Logo are register ed in the U.S. Patent and Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2003 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MAC7100EC/D , Rev. 0.1, HOW TO REACH US: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo, 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or in tegrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assu me any liability arising out of the application or use of any product or circuit, and specifica lly disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications c an and do vary in different applications and actual performance may vary over time. All operati ng parameters, including “Typicals” must be validated for each customer application by cust omer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications in tended to support or sustain life, or for any other application in which the failure of the Motoro la product could create a situation where personal injury or death may occur. Should Buyer purc hase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distri butors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such un intended or unauthorized use, even if such claim alleges that Motorola was negligent regardi ng the design or manufacture of the part. MOTOROLA and the Stylized M Logo are register ed in the U.S. Patent and Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2003 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
48 MAC7100 Microcontroller Family Hardware Specifications MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Mechanical Information Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...