MAC08BT1_05 ONSEMI | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 7

Technical content

Features

  • Sensitive Gate Trigger Current in Four Trigger Modes
  • Blocking V oltage to 600 V olts
  • Glass Passivated Surface for Reliability and Uniformity
  • Surface Mount Package
  • Pb−Free Packages are Available MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Peak Repetitive Off−State Voltage (Note 1) (Sine Wave, 50 to 60 Hz, Gate Open, TJ = 25 to 110°C) MAC08BT1 MAC08MT1 VDRM, VRRM 200 600 V On−State Current RMS (TC = 80°C) (Full Sine Wave 50 to 60 Hz) IT(RMS) 0.8 A Peak Non−repetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, T C = 25°C) ITSM 8.0 A Circuit Fusing Considerations (Pulse Width = 8.3 ms) I2t 0.4 A2s Peak Gate Power (TC = 80°C, Pulse Width /C0118 1.0 /C0109s) PGM 5.0 W Average Gate Power (TC = 80°C, t = 8.3 ms) PG(AV) 0.1 W Operating Junction Temperature Range TJ −40 to +110 °C Storage Temperature Range Tstg −40 to +150 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. V DRM and VRRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. THERMAL CHARACTERISTICS Characteristic Symbol Max Unit Thermal Resistance, Junction−to−Ambient PCB Mounted per Figure 1 R/C0113JA 156 °C/W Thermal Resistance, Junction−to−Tab Measured on MT2 Tab Adjacent to Epoxy R/C0113JT 25 °C/W Maximum Device Temperature for Soldering Purposes for 10 Secs Maximum TL 260 °C TRIAC

0.8 AMPERE RMS

Preferred devices are recommended choices for future use and best overall value. MT1 G MT2 PIN ASSIGNMENT

3 Gate

4 Main Terminal 2

http://onsemi.com SOT−223 CASE 318E STYLE 11 MARKING DIAGRAM AYW AC08x /C0071 /C0071 A = Assembly Location Y = Year W = Work Week AC08X = Device Code x= B or M /C0071 = Pb−Free Package (Note: Microdot may be in either location) Device Package Shipping †

ORDERING INFORMATION

MAC08BT1 SOT−223 1000 Tape & Reel MAC08MT1 SOT−223 1000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. MAC08BT1G SOT−223 (Pb−Free)

1000 Tape & Reel

MAC08MT1G SOT−223 (Pb−Free)

MAC08BT1, MAC08MT1 http://onsemi.com ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted; Electricals apply in both directions.) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) T J = 25°C TJ = 110°C IDRM, IRRM − 200 /C0109A /C0109A ON CHARACTERISTICS Peak On−State Voltage (Note 2) (IT = /C00341.1 A Peak) VTM − − 1.9 V Gate Trigger Current (Continuous dc) All Quadrants (VD = 12 Vdc, RL = 100 /C0087) IGT − − 10 mA Holding Current (Continuous dc) (VD = 12 Vdc, Gate Open, Initiating Current = /C003420 mA) IH − − 5.0 mA Gate Trigger Voltage (Continuous dc) All Quadrants (VD = 12 Vdc, RL = 100 /C0087) VGT − − 2.0 V DYNAMIC CHARACTERISTICS Critical Rate of Rise of Commutation Voltage (f = 250 Hz, ITM = 1.0 A, Commutating di/dt = 1.5 A/mS On−State Current Duration = 2.0 mS, V DRM = 200 V, Gate Unenergized, TC = 110°C, Gate Source Resistance = 150 /C0087, See Figure 10) (dv/dt)c 1.5 − − V//C0109s Critical Rate−of−Rise of Off State Voltage (Vpk = Rated VDRM, TC= 110°C, Gate Open, Exponential Method) dv/dt 10 − − V//C0109s 2. Pulse Test: Pulse Width ≤ 300 /C0109sec, Duty Cycle ≤2%. + Current + Voltage VTM IH Symbol Parameter VDRM Peak Repetitive Forward Off State Voltage IDRM Peak Forward Blocking Current VRRM Peak Repetitive Reverse Off State Voltage IRRM Peak Reverse Blocking Current Voltage Current Characteristic of Triacs (Bidirectional Device) IDRM at VDRM on state off state IRRM at VRRM Quadrant 1 MainTerminal 2 + Quadrant 3 MainTerminal 2 − VTM IH VTM Maximum On State Voltage IH Holding Current

All polarities are referenced to MT1. With in−phase signals (using standard AC lines) quadrants I and III are used. Figure 1. PCB for Thermal Impedance and Power Testing of SOT-223 BOARD MOUNTED VERTICALLY IN CINCH 8840 EDGE CONNECTOR. BOARD THICKNESS = 65 MIL., FOIL THICKNESS = 2.5 MIL.

Figure 2. On-State Characteristics Figure 3. Junction to Ambient Thermal Figure 4. Current Derating, Minimum Pad Size Figure 5. Current Derating, 1.0 cm Square Pad Figure 6. Current Derating, 2.0 cm Square Pad

50 OR 60 Hz

Figure 7. Current Derating

Figure 8. Power Dissipation Figure 9. Thermal Response, Device Figure 10. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Voltage (dv/dt)c

200 VRMS

Note: Component values are for verification of rated (dv/dt) c. See AN1048 for additional information. Figure 11. Typical Commutating dv/dt versus Figure 12. Typical Commutating dv/dt versus

Figure 13. Exponential Static dv/dt versus Figure 14. Typical Gate Trigger Current Variation

600 Vpk

Figure 15. Typical Holding Current Variation Figure 16. Gate Trigger Voltage Variation

MAC08BT1, MAC08MT1 http://onsemi.com PACKAGE DIMENSIONS SOT−223 (TO−261) CASE 318E−04 ISSUE L STYLE 11: PIN 1. MT 1 2. MT 2 3. GATE 4. MT 2 D E b e 12 3 0.08 (0003) A C NOTES: /Em/figure1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. /Em/figure2. CONTROLLING DIMENSION: INCH. 1.5 0.059 /C0466mm inches/C0467SCALE 6:1 3.8 0.15 2.0 0.079 6.3 0.2482.3 0.091 2.3 0.091 2.0 0.079 SOLDERING FOOTPRINT* HE DIM A MIN NOM MAX MIN MILLIMETERS 1.50 1.63 1.75 0.060 INCHES A1 0.02 0.06 0.10 0.001 b 0.60 0.75 0.89 0.024 b1 2.90 3.06 3.20 0.115 c 0.24 0.29 0.35 0.009 D 6.30 6.50 6.70 0.249 E 3.30 3.50 3.70 0.130 e 2.20 2.30 2.40 0.087 0.85 0.94 1.05 0.033 0.064 0.068 0.002 0.004 0.030 0.035 0.121 0.126 0.012 0.014 0.256 0.263 0.138 0.145 0.091 0.094 0.037 0.041 NOM MAX L1 1.50 1.75 2.00 0.060 6.70 7.00 7.30 0.264 0.069 0.078 0.276 0.287 HE − − 0° 10° 0° 10° /C0113 /C0113 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 MAC08BT1/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.