Microcontroller

MAB8441T

NXP Semiconductors

SINGLE-CHIP 8-BIT MICROCONTROLLER August 1990

Manufacturer: NXP Semiconductors

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© 8:bit: CPU, ROM, RAM and 1/0 in a single 28-lead DIL package @ 2K, 4K or 6K ROM bytes plus a ROM-less version © 64 or 128 RAM bytes © 20 quasi-bidirectional 1/O port lines © Two testable inputs: one of which can be used to detect zero cross-over, the other is also the external interrupt input © Single level vectored interrupts: external, timer/event counter, serial I/O © Serial I/O that can be used in single or multi-master systems (serial 1/O data via an existing port line and clock via a dedicated line) © 8-bit programmable timer/event counter © Internal oscillator, generated with inductor, crystal, ceramic resonator or external source © Over 80 instructions (based on MAB8048) all of 1 or 2 cycles © Single 5 V power supply (+ 10%) © Operating temperature ranges: Oto+ 70°C MAB84X1 family -40to+ 85°C MAFB4X1 family only —40 to + 110°C MAF84AX1 family only PACKAGE OUTLINES MAB8401B: 28-lead ‘Pigay-back’ package (with up to 28-pin EPROM on top). MABB401WP: 68-lead plastic leaded chip-carrier (PLCC) (SOT 188). MAB/MAF8421/41/61P: 28-lead DIL; plastic with internal heat spreader (SOT117). MAF84A21/41/61P: 28-lead DIL; plastic with internal heat spreader (SOT 117). MAB8421/41/61T: 28-lead mini-pack; plastic (S028; SOT 136A), “August 1990 23 @@ 7110826 0074753 497 ; -

crock} ATA i] eae Skevres Ea [ sara] Ex 30, “ft FREQ TEST ff ff if i | fF Iai? lot (a tai} Lose REGISTER | RecisteRo ] | Reaistens | LOGIC UNIT REGISTER [Recisten« | oo pecdoer os = OND verre ADAST ‘BRANCH FAG Lose CARRY DATA STORE intro RESET. XTALT XTAL2 TEST INTERRUPT INITIALIZE — OSCILLATOR BA0r 128 BYTES Fig. 1a Block diagram of the MAB84X1 family. | er eran 4 es | ~~ aT yx | eR i3 z | z mw i | | Fig. 1b Replacement for dotted part in Fig. 1a Fig. 1c Replacement of dotted part in Fig. 1a for the MAB8401WP bond-out version. for the MAB8401B ‘Piggy-back’ version, 2-4 August 1990 _ Ml 7110826 0074754 323 i

Single-chip 8-bit microcontroller MAF BAXY FAMILY PINNING a2] Uf v SDA/P2.3 P21 seux[3 | [25] P20 poo [a] [25] P17 vor [5] [za] P10 po2 [6] [23] P15 03 [7] weggany 22) PM mapedat ros [3] [20] Piz ros {i0] fia] ris ror [ia] [ia] P10 int/To [12] RESET n fl [ie] xrat2 Veg [a] [is] xracs 72445293 Fig. 2 Pinning diagram for mask-programmable devices MAB8421, MAB8441, MAB8461 and for MAB8401 ‘Piggy-back’ version bottom pinning (for top pinning see Fig. 3). PINNING DESIGNATION Vss 14 Ground Vec 28 Power supply, + 5 V PO.0-PO.7 4-11 Port 0, 8-bit quasi-bidirectional !/O port P10-P1.7 18-25 Port 1, 8-bit quasi-bidirectional 1/O port with 8-bit LED driver 2.0 —P2.3 26, 27,1,2 Port 2, 4-bit quasi-bidirectional I/O port; SDA/P2.3 is the serial data |/O in serial 1/0 mode SCLK 3 Bidirectional clock for serial 1/O INT/TO 12 External interrupt input (sensitive to a negative-going edge min LOW > 7 clock pulses, min HIGH > 4 clock pulses), testable using the JTO or JNTO instructions, 1 13 Input pin, testable using the JT1 or JNT1 instructions. It can be designated as event counter input using the STRT CNT instruction. It can also be used to detect zero cross-over of slowly moving AC inputs. RESET 7 Input to initialize the processor (active HIGH). XTALI 15 Connection to timing component (crystal) that determines the frequency of the internal oscillator. It is also the input for an external clock source. XTAL2 16 Connection to other side of the timing component. August 1990 25 M@@ 7110826 0074755 2bT

FAMILY . MAB8401B (top pinning) PIN DESIGNATION 0 designation pin function Yec [7] Veco SSS Vss 14, 22 Ground ar]? ] Yee Vee 1,26-28 Power supply, +5 V arf] [25] Voc AO-A12 10-3, 25, 24, 21,23, 2 Address outputs sofa] AB DO-D7 11-13, as[s] a9 15-19 Data inputs aah a an PSEN 20 Program store enable a3 ss a2fe] Br] aro arto] [20] FSEN Fig. 3 Pinning diagram for MAB8401B ‘Piggy-back’ Ao [a] 07 version top pinning (for bottom pinning see Fig, 2); to access a 2732 or 2764 EPROM. vofii] [78] 06 ot [aa] Ds Note o2 fa] Te] oe Access times for ROMS/EPROMS to be below 1 ys. Vs [74] 03 Tzee190 A0-A12K AO-ATD_| Teddress bus) em EHD 00-p7[_b0-07_» EPROM < F20-723> max. BK bytes ‘MABS401WP SCLK z BOND OUT CHIP intro RESET XTALI Ves Yoo xTAL2 Nec Vss Fig. 32 Connection of EPROM to “Piggy-back’ package MAB8401B. 72079628 M@ 7110826 OOF8?S6 OR

26 August 1990 |

Single-chip 8-bit microcontroller MAF84AX1 FAMILY 2 6 Psst tseaeree: &é € 23 ee FF se cre SHH HENHEU ERE RHEE {10 J [60_} {i (59 | p13 Po2 [iz] (se7] p12 P03 [13] [67] Pat pos | 14) ("s6"] P10 Pos | 15] (“s5" | reset Pos [16] (54 ] xtar2 P07 7] (C337] xraur oo (Te MABB4OIWP (ca) act hs (si) cuk iwr/to [20] (“s0] Psen nay [49] 07 De (48_| 06 orf 23°) [47] 05 o2{ 24) [46 | 04 aiz {725} [45] 03 [26 } Cas] Fig. 4 Pinning diagram; PLCC. CHIP CARRIER DESIGNATION designation pad no. function . Vss 35 Ground Veco 68 Power supply, + 5 V PO.0-PO.7 = 4-5, 12-17 Port 0, 8-bit quasi-bidirectional I/O port P1.0—P1.7 56—59, 62-65 Port 1, 8-bit quasi-bidirectional 1/O port with 8-bit LED driver P2.0 — P2.3 66, 67, 1,2 Port 2, 4-bit quasi-bidirectional 1/0 port; SDA/P2.3 is the serial data I/O in serial 1/0 mode SCLK 3 Bidirectional clock for serial 1/O INT/TO 20 External interrupt input (sensitive to a negative-going edge), testable using the JTO or JNTO instructions August 1990 27 WM 711086 007475? O32

T1 21 Input pin, testable using the JT1 or JNT1 instructions. It can be designated as event counter input using the STRT CNT inctruction. It can also be used to detect zero cross-over of slowly moving a.c. inputs. RESET 55 Input to initialize the processor (active HIGH) XTALt 53 Connection to timing component (e.g. crystal) that determines the frequency of the internal oscillator. It is also the input for an external clock source. XTAL2 54 Connection to other side of the timing component EXsI 34 External serial I/O interrupt (active-LOW) for emulation of MAB/F8422/42. A0-A12 41-36, 33-28 Program memory address outputs (active HIGH); AO = LSB, 25 A12 = MSB. Address output change after begin $3 of TS8. DO-D7 22-24, 45—49 Data input lines (active HIGH) used for reading external program memory. DO = LSB, D7 = MSB. cLK 51 Clock output buffered from XTAL2. On the positive-going edge the (internal) ¢ clock goes HIGH. PSEN 50 Program store enable. This signal is used for enabling the external EPROM (e.g. on the ‘Piggy-back’ version). For emulation, it enables the emulation memory and it indicates machine cycles. Active LOW during TS9,*TS10 of each machine cycle and TS1 of _ the following machine cycle. C1 18 Cycle 1 indication output (active LOW). During emulation, this signal indicates the opcode fetch cycle (useful for external instruction decoding, real-time trace). Active from start of TS10 of the cycle preceding cycle 1, until the start of TS10 of cycle 1, HALT 52 Halt input (active LOW). |f activated, the current instruction is finished and the microcontroller stops execution (HALT mode). The next program counter address is available on the address bus. Program counter and timer/event counter are no longer updated. The serial I/O finishes the current transmit/receive action and goes into the idle state. Interrupts are not sampled in the HALT mode, they are only sampled when the microcontroller is running. Interrupt routines can be single-stepped as a normal program. INTA 19 Interrupt acknowledge output (active LOW). It indicates any interrupt acception. Active from start of TS8 of the interrupted cycle, until start of TS7 of the second cycle of the (internally forced ‘CALL vector address’ instruction. During INTA active, the address bus shows the address that has been saved in the stack (return address) ; the C1 output indicates opcode fetch cycles as if a user CALL was executed. EMU20 6 Emulate 20-pin version MAB/F8422/42 (active-LOW). * TS = Time slot, where 10 TS = 1 cycle. M@™@ 7110826 0074758 179 a 2-8 August 1990 | |

Single-chip 8-bit microcontroller MAFB4AX1 FAMILY FUNCTIONAL DESCRIPTION (for more detail see 84XXX family specification) Bond-out version MAB8401WP- The bond-out version is a microcontroller that contains no on-board ROM, but has all address and data Jines brought out to access an external ROM or EPROM. Thus, this version has more pins than the standard microcontrollers with on-board ROM. It has all the features of the other members of the MAB84X1 family, including emulation facilities for the MAB/F8422/42 (20-pin version), It can address 8K bytes of external ROM. The RAM has 128 bytes, Piggy-back version MAB8401B The Piggy-back version is a special package that has standard pinning to the bottom which facilitates insertion as a mask-programmed device. An EPROM is mounted on top in an additional socket. Thus, the total package height is greater than the standard DIL package. Emulation of the 8422/42 is not possible, Program and data memory The program memory (ROM) is mask-programmed at our factory. Because the MAB84X1 family offers a range of ROM capacities to suit the application, ROM expansion is not required. Figure 5 shows the program memory map. Program memory is arranged in banks of 2K bytes, that are selected by SEL MB instructions. 3401/41/81 MAB461 a magi 7 a :— SELMB2 ca oa MABB441 Pyog5, i> 6ap- — RAM { setresses . indirectly

4 SELMBI 2 2 cup pete

waged [2048 — Es 7 BANK1 : - SELMBO WORKING | Oty le recisens | Sdéresabie sone 8x8 is selected a am Fr | 1028 eeekaanteuns. 2a Ro] _| wa the SEL MB3 instruction 23 LEVEL __ STACK 1 STAC . 2 2 USER RAM * ; 6x8 7 7] BANKO WORKING directly REGISTERS | agcressable 5 locaton? terfesuner mt S8 | seteces 6 : rupt vector ) 5| location: senat 1/0 interrupt o[ no) 4 vector 7284536.5 3 location 3 : external interrupt 2 vector 1 Fig. 6 The data memory map. ty location 0: reset vector 72045366 Fig. 5 The program memory map. August 1990 29 MH 7110826 0074759 905 a

FUNCTIONAL DESCRIPTION (continued) The data memory (RAM) consists of 64 or 128 bytes (8-bit words). All locations are indirectly addressable using RAM pointer registers and up to 16 designated location can be addressed directly. The memory also includes an 8-leve! program counter stack addressed by a 3-bit stack pointer. Figure 6 shows the data memory map. On-chip peripheral functions In addition to the CPU and memories, an interrupt system, I/O facilities, and an 8-bit timer/event counter are integrated on-chip to assist the CPU in repetitions, complicated or time-critical tasks. The 1/0 facilities include the 1/O pins, parallel ports and a serial 1/O port, consisting of a data line SDA shared with a parallel port line (P2.3), and a dedicated clock line SCLK. 1/0 facilities The MAB84XxX family has 23 1/0 lines arranged as: © A parallel port of 4 lines (P2.0—P2.3). © A serial I/O consisting of a data line shared with a parallel port line (P2.3) and a separate clock line SCLK; @ An external interrupt and test input INT/TO, which when used as a test input can be tested by the conditional jump instructions JTO or JNTO; © A test input T1, which can alter program sequences when tested by conditional jump instructions JT1 or JNT1. T1 can also be used as an input to the timer/event counter or to detect zero cross-over of slowly moving AC signals. All parallel port lines are available in three optional output configurations (except P2.3 — option 1 only): © Option 1; open drain output without pull-up transistor (Fig. 7(a)) © Option 2; open drain output with pull-up transistor (Fig. 7(b)) © Option 3; push-pull output with pull-up transistor (Fig. 7(c)) 'f the inputs and outputs on a port are mixed (mixed-mode), the inputs should be options 1 or 2 but not option 3. This prevents cross-currents via TR2 and an external connection to ground, while switching the output on the same port and in parallel, masking the inputs with logic 1s. The MAB84X1 family serial I/O interface has been designed to eliminate the heavy processing load imposed upon a normal microcontroller performing serial data transfer. Whereas a normal microcon- troller must regularly monitor the serial data bus for the presence of data, the serial |/O interface detects, receives and converts the serial data stream into a parallel format without interrupting the execution of the current program. An interrupt is sent to the microcontroller only when a complete byte is received. Then, the microcontroller reads the data byte in one instruction. Likewise, for transmission, the serial I/O interface performs parallel to serial conversion and subsequent serial output of the data and the microcontroller is only interrupted in the execution of its programmed tasks when a complete byte has been transmitted. The design of the serial 1/O interface allows any number of MAB84X1 family devices and peripheral circuits with |?C bus compatibility to be interconnected by the two-line serial bus. This is achieved by allocating a specific 7-bit address to each device and ensuring that a device reacts only to a message preceded by its own address or the ‘general call’ address. Address recognition is performed by the interface hardware so that the microcontroller need only be interrupted when a valid address is received. This saves significant processing time and memory space compared to a conventional microcontroller with a software serial interface. When the address facility is not required, for instance in a system with only two microcontrollers, direct data transfer is possible. In multi-master systems, an automatically invoked arbitration procedure prevents two or more devices transmitting simultaneously. mm 7110826 0074760 be? AA

210 August 1990

Single-chip 8-bit microcontroller MAF84X1 sle-chip 8-it mic : MAF84AX1 FAMILY ANL, ORL 2 ort F "1 2 tm cue 10 port ine pulse a Se nee la) ANL, ORL av mere ol am cue 1/0 port ine ite a sok Ser ne ANL, ORL y +5] +5} [1 13 Tee imwmai__|To : Bi = & ° a 0 port tne ck TR Pulse = Siew oe, te rzesss43 Fig. 7 Quasi-bidirectional 1/0 interface with (a) open drain output without pull-up transistor, (b) open drain output with pull-up transistor, (c) push-pull output with pull-up transistor. Serial 1/0 interface Figure 8 shows the serial I/O interface. The clock line of the serial bus has exclusive use of pin 3 (SCLK) while the data line shares pin 2 (serial data) with the 1/0 line P2.3 of port 2. When the serial 0 is enabled, P2.3 is disabled as a parallel port line (P2.3 and SCLK only open drain). The microcontroller and interface communicate via the internal microcontroller bus and the Serial Interrupt Request line. Data and information controlling the operation of the interface are stored in four registers: © data shift register SO, © serial I/O interface status word S1, © serial clock control word $2, © address register SO’ August 1990 21 MB 7110826 0074761 Sb3 mm

“FUNCTIONAL DESCRIPTION (continued) Serial 1/0 interface (continued) Data shift register SO SO is the shift register that converts serial data to parallel format and vice versa. A pending interrupt is generated only after a complete byte has been transmitted, or after a complete data byte, specific or general call address has been received. The most significant bit is transmitted first. Serial |/O interface status word $1 $1 provides information about the state of the interface and stores interface control information from the microcontroller. The four most significant bits are common to both read and write instructions, with a separate 4 read-only control bits and 4 write-only interface status bits. MST and TRX These bits determine the operating mode of the serial I/O interface (Table 2). Table 1 Operating modes of the serial |/O interface. slave receiver master receiver slave transmitter master transmitter BB: Bus Busy This bit indicates the status of the bus. PIN: Pending Interrupt Not PIN = ‘0’ indicates that there is an interrupt pending. This causes a Serial Interrupt Request when the serial interrupt mechanism is enabled. ESO: Enable Serial Output The ESO flag enables/disables the serial 1/O interface: ESO = logic 1 enables ESO = logic 0 disables BCO, BC1 and BC2 These bits indicate the number of bits received or transmitted in a serial data stream. Bits ESO, BCO, BC1 and BC2 can only be written via software. AL: Arbitration Lost The AL flag is set via the hardware when the serial |/O interface, as a master transmitter, loses the bus arbitration procedure. AAS: Addressed As Slave This flag is set via the hardware when the interface detects either its own address or the ‘general call’ address as the first byte of a transfer and if the interface has been programmed to operate in the address recognition mode, ““M 7110826 OO747be 4TT

212 August 1990 | |

" - oe as MAF84X1 Single chi ingle chip 8-bit microcontroller MAFB4AX1 FAMILY ADO: Address Zero This flag is set via the hardware after the general call address is detected when the interface is operating in the address recognition mode. LRB: Last Received Bit This contains either the last data bit received or, for a transmitting device in the acknowledge mode, the acknowledge from the receiving device. Bits AL, AAS, ADO and LRB can only be read via software. Serial clock control register S2 Bits 0 to 4 of S2 are used to set the frequency of the serial clock signal. When a 4,43 MHz crystal is used, the frequency of the serial clock can be varied between 100 kHz and 720 Hz. An asymmetrical clock with a HIGH to LOW ratio of 3 to 1 is produced by setting bit 5. The asymmetrical clock allows a microcontroller more time per clock period for sampling the data line, making the timing of this action less critical. Bit 6 is used to activate the acknowledge mode of the serial 1/O. S2 is a write-only register. Address register SO’ The address register contains the 7-bit address back-up latches and the bit (ALS) used to enable/disable the address recognition mode. Only when ESO = 0 can the address register be written using the MOV SO,A and MOV SO,#data instructions. Serial I/O interrupt logic The interrupt logic is enabled by the EN Si! instruction and disabled by DIS SI. When the interrupt logic is enabled, a pending interrupt results in a serial 1/O interrupt to the controller, causing a jump to location 5 in the ROM, When the logic is disabled, the presence of an interrupt is still indicated by the PIN bit in register S1, Therefore, an interrupt can still be serviced but a vectored interrupt will not occur. Interrupt system External events and real-time on-chip peripherals require servicing by the CPU asynchronous to the execution of any particular section of code. To tie the asynchronous activities of these functions to normal program execution, three single-level nested interrupts are provided. Each interrupt vectors to a separate location in the program memory for its service program. Each source can be individually enabled or disabled, When more than one interrupt occurs simultaneously, their priority will be: (1) external, (2) serial 1/O and, (3) timer/event counter. An additional external interrupt can be created using the timer/event counter interrupt. August 1990 2413 @@ 7110826 0OO747b3 336

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244 August 1990 \\|

Single-chip 8-bit microcontroller MAF84AX1 FAMILY ‘Test input T1 The T1 input line can be used as: © a test input for branch instructions, ‘© an input for zero voltage cross-over detection, © an external input to the event counter. An internal pull-up transistor is provided as a ROM mask option. This is useful when the input is from a switch or standard TTL output. When T1 is used as a test input, the JT1 or JNT1 instructions test for a HIGH or a LOW respectively. When used for zero-cross detection purposes, the T1 input must be coupled through a capacitor of typical value 1 uF and operation carried out using the T1 input without the pull-up transistor. The maximum input voltage amplitude is 3 V (peak-to-peak), with a maximum operational frequency of 1 kHz. The T1 input has an on-chip DC offset circuit which self-biases the input to its exact switching level of 1 V. As a consequence a smal! change will cause a digital transition to occur. The switching level of the T1 input circuit is within the bias voltage of + 135 mV. Upon each positive cycle on the pin, the event counter is incremented and an overflow will set the timer flag TF. Zero cross-over detection used in conjunction with the timer/event counter interrupt, is useful in thyristor control of power equipment. Figure 9 illustrates, (a) the input waveform, (b) the input diagram and {c) the on-chip self-stabilized bias. v rer0~ cross | \\ | wmput_— aa ta 3V max OC componest 7 (=p) AC source | tar T MaB.gaxt MABB4X1 interpretation 7297897 1 v (a) to bias voltage Ve, tn ° tur 7297599 1 t AC source ——| Ti /event counter (b) Ya 7297598.1 {c) Figure 9 Zero-cross detection circuitry; (a) input waveform, (b) input diagram, (c) on-chip self-stabilized bias, The operation of T1 as an input to the timer/event counter is described under the heading Timer/ event counter. August 1990 215 MB 7110826 OO747b5 109 a

Ten pins are provided that can sink high currents: — P2.3 (serial data), pin 2 5 mA at 0,45 V (open drain), —SCLK, pin 3 5 mA at 0,45 V (open drain), —P1.0—P1.7* 10 mA at 1V Timer/event counter An 8-bit binary up-counter is provided. This can count external events, machine cycles divided by 32, ‘or machine cycles directly. When used as a timer, the input to the counter is either the overflow or input of a 5-bit prescaler. When used as an event counter, LOW to HIGH transitions on T1 (pin 13) are counted, The maximum rate at which the counter may be incremented is once every machine cycle (200 kHz for a 5 ys machine cycle). Figure 10 illustrates the timer/event counter. PRESCALER XTAL+30 +32 (internal cock freaveney}| Star timer PS=1, PS=0 uma toad or reas UY fas as EDGE 8-BIT | % COUNTER FLAG x START TIMER Geared Si srant counren ones Stor Tate /COUNTER resoue Fig. 10 The timer/event counter. Differences betwoen the MAB8O21 and MABEO4B microcontrollers, and the MABSA4X1 family. 8088 wor, ] 8421, 8441, 8461 | ROM capacity (bytes) «K 1K ROMiess =, 2K, 4K, 6K | RAM capacity (bytes) 64 64 128, 64, 64, 128, 128 paraie 170 lines Brera | rere peeve) ingle nous 1 3 2 serra /O. no no ‘yes, 2-line muiti-transmitter tree Bon Bon Bon praeater mod.32 | mod. 32 mod. 1 & mod. 32 machine cycle time (ys) 10 25 5 Tor clock (MH) 3 6 6 snetuction et 2021 a04e 8088 wath omsions; Siew ser 1/0 instructions, | 2 new Feta rmtroctos | Zhew convo! nsruetons; | | ‘ new cond, branch instruction | wnterrupts none 2 3 j extern! external timer! feral VO | vent counter | timerfevent counter | ‘no. of pins (DIL) a 40 68 (PLCC), 28 * P1.0 to P1.7 may be connected in parallel if their logic outputs are always the same, @§ 7110826 OO747bb O4S

216 August 1990 |

, abit mi F84X1 Single-chip 8-bit microcontroller MAF84AX1 : FAMILY OSCILLATOR CIRCUITRY Clock frequency is determined by using the internal oscillator or by connecting an external clock to XTAL1, Where the internal oscillator is used, the frequency is set by a crystal between XTAL1 and XTAL2, or by a ceramic resonator or an inductor, each with two associated capacitors, between XTAL1 and XTAL2 (see Fig. 11a). A machine cycle consists of 10 states, each state being 3 oscillator periods. The common 6 MHz crystal gives a 5 us machine cycle, The MABB4X1 family has dynamic logic, and therefore, for adequate refreshing the oscillator frequency must be at least 1 MHz. XTALY XTAL2. 1. Crystal — AT-cut 2. Ceramic resonator C1 =C2=27 pF C1 may be trimmed

10 BME Cy <6,75 pF (parasitic capacitance)

Fig. 11a Quartz crystal or ceramic resonator mode. LC oscillator timing c 3,0 MHz 33 pF 100 wH 2 4,0 MHz 33 pF 56 wH oem XTAL2 4,4 MHz 33 pF 47 uH reesesa.2 5,0 MHz 33 pF 33 uH 6,0 MHz 33 pF 22 uH Fig. 11b LC pi-network. Vee Drive XTAL1 ! Leave XTAL2 open []r= Driver may be high-speed CMOS or any TTL r ty, te << 10 ns XTALI rears Fig, 11¢ External drive. August 1990 247 Mi 7110826 00747b7 Ta)

The program status word (PSW) is an 8-bit word in the CPU which stores information about the current status of the microcontroller (Fig. 12). The PSW bits are: bits 0, 1 and 2 — stack pointer bits (SPg, SP7, SP2); bit3 — prescaler select (PS); 0 = divide-by-32; 1 = no prescaling; bit 4 — working register bank select (RBS): 0 = register bank O 1 = register bank 1; bit 5 — not used (1); bit6 — auxiliary carry (AC): half-carry bit is generated by an ADD instruction and used by the decimal adjust instruction DA A; bit? — carry (CY): the carry flag indicates that the previous operation has resulted in an overflow of the accumulator. BeBe Ge eck stack pointer [ev |e] + [ros] rs [ra], [sro] ry sa Use rzs9169 Fig. 12 Program status word, All bits can be read using MOV A, PSW and bit 3 can be written with MOV PSW, A. Bits 6 and 7 can be set and cleared by CPU operation. Bit 4 is changed by the SEL RB instruction, bit 3 by the MOV PSW,A instruction, and bits 0, 1 and 2 by the CALL, RET or RETR instructions and when an interrupt occurs. Bits 4, 6 and 7 are stored in the program counter stack during sub- routine and interrupt calls, These bits are restored to the PSW with RETR (return and restore) instruction. Note: The RET instruction has no restore feature and should not be used at the end of an interrupt because this would leave any further interrupts disabled. The MAB84X1 family has arithmetic, logical and branching capabilities. The DA A, SWAP A, and XCHD instructions simplify BCD arithmetic and the handling of nibbles. The MOVP A,@A instruction permits efficient table look up from the current ROM page. The conditional branch logic within the processor enables several conditions, internal and external to the processor, to be tested by the user’s program. Table 2 lists the conditional branch instructions used to change the program execution sequence. The DJNZ instruction decrements a designated register and branches if the contents are not zero. This instruction makes the register an efficient program loop counter. The JMPP @A instruction allows multiway branches to destinations indirectly addressed by the contents of the accumulator. M@@ 7110826 00747b8 918 a 2-18 August 1990 | |

Single-chip 8-bit mi MAF84X1 gle-chip 8-bit microcontroller MAF84AX1 FAMILY : Table 2 Conditional branches TEST JUMP CONDITION JUMP INSTRUCTION accumulator O or non-zero JZ, INZ accumulator bit test 1 JBO to JB7 carry flag Oort INC, JC timer overflow flag 1 JTF test input INT Oor1 INTO, JTO test input T1 Oorl JNT1, JT1 test flag O 1 JFO test flag 1 1 JF1 register non-zero DJNZ RESET A positive-going signal on the RESET input: — sets the program counter to zero, — selects location 0 of memory bank 0, and register bank 0, — sets the stack pointer to zero (‘000'B); pointing to RAM address 8, — disable the interrupts (external, timer and serial 1/0), — stops the timer/event counter, then sets it to zero, — sets the timer prescaler to divide-by-32, — resets the timer flag, — sets all ports to logic ‘1’ (input mode), — sets the serial I/O to slave receiver mode and disables serial 1/O. Automatic reset at power-up may be obtained by connecting the RESET pin to Vcc through a 1 uF capacitor C, together with a diode to Vgg (cathode to RESET pin). This arrangement is satisfactory, if both the voltage (Vc) rise time and the oscillator start-up time do not exceed either 1 or 10 ms respectively. The power-on reset circuit is shown in figure 13, At power-on the current drawn by RESET commences to charge the capacitor C. The difference between this increasing capacitor voltage and Vcc is known as VRESET- The charging circuit is designed to hold VREgeT above the lower threshold of a Schmitt trigger arrangement long enough to effect a complete reset. The minimum time required; is the oscillator start-up time plus two machine cycles. 60 7298137 ne LEE manny aenene a LZ Z we poe Lay LV @| FP aoe = Viti iii ty 72981362 % : 2 F) 4 3 VR) Fig. 13 Typical power-on Fig. 14 Power-on reset input reset circuitry. characteristics (typical). August 1990 2-19 MB 7110826 0074769 654

The instruction set consists of over 80 one and two byte instructions and is based on the MAB8048 instruction set. New instructions include those for serial |/O operation and memory bank selection. Program code efficiency is high because all ROM locations on a 256 byte page require only a single byte address. Table 3 gives the instruction set of the MAB84X1 family and Table 4 shows the instruction map. The following symbols and abbreviations are used. Note: During development of software on a PMDS or similar system, it is important to ensure that no jump instruction (direct or indirect), outreaches the final address range of the device. symbol description A the accumulator AC the auxiliary carry flag addr program memory address (11-bits) Bb bit designation (b = 0Q—7) BS the bank switch c carry flag CLK clock signal CNT event counter D nibble designation (4-bits) DBF program memory bank flip-flop data number or expression (B-bits) FO, F1 flags O and 1 i interrupt INT external interrupt Pp ‘in-page’ operation designation Pp Port designation (p = 1, 2 or 4—7) PSW program status word Rr register designation (r = 0, 1 or 0-7) SP stack pointer T timer Tr timer flag TO, T1 | test 0 and 1 inputs # immediate data prefix @ indirect address prefix s current value of program counter + is replaced by ° is exchanged with

220 August 1990

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Single-chip 8-bit microcontrotler Are aX FAMILY Table 5 shows the additional MAB84X1 family instructions (including the five for serial 1/0. operation) that are not part of the MAB8048 instruction set. Table 5 MABB4X1 family instructions not in the MABBO48 instruction set MOV A, S, DEC @Rr SEL MB2 JNTF addr MOV 5S, A DJNZ @Rr, addr SEL MB3 MOV Sp, #data ENSI DISSI Table 6 shows the MAB8048 instructions omitted from the MAB84X1 family instruction set. Table 6 MAB8048 instructions not in the MABB4X1 family instruction set a MOVX A, @R CLR FO * JNU addr ENTO CLK MOVX@R, A CPL FO JFO addr MOVP3 A, @A CLRFI (JF1 addr MOVD A, P CPL FI MOVD P, A ANLD PA * replaced by ORLDP,A JTO INTO. August 1990 2-27 @ 71108626 0074777 920 a

ABSOLUTE MAXIMUM RATINGS. Limiting values in accordance with the Absolute Maximum System (IEC 134) Stress above those listed under ‘Absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device, at these, or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. parece wmbot [min [wae | oni Input voltage on any pin with respect to ground (Vgg) vi -0,5 +7 v Total power dissipation SOT-117, 28-lead DIL Prot - 1 w SOT-136, 28-lead DIL | Prot - 06 w Input/output current for all pins | | except port 1 Tae) - 10 mA Input/output current for port 1 | llo - | 20 mA Storage temperature | Tstg 65 | +150 °c Operating temperature | standard | Tamb 0 +70 oc extended Tamb —40 +85 oc | automotive Tamb —40 +110 °c Ce) —— ic [ | Purchase of Philips’ 1?C components conveys a license under the Ly} 25) Philips’ |?C patent to use the components in the !?C-system lena Weee || provided the system conforms to the I?C specifications defined eee) by Philips. M@™ 7110426 0074778 6b? 2-28 August 1990 |

Single-chip 8-bit microcontroller AA FAMILY DC CHARACTERISTICS Voc = 5 V (10%); Vgg = 0 V; all voltages with respect to Vgg unless otherwise specified Supply current | | MAB Oto + 70 °C loc - 85 mA . | MAF —40 to + 85 OC lec - 100 mA | MAFe4a —40 to + 110 0C lec - 100 mA | | | Inputs. Input voltage LOW | | (except P2.3 and SCLK) | Vit -05 |08 |v Input voltage LOW | (P2.3 and SCLK) Vit 05 | 1,5 Vv Input voltage HIGH | (all inputs except XTAL1, Veco | P2.3 and SCLK) Vin 2 tos | Y | Input voltage HIGH Vv | “"OCTAL1, P2,3 and SCLK) Vint 3,0 oc v | +05 Outputs | Output voltage LOW | (P0.0-P0.7) | 1oL= 1,6 ma VoL - 0,45 v Output voltage LOW | (P1.0-P1.7 for j 8401/11/21/41/61) 1oL12=10mA Voz | - 10 «|v Output voltage LOW | (P2.0—P2.2) loL2= 1,6 mA VoL2 = 0,45 Vv Output voltage LOW (P2.3, SCLK) loLg=5mA VoL3 - 0,45 Vv Output voltage LOW {non-standard pins of bond-out versions) 1oL4=0,4 mA VoL4a - 0,45 iv Output voltage HIGH {all outputs unless open drain) 1oH = —50 nA Vou 24 - v Output leakage current Vss <V1<Vee tlot - 10 HA August 1990 2-29 @@ 7110826 0074779 773 -

AC CHARACTERISTICS (all versions except bond-out) Voc = 5 V + 10%; Vgg = 0 V. ee ee Frequency FXTAL MAB/MAF84X1 MHz MAF84AX1 MHz Cycle time tcy MAB/MAF84X1 us MAF84AX1 us AC CHARACTERISTICS (bond-out versions) Vc = 5 V + 10%; Vgg = 0 V. a fou = 6 MHz Control pulse duration PSEN (9CP) tec 18 9 us ‘Address to PSEN L set-up (1CP) tas 167 - ns Data to PSEN H set-up (1CP + 120 ns) tos 600 - ns Data hold time toR () - ns Address to data-in (10CP—tpg) tap - 1,07 us Time from PSEN L to C1 (3CP) tec 500 - ns Time from iNTA L to PSEN (3CP) PO 500 - ns Time from INTA H to PSEN (6CP) PT 1 - us HALT set-up to PSEN (15CP) tHs 25 - Hs HATT hold time from PSEN (3CP) tHH 500 - ns Note: CP = clock pulse. T1 ZERO-CROSS CHARACTERISTICS Tamb = 0 to + 70 °C; Veg = 5 V + 10%, Vgg = 0 V; CL = 80 pF Zero-cross detection input (T1) peak-topeak AC coupled, C= 1,0uF| Vzx(p.p) | 1 3 Vv Zero-cross accuracy 60 Hz sine wave Azx - +135 | mv Zero-cross detection input frequency (T1) Fzx 0,05 1 kHz 2-30 August 1990 ) { MB 7110826 0074780 415

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Product Information

MAB8441T specifications and overview.

Summary

SINGLE-CHIP 8-BIT MICROCONTROLLER August 1990

Description

SINGLE-CHIP 8-BIT MICROCONTROLLER August 1990

Source title MAB8441T Datasheet(PDF) - NXP Semiconductors

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