M95512 STMICROELECTRONICS | Alldatasheet
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Technical content
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Table 1. Product List Figure 1. Packages
During all operations, VCC must be held stable and within the specified valid range: VCC (min) to VCC (max). All of the input and output signals must be held High or Low (according to voltages of VIH, VOH , VIL or VOL , as specified in Table 13.). These signals are described next. Serial Data Output (Q).This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D).This input signal is used to transfer data serially into the device. It receives in- structions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C).This input signal provides the timing of the serial interface. Instructions, address- es, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select (S ).When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Stand- by Power mode. Driving Chip Select (S) Low se- lects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. Hold (HOLD).The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be se- lected, with Chip Select (S) driven Low. Write Protect (W).The main purpose of this in- put signal is to freeze the size of the area of mem- ory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either High or Low, and must be stable during all write instructions.
Figure 5. SPI Modes Supported
Figure 7. shows the position of the Status Register cates the status of the internal Write Enable Latch. be software protected against Write instructions. Table 3. Status Register Format they are accepted for execution. the memory to be configured as read-only. This is the Software Protected Mode (SPM). the Hardware Protected Mode (HPM). some other device on the SPI bus. Table 4. Write-Protected Block Size
The memory is organized as shown in Figure 7. Figure 7. Block Diagram
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Table 5. Instruction Set
Write or Write Status Register cycle is in progress. bit before sending a new instruction to the device. tinuously, as shown in Figure 10.. cates the status of the internal Write Enable Latch. be software protected against Write instructions. Figure 10. Read Status Register (RDSR) Sequence
the Write Enable Latch (WEL). The instruction sequence is shown in Figure 11.. Register. b6, b5 and b4 are always read as 0. pleted, the Write Enable Latch (WEL) is reset. Figure 11. Write Status Register (WRSR) Sequence
Table 6. Protection Modes Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 6.. ware Protected Mode (HPM) is entered. the Status Register, can be used.
(S) signal can occur at any time during the cycle. ed, if a Write cycle is currently in progress. Figure 12. Read from Memory Array (READ) Sequence
lect (S) High at a byte boundary of the input data. these devices is 128 bytes). Figure 13. Byte Write (WRITE) Sequence
Figure 14. Page Write (WRITE) Sequence instructions can be started). down (they are non-volatile bits).
Table 7. may cause permanent damage to the de- Table 7. Absolute Maximum Ratings
Table 8. Operating Conditions (M95512-W) Table 9. Operating Conditions (M95512-R) Note: 1. This product is under development. For more information, please contact your nearest ST sales office. Table 10. AC Measurement Conditions Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 15. AC Measurement I/O Waveform Table 11. Capacitance Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 5 MHz.
Table 12. DC Characteristics (M95512-W, Device Grade 6) Note: 1. The information contained in Table 12. is subject to change without previous notice. Table 13. DC Characteristics (M95512-R) Note: 1. The information contained in Table 13. is subject to change without previous notice.
Table 14. AC Characteristics (M95512-W, Device Grade 6) Note: 1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC (max).
- Value guaranteed by characterization, not 100% tested in production.
- The information contained in Table 14. is subject to change without previous notice.
Test conditions specified in Table 10. and Table 8.
Table 15. AC Characteristics (M95512-R) Note: 1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC (max).
- Value guaranteed by characterization, not 100% tested in production.
- The information contained in Table 15. is subject to change without previous notice.
Test conditions specified in Table 10. and Table 9.
Figure 18. Output Timing
Figure 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline Note: Drawing is not to scale. Table 16. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
Figure 20. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline Note: 1. Drawing is not to scale. Table 17. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
Table 18. Ordering Information Scheme(1) Note: 1. Ordering information related to the M95512 identified with the process letter "A". 6 = Industrial temperature range, –40 to 85 °C.
REVISION HISTORY
Table 19. Document Revision History identified with the process letter “A”. Table 1., Product List added. AEC-Q100-002 compliance. Device Grade information clarified. tHHQX , tCHHL and tCHHH corrected to tHHQV , tCLHL and tCLHH , respectively. removed). Document status changed to Preliminary Data.
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