M95512-RCS6TP/AB

M95512-DR STMICROELECTRONICS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 48

Technical content

Datasheet sections

• 1 Description
• 2 Signal description
• 2.1 Serial Data output (Q)
• 2.2 Serial Data input (D)
• 2.3 Serial Clock (C)
• 2.4 Chip Select (S
• 2.5 Hold (HOLD )
• 2.6 Write Protect (W )
• 2.7 V CC supply voltage
• 2.8 V SS ground
• 3 Connecting to the SPI bus
• 3.1 SPI modes
• 4 Operating features
• 4.1 Supply voltage (V CC)
• 4.1.1 Operating supply voltage V CC
• 4.1.2 Device reset
• 4.1.3 Power-up conditions
• 4.1.4 Power-down
• 4.2 Active Power and Standby Power modes
• 4.3 Hold condition
• 4.4 Status register
• 4.5 Data protection and protocol control
• 5 Memory organization
• 6 Instructions
• 6.1 Write Enable (WREN)
• 6.2 Write Disable (WRDI)
• 6.3 Read Status Register (RDSR)
• 6.3.1 WIP bit

Features

■ Compatible with the Serial Peripheral Interface (SPI) bus ■ Memory array – 512 Kb (64 Kbytes) of EEPROM – Page size: 128 bytes ■ Additional Write lockable Page (Identification page) ■ Write – Byte Write within 5 ms – Page Write within 5 ms ■ Write Protect: quarter, half or whole memory array ■ High-speed clock frequency (20 MHz) ■ Single supply voltage: 1.8 V to 5.5 V ■ More than 1 Million Write cycles ■ More than 40-year data retention ■ Enhanced ESD Protection ■ Packages – ECOPACK2® (RoHS compliant and Halogen-free) SO8 (MN) 150 mils width TSSOP8 (DW) 169 mils width UFDFPN8 (MB) 2 × 3 mm (MLP) WLCSP (CS)

M95512-W, M95512-R Contents Doc ID 11124 Rev 13 3/48

Table 19. SO8N – 8 lead plastic small outline, 150 mils body width, package Table 21. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead

1 Description

the document these devices are referred to as M95512, unless otherwise specified. unique identification parameters and/or parameters specific to the production line. Figure 1. Logic diagram can be interrupted using Hold (HOLD).

Signal description M95512-W, M95512-R 8/48 Doc ID 11124 Rev 13

2 Signal description

During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in Table 13 and Table 15). These signals are described next.

2.1 Serial Data output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).

2.2 Serial Data input (D)

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C).

2.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

2.4 Chip Select (S )

When this input signal is high, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.

2.5 Hold (HOLD )

The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low.

M95512-W, M95512-R Signal description Doc ID 11124 Rev 13 9/48

2.6 Write Protect (W )

The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all write instructions.

2.7 V CC supply voltage

VCC is the supply voltage.

2.8 V SS ground

VSS is the reference for the VCC supply voltage.

3 Connecting to the SPI bus

These devices are fully compatible with the SPI protocol. Figure 4. Bus master and memory devices on the SPI bus

1. The Write Protect (W ) and Hold (HOLD) signals should be driven, high or low as appropriate.

Figure 4 shows an example of three memory devices connected to an MCU, on an SPI bus. line at a time, the other devices are high impedance. line in the high impedance state. time, and so, that the tSHCH requirement is met. The typical value of R is 100 k,.

3.1 SPI modes

• CPOL=0, CPHA=0
• CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in Stand-by mode and not transferring data:
• C remains at 0 for (CPOL=0, CPHA=0)
• C remains at 1 for (CPOL=1, CPHA=1)

Figure 5. SPI modes supported

Operating features M95512-W, M95512-R 12/48 Doc ID 11124 Rev 13

4 Operating features

4.1 Supply voltage (V CC)

4.1.1 Operating supply voltage V CC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 8 and Table 10.). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.

4.1.2 Device reset

In order to prevent inadvertent Write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until V CC has reached the POR threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 8 and Table 10). When VCC passes over the POR threshold, the device is reset and in the following state:

• in the Standby Power mode
• deselected (note that when the device is deselected it is necessary to apply a falling edge on Chip Select (S) prior to issuing any new instruction, otherwise the instruction is not executed)
• Status register values: – the Write Enable Latch (WEL) bit is reset to 0 – the Write In Progress (WIP) bit is reset to 0 – the SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits). When V CC passes over the POR threshold, the device is reset and enters the Standby Power mode, however, the device must not be accessed until VCC reaches a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range defined in Table 8 and Table 10.

4.1.3 Power-up conditions

When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see Figure 4). In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge sensitive as well as level sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S ). This ensures that Chip Select (S) must have been high, prior to going low to start the first operation. The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Table 8 and Table 10 and the rise time must not vary faster than 1 V/µs.

4.1.4 Power-down

• deselected (Chip Select (S) should be allowed to follow the voltage applied on VCC)
• in Standby Power mode (that is there should not be any internal write cycle in progress).

4.2 Active Power and Standby Power modes

device consumes ICC, as specified in Table 15.

4.3 Hold condition

resetting the clocking sequence. Input (D) and Serial Clock (C) are Don’t Care. To enter the Hold condition, the device must be selected, with Chip Select (S) low. Normally, the device is kept selected, for the whole duration of the Hold condition. Serial Clock (C) already being low (as shown in Figure 6). Serial Clock (C) already being low. with Serial Clock (C) being low. Figure 6. Hold condition activation

4.4 Status register

4.5 Data protection and protocol control

within applications that could experience problems if memory bytes are corrupted.

• Write and Write Status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.
• All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: –P o w e r - u p – Write Disable (WRDI) instruction completion – Write Status Register (WRSR) instruction completion – Write (WRITE) instruction completion
• The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be configured as read-only.
• The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the Status Register. For any instruction to be accepted, and executed, Chip Select (S) must be driven high after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C). Two points need to be noted in the previous sentence:
• The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions).
• The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus transaction for some other device on the SPI bus.

Table 2. Write-protected block size

5 Memory organization

The memory is organized as shown in Figure 7. Figure 7. Block diagram

1 Page

6 Instructions

Each instruction starts with a single-byte code, as summarized in Table 3. Table 3. M95512-W and M95512-R instruction set Table 4. M95512-DR instruction set

1. Address bit A10 must be 0, all other address bits are Don't Care.
2. Address bit A10 must be 1, all other address bits are Don't Care.

6.1 Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. Figure 8. Write Enable (WREN) sequence

6.2 Write Disable (WRDI)

and the bits of the instruction byte are shifted in, on Serial Data Input (D).

• Power-up
• WRDI instruction execution
• WRSR instruction completion
• WRITE instruction completion.

Figure 9. Write Disable (WRDI) sequence

6.3 Read Status Register (RDSR)

to read the Status Register continuously, as shown in Figure 10.

6.3.1 WIP bit

6.3.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. Latch is reset and no Write or Write Status Register instruction is accepted.

6.3.3 BP1, BP0 bits

Hardware Protected mode has not been set.

6.3.4 SRWD bit

Write Status Register (WRSR) instruction is no longer accepted for execution. Table 5. Status register format

Figure 10. Read Status Register (RDSR) sequence

6.4 Write Status Register (WRSR)

(C). Otherwise, the Write Status Register (WRSR) instruction is not properly executed. also reset when the Write cycle tW is complete.

• The Block Protect (BP1, BP0) bits define the size of the area to be treated as read-only, as defined in Table 6.
• The SRWD bit (Status Register Write Disable bit), depending on the signal applied on the Write Protect pin (W), allows the user to set or reset the write protection mode of the Status Register. When the Status Register is in the Write-protected mode, the Write Status Register (WRSR) instruction is not executed. The contents of the SRWD and BP1, BP0 bits are updated upon completion of the WRSR instruction (after t W). The Write Status Register (WRSR) instruction has no effect on Status Register bits b6, b5, b4, b1, b0. They are always read as 0.

Figure 11. Write Status Register (WRSR) sequence

The protection features of the device are summarized in Table 6. Write Protect (W) input pin.

• If Write Protect (W) is driven high, it is possible to write to the Status Register (provided that the WEL bit has previously been set by a WREN instruction.
• If Write Protect (W) is driven low, it is not possible to write to the Status Register even if the WEL bit has previously been set by a WREN instruction (attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software-protected (SPM) by the Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected against data modification. Regardless of the order of the two events, the Hardware-protected mode (HPM) can be entered either:
• by setting the SRWD bit after driving the Write Protect (W) input pin low
• or by driving the Write Protect (W) input pin low after setting the SRWD bit Once entered, the Hardware-protected mode (HPM) can only be exited by pulling Write Protect (W) high. If Write Protect (W) is permanently tied high, the Hardware-protected mode (HPM) can never be activated, and only the Software-protected mode (SPM) using the Block Protect (BP1, BP0) bits in the Status Register, can be used.

Table 6. Protection modes

1. As defined by the values in the Block Protect ( BP1, BP0) bits of the Status Register, as shown in Table 2.

6.5 Read from Memory Array (READ)

that address is shifted out, on Serial Data Output (Q). incremented, and the byte of data at the new address is shifted out. Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. Figure 12. Read from Memory Array (READ) sequence

6.6 Write to Memory Array (WRITE)

in, on Serial Data Input (D). towards the end of the same page, can be written in a single internal write cycle.

• if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before)
• if a Write cycle is already in progress
• if the device has not been deselected, by Chip Select (S) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in)
• if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits. Note: The self-timed write cycle t W is internally executed as a sequence of two consecutive events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as “1”.

Figure 13. Byte Write (WRITE) sequence

Figure 14. Page Write (WRITE) sequence

6.7 Read Identification Page (available only in M95512-DR

permanently locked in Read-only mode. Reading this page is achieved with the Read Identification Page instruction (see Table 4). The instruction is not accepted, and is not executed, if a write cycle is currently in progress. Figure 15. Read Identification Page sequence

6.8 Write Identification Page (available only in M95512-DR

Don't Care, the [A6:A0] address bits define the byte address inside the identification page. has been latched in, indicating that the instruction is being used to write a single byte. are overwritten with the incoming data. (The page size of these devices is 128 bytes).

• if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a Write Enable instruction)
• if Status register bits (BP1, BP0) = (1, 1)
• if a write cycle is already in progress
• if the device has not been deselected, by Chip Select (S) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that was latched in)
• if the Identification page is locked by the Lock Status bit

Figure 16. Write Identification Page sequence

6.9 Read Lock Status (available only in M95512-DR devices)

in on Serial Data input (D). Address bit A10 must be 1, all other address bits are Don't Care. The instruction sequence is shown in Figure 17. Figure 17. Read Lock Status sequence

6.10 Lock ID (available on ly in M95512-DR devices)

Care. The data byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care. the Lock ID instruction is not executed.

• if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a Write Enable instruction)
• if Status register bits (BP1,BP0) = (1,1)
• if a write cycle is already in progress
• if the device has not been deselected, by Chip Select (S) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that was latched in)
• if the Identification page is locked by the Lock Status bit

Figure 18. Lock ID sequence

M95512-W, M95512-R ECC (error correction code) and write cycling Doc ID 11124 Rev 13 29/48

7 ECC (error correction code) and write cycling

The M95512-W, M95512-R and M95512-DR devices offer an ECC (error correction code) logic which compares each 4-byte word with its associated 6 EEPROM bits of ECC. As a result, if a single bit out of 4 bytes of data happens to be erroneous during a Read operation, the ECC detects it and replaces it by the correct value. The read reliability is therefore much improved by the use of this feature. Note however that even if a single byte has to be written, 4 bytes are internally modified (plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes making up the word. It is therefore recommended to write by words of 4 bytes in order to benefit from the larger amount of Write cycles. The M95512-W, M95512-R and M95512-DR devices are qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device by multiples of 4-byte packets.

8 Power-up and delivery state

8.1 Power-up state

After power-up, the device is in the following state:

• Standby Power mode
• Deselected (after Power-up, a falling edge is required on Chip Select (S) before any instructions can be started).
• Not in the Hold Condition
• Write Enable Latch (WEL) is reset to 0
• Write In Progress (WIP) is reset to 0 The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits).

8.2 Initial delivery state

The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.

9 Maximum rating

Table 7. Absolute maximum ratings

1. Compliant with JEDEC Std J-STD- 020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®

10 DC and AC parameters

match the measurement conditions when relying on the quoted parameters. Figure 19. AC measurement I/O waveform Table 8. Operating conditions (M95512-W device grade 6) Table 9. Operating conditions (M95512-W device grade 3) Table 10. Operating conditions (M95512-R and M95512-DR) Table 11. AC measurement conditions

Table 12. Capacitance (1) Table 13. DC characteristics (current (1) M95512-W products)

1. Current products are identified by AB process letters AB.
2. Characterized value, not tested in production.

Table 14. DC characteristics (new (1) M95512-W products)

1. New products are identified by process letter K.
2. Characterized value, not tested in production.

Table 15. DC characteristics (current and new M95512-R and M95512-DR products)

1. Current products are identif ied by process letters AB.
2. New products are identified by process letter K.
3. Characterized value, not tested in production.

Table 16. AC characteristics (current (1) M95512-W products)

1. Current products are identified by process letters AB.
2. t CH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
3. Value guaranteed by characterizati on, not 100% tested in production.

Table 17. AC characteristics (New (1) M95512-W products)

1. New products are identified by process letter K.
2. t CH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
3. Value guaranteed by characterization, not 100% tested in production.

Table 18. AC characteristics (current and new M95512-R and M95512-DR products)

1. Current products are identifi ed by process letters “AB”.
2. New products are identified by process letter K. For these new products, the test flow guarantees the AC parameter values
3. t CH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
4. Value guaranteed by characterization, not 100% tested in production.

Figure 22. Serial output timing

specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 23. SO8N – 8 lead plastic small outli ne, 150 mils body width, package outline

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 24. TSSOP8 – 8 lead thin shrink small outline, package outline

1. The central pad (area E2 by D2 in the above illust ration) is internally pulled to VSS. It must not be

connected to any other voltage or signal line on the PCB, for example during the soldering process. Table 20. TSSOP8 – 8 lead thin shrink small outline, package mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 25. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead

1. The central pad (the area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be

connected to any other voltage or signal line on the PCB, for example during the soldering process.

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 26. WLCSP-R – 8-bump wafer-length chip-scale package outline Table 22. WLCSP-R – 8-bump wafer-length chip-scale package mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Measured at the maximum bump diam eter parallel to primary datum Z.

12 Part numbering

Table 23. Ordering information scheme 6 = Industrial temperature range, –40 to 85 °C.

1. ST strongly recommends the use of the automotive grade devices for use in an automotive environment.

nearest ST sales office for a copy.

of this device, please contact your nearest ST sales office.

1. The process letters only appear in the product ordering codes of device grade 3 devices. For other

devices, it is only given here as an indication of how to differentiate current from new products. To identify current from new devices, please contact your nearest ST sales office. Table 24. Available M95512 products (package, voltage range, temperature grade) Table 25. Available M95512-DR products (package, voltage range, temperature

Table 26. Document revision history the new device identified with the process letter “A”. (related tables removed). Document status changed to Preliminary Data. products). Document status changed to Datasheet.

Document reformatted. Packages are ECOPACK® compliant. Reset paragraphs replaced by Section 4.1: Supply voltage (VCC). Section 7: ECC (error correction code) and write cycling added. Note modified below Table 12: Capacitance. CL modified in and Table 11: AC measurement conditions. (current and new M95512-R and M95512-DR products). (current and new M95512-R and M95512-DR products) modified. tSHQZ end timing line moved back in Figure 22: Serial output timing. SO8N package specifications updated (see Figure 23 and Table 19). cycles (corrected on cover page). range), see Table 8 on page 31). Section 4.1: Supply voltage (VCC) on page 12 updated. Write to Memory Array (WRITE) on page 23 clarified. temperature grade) added. Small text changes. products (package, voltage range, temperature grade)). 20 MHz added (preliminary data). UFDFPN8 package added (see Section 11: Package mechanical data). Table 26. Document revision history (continued)

VESD modified in Table 7: Absolute maximum ratings. Data related to new products are no longer preliminary.