M95320_09 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 44
Technical content
Datasheet sections
- 1 Description
- 2 Signal description
- 2.1 Serial Data output (Q)
- 2.2 Serial Data input (D)
- 2.3 Serial Clock (C)
- 2.4 Chip Select (S
- 2.5 Hold (HOLD )
- 2.6 Write Protect (W )
- 2.7 V SS ground
- 2.8 V CC supply voltage
- 3 Connecting to the SPI bus
- 3.1 SPI modes
- 4 Operating features
- 4.1 Supply voltage (V CC)
- 4.1.1 Operating supply voltage V CC
- 4.1.2 Device reset
- 4.1.3 Power-up conditions
- 4.1.4 Power-down
- 4.2 Active Power and Standby Power modes
- 4.2.1 Hold condition
- 4.3 Status Register
- 4.4 Data protection and protocol control
- 5 Memory organization
- 6 Instructions
- 6.1 Write Enable (WREN)
- 6.2 Write Disable (WRDI)
- 6.3 Read Status Register (RDSR)
- 6.3.1 WIP bit
Features
■ Compatible with SPI bus serial interface (positive clock SPI modes) ■ Single supply voltage: – 4.5 to 5.5 V for M95320 – 2.5 to 5.5 V for M95320-W – 1.8 to 5.5 V for M95320-R ■ 10 MHz, 5 MHz or 2 MHz clock rates ■ 5 ms write time ■ Status Register ■ Hardware protection of the Status Register ■ Byte and Page Write (up to 32 bytes) ■ Self-timed programming cycle ■ Adjustable size read-only EEPROM area ■ Enhanced ESD protection ■ More than 1 million Write cycles ■ More than 40-year data retention ■ Packages –E C O P A C K 2 ® (RoHS-compliant and Halogen-free) SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width UFDFPN8 (MB) 2 x 3 mm
M95320, M95320-W, M95320-R Contents Doc ID 5711 Rev 12 3/44
Table 23. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
1 Description
are 32 Kbit devices organized as 4096 × 8 bits. are C, D and Q, as shown in Table 1 and Figure 1. can be interrupted using Hold (HOLD). Figure 1. Logic diagram Figure 2. 8-pin package connections
- See Package mechanical data section for package dimensions and how to identify pin-1.
Table 1. Signal names
Signal description M95320, M95320-W, M95320-R 8/44 Doc ID 5711 Rev 12
2 Signal description
During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in Table 13 to Table 16). These signals are described next.
2.1 Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
2.2 Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C).
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S )
When this input signal is high, the device is deselected and Serial Data output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
2.5 Hold (HOLD )
The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
M95320, M95320-W, M95320-R Signal description Doc ID 5711 Rev 12 9/44
2.6 Write Protect (W )
The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all write operations.
2.7 V SS ground
VSS is the reference for the VCC supply voltage.
2.8 V CC supply voltage
Refer to Section 4.1: Supply voltage (VCC) on page 12.
3 Connecting to the SPI bus
These devices are fully compatible with the SPI protocol. others being high impedance. Figure 3. Bus master and memory devices on the SPI bus
- The Write Protect (W ) and Hold (HOLD) signals should be driven, high or low as appropriate.
bus master leaves the S line in the high impedance state. same time, and so, that the tSHCH requirement is met. The typical value of R is 100 k.
3.1 SPI modes
- CPOL=0, CPHA=0
- CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in Stand-by mode and not transferring data:
- C remains at 0 for (CPOL=0, CPHA=0)
- C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. SPI modes supported
Operating features M95320, M95320-W, M95320-R 12/44 Doc ID 5711 Rev 12
4 Operating features
4.1 Supply voltage (V CC)
4.1.1 Operating supply voltage V CC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 8, Table 9 and Table 10). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
4.1.2 Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until V CC reaches the internal threshold voltage (this threshold is defined in DC characteristics tables 13, 14, 15 and 16 as VRES). When VCC passes over the POR threshold, the device is reset and in the following state:
- in the Standby Power mode
- deselected (note that, to be executed, an instruction must be preceded by a falling edge on Chip Select (S))
- Status register values: – the Write Enable Latch (WEL) bit is reset to 0 – the Write In Progress (WIP) bit is reset to 0 – the SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits). When V CC passes over the POR threshold, the device is reset and enters the Standby Power mode. The device must not be accessed until VCC reaches a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range defined in Table 8, Table 9 and Table 10.
4.1.3 Power-up conditions
When the power supply is turned on, VCC continuously rises from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see Figure 3). In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge- sensitive as well as level-sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S ). This ensures that Chip Select (S) must have been high, prior to going low to start the first operation. The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Table 8, Table 9 and Table 10 and the rise time must not vary faster than 1 V/µs.
4.1.4 Power-down
- deselected (Chip Select S should be allowed to follow the voltage applied on VCC)
- in Standby Power mode (there should not be any internal write cycle in progress).
4.2 Active Power and Standby Power modes
device consumes ICC, as specified in Table 13 to Table 16.
4.2.1 Hold condition
resetting the clocking sequence. input (D) and Serial Clock (C) are Don’t Care. To enter the Hold condition, the device must be selected, with Chip Select (S) low. Normally, the device is kept selected, for the whole duration of the Hold condition. Serial Clock (C) already being low (as shown in Figure 5). Serial Clock (C) already being low. with Serial Clock (C) being low. Figure 5. Hold condition activation
4.3 Status Register
detailed description of the Status Register bits.
4.4 Data protection and protocol control
within applications that could experience problems if memory bytes are corrupted.
- Write and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.
- All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: –P o w e r - u p – Write Disable (WRDI) instruction completion – Write Status Register (WRSR) instruction completion – Write (WRITE) instruction completion
- The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be configured as read-only.
- The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits of the Status Register. For any instruction to be accepted, and executed, Chip Select (S) must be driven high after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C). Two points need to be noted in the previous sentence:
- The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions).
- The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus transaction for some other device on the SPI bus.
Table 2. Write-protected block size
5 Memory organization
The memory is organized as shown in Figure 6. Figure 6. Block diagram
1 Page
6 Instructions
Each instruction starts with a single-byte code, as summarized in Table 3. automatically deselects itself.
6.1 Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. Figure 7. Write Enable (WREN) sequence Table 3. Instruction set
6.2 Write Disable (WRDI)
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
- Power-up
- WRDI instruction execution
- WRSR instruction completion
- WRITE instruction completion.
Figure 8. Write Disable (WRDI) sequence
6.3 Read Status Register (RDSR)
to read the Status Register continuously, as shown in Figure 9.
6.3.1 WIP bit
6.3.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3 BP1, BP0 bits
Hardware Protected mode has not been set.
6.3.4 SRWD bit
Write Status Register (WRSR) instruction is no longer accepted for execution. Table 4. Status Register format
Figure 9. Read Status Register (RDSR) sequence
6.4 Write Status Register (WRSR)
Table 20). The instruction sequence is shown in Figure 10. reset at the end of the write cycle tW.
- The Block protect (BP1, BP0) bits define the size of the area that is to be treated as read only, as defined in Table 2.
- The SRWD bit (Status register write disable bit), in accordance with the signal read on the Write protect pin (W), allows the user to set or reset the write protection mode of the Status Register itself, as shown in Table 5. When in the Write-protected mode, the Write Status Register (WRSR) instruction is not executed. The contents of the SRWD and BP1, BP0 bits are updated after the completion of the WRSR instruction, including the tW write cycle. The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1 and b0 bits in the Status Register. Bits b6, b5, b4 are always read as 0. C D S 21 3456789 1 0 1 1 1 2 1 3 1 4 1 5 Instruction AI02031E Q 7 6543210 Status Register Out High Impedance MSB 7 6543210 Status Register Out MSB
The protection features of the device are summarized in Table 5.
- If Write Protect (W) is driven high, it is possible to write to the Status Register provided that the Write enable latch (WEL) bit has previously been set by a Write Enable (WREN) instruction.
- If Write Protect (W) is driven low, it is not possible to write to the Status Register even if the Write Enable latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software-protected (SPM) by the Block protect (BP1, BP0) bits in the Status Register, are also hardware-protected against data modification. Regardless of the order of the two events, the Hardware-protected mode (HPM) can be entered:
- by setting the Status register write disable (SRWD) bit after driving Write Protect (W) low
- or by driving Write Protect (W) low after setting the Status register write disable (SRWD) bit. The only way to exit the Hardware-protected mode (HPM) once entered is to pull Write Protect (W) high. If Write Protect (W) is permanently tied high, the Hardware-protected mode (HPM) can never be activated, and only the Software-protected mode (SPM), using the Block protect (BP1, BP0) bits in the Status Register, can be used.
Table 5. Protection modes
10 Software
- As defined by the values in the Block Protect (BP1 , BP0) bits of the Status Register, as shown in Table 2.
Table 6. Address range bits (1)
- b15 to b12 are Don’t Care.
Figure 10. Write Status Register (WRSR) sequence
6.5 Read from Memory Array (READ)
that address is shifted out, on Serial Data Output (Q). incremented, and the byte of data at the new address is shifted out. Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. Figure 11. Read from Memory Array (READ) sequence
- Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
6.6 Write to Memory Array (WRITE)
in, on Serial Data Input (D). towards the end of the same page, can be written in a single internal Write cycle.
- if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before)
- if a write cycle is already in progress
- if the device has not been deselected, by Chip Select (S) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in)
- if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits. Note: The self-timed write cycle t W is internally executed as a sequence of two consecutive events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as “1”.
Figure 12. Byte Write (WRITE) sequence
- Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
Figure 13. Page Write (WRITE) sequence
- Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
Power-up and delivery state M95320, M95320-W, M95320-R 24/44 Doc ID 5711 Rev 12
7 Power-up and delivery state
7.1 Power-up state
After Power-up, the device is in the following state:
- Standby Power mode
- deselected (after power-up, a falling edge is required on Chip Select (S) before any instructions can be started).
- not in the Hold condition
- the Write Enable Latch (WEL) is reset to 0
- Write In Progress (WIP) is reset to 0 The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits).
7.2 Initial delivery state
The device is delivered with the memory array set to all 1s (each byte = FFh). The Status register write disable (SRWD) and Block protect (BP1 and BP0) bits are initialized to 0.
8 Maximum rating
Table 7. Absolute maximum ratings
- Compliant with JEDEC Std J-STD-020C (for smal l body, Sn-Pb or Pb assembly), the ST ECOPACK®
9 DC and AC parameters
match the measurement conditions when relying on the quoted parameters. Table 8. Operating conditions (M95320) Table 9. Operating conditions (M95320-W) Table 10. Operating conditions (M95320-R)
- This product is under development. For more inform ation, please contact your nearest ST sales office.
Table 11. AC measurement conditions (1)
- Output Hi-Z is defined as the point where data out is no longer driven.
Figure 14. AC measurement I/O waveform Table 12. Capacitance (1)
- Sampled only, not 100% tested.
Table 13. DC characteristics (M95320, device grade 3)
- For all 5 V range devices, the device meets the out put requirements for both TTL and CMOS standards.
- Characterized only, not 100% tested.
Table 14. DC characteristics (M95320-W, device grade 6)
- Characterized only, not 100% tested.
Table 15. DC characteristics (M95320-W, device grade 3)
- Characterized only, not 100% tested.
Table 16. DC characteristics (M95320-R)
0.8 VCC V
- Characterized only, not 100% tested.
Table 17. AC characteristics (M95320, device grade 3)
- These timings are offered with grade3 dev ices referenced with “/PC” process letters only (see the last digits in the Part
- t CH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
- Value guaranteed by characterization, not 100% tested in production.
- t CLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be
equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV+tSU.
Table 18. AC characteristics (M95320-W, device grade 6)
- t CH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
- Value guaranteed by characterizati on, not 100% tested in production.
- t CLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0
Table 19. AC characteristics (M95320-W, device grade 3)
- These timings are offered with grade3 dev ices referenced with “/PC” process letters only (see the last digits in the Part
- t CH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
- Value guaranteed by characterization, not 100% tested in production.
- t CLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be
equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV+tSU.
Table 20. AC characteristics (M95320-R)
- If the application uses the M95320-R device with 2.5 V VCC 5.5 V and –40 °C TA +85 °C, please
refer to Table 18: AC characteristics (M95320-W, device grade 6) instead of the above table.
- t CH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
- Value guaranteed by characterizati on, not 100% tested in production.
Figure 17. Serial output timing
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 18. SO8N – 8-lead plastic small outlin e, 150 mils body width, package outline Table 21. SO8N – 8-lead plastic small outline, 150 mils body width, package
- Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 19. TSSOP8 – 8-lead thin shrink small outline, package outline Table 22. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
- Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 20. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
- The central pad (the area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be
connected to any other voltage or signal line on the PCB, for example during the soldering process.
- Values in inches are converted from mm and rounded to 4 decimal digits.
- Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
11 Part numbering
of this device, please contact your nearest ST sales office. Table 24. Ordering information scheme
- All packages are ECOPACK2 ® (RoHS compliant and Halogen-free).
6 = Industrial temperature range, –40 to 85 °C.
- ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
nearest ST sales office for a copy.
- The process letter only concerns Grade-3 devices.
Table 25. Available M95320x products (package, voltage range, temperature grade)
Table 26. Document revision history tCLCH, tCHCL, tDLDH and tDHDL changed to 50ns for the -V range. “-V” Voltage range changed to “2.7V to 3.6V” throughout. Maximum lead soldering time and temperature conditions updated. Instruction sequence illustrations updated. “Bus Master and Memory Devices on the SPI bus” illustration updated. 18-Dec-2001 2.0 Document reformatted using the new template. No parameters changed. related characteristics added. Description of Power On Reset: VCC Lock-Out Write Protect updated. process. tHHQX corrected to tHHQV. Figure 16: Hold timing updated.
Document converted to new ST template. Packages are ECOPACK® compliant. PDIP package removed. SO8N package specifications updated (see Table 21 and Figure 18). identification letter Table removed. Table 14. ICC updated in Table 15. Data in Table 16 is no longer tCH updated in Table 18. Table 21: AC characteristics (M95640-R) added. Timing line of tSHQZ modified in Figure 17: Serial output timing. removed. Note 2 removed from Figure 2. Note 2 removed below Figure 3 and explanatory paragraph added. device grade 6 TA temperature range. characteristics (M95320-W, device grade 6) modified accordingly). temperature grade): /PB process letter added, /P process letter removed. Table 25 and Table 27 added. Small text changes. package mechanical data updated. decimal digits in Section 10: Package mechanical data. Section 2.7: VSS ground added. VIL and VIH modified in Table 16: DC characteristics (M95320-R). Table 21: AC characteristics (M95640-R). Small text changes. Table 26. Document revision history (continued)
Section 4.1: Supply voltage (VCC) updated.
10 MHz frequencies added to Table 17: AC characteristics (M95320,
Section 4.1: Supply voltage (VCC) updated. Table 16: DC characteristics (M95320-R) modified. Note added to Section 6.6: Write to Memory Array (WRITE). Section 7.2: Initial delivery state specified. DC characteristics (M95320, device grade 3). VRES parameter added to DC characteristics tables 13, 14, 15 and 16. Note added to tCLQV in AC characteristics tables 17, 18, 19 and 21. Process letter modified in Table 24: Ordering information scheme. 64 Kbit densities removed from datasheet. Ordering information scheme. IOL and IOH added to Table 7: Absolute maximum ratings. pitch dual flat no lead, package outline.