M95640-S STMICROELECTRONICS | Alldatasheet

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Table 1. Product List Figure 1. Packages

and Q, as shown in Table 3. and Figure 2.. interrupted using Hold (HOLD). Table 2. How to Identify Previous, Current and New Products by the Process Identification Letter Note: 1. For further information, please ask your ST Sales Office for Process Change Notices. Figure 2. Logic Diagram Figure 3. 8 Pin Package Connections mensions and how to identify pin-1. Table 3. Signal Names

M95640, M95320 SIGNAL DESCRIPTION During all operations, VCC must be held stable and within the specified valid range: VCC (min) to VCC (max). All of the input and output signals must be held High or Low (according to voltages of VIH, VOH , VIL or VOL , as specified in Table 16. to Table 20.). These signals are described next. Serial Data Output (Q).This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D).This input signal is used to transfer data serially into the device. It receives in- structions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C).This input signal provides the timing of the serial interface. Instructions, address- es, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select (S ).When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Stand- by Power mode. Driving Chip Select (S) Low se- lects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. Hold (HOLD).The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be se- lected, with Chip Select (S) driven Low. Write Protect (W).The main purpose of this in- put signal is to freeze the size of the area of mem- ory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either High or Low, and must be stable during all write operations.

Figure 5. SPI Modes Supported

a suitable pull-up resistor. reached the Power On Reset threshold voltage. voltage defined in Tables 10, 11, 12 and 13. the internal write cycle (tW ). At Power-down, the device must be deselected. and Serial Clock (C) are Don’t Care. selected, with Chip Select (S) Low. cesses that had been in progress. Clock (C) already being Low. Figure 6. also shows what happens if the rising

some other device on the SPI bus. Table 5. Write-Protected Block Size

The memory is organized as shown in Figure 7.. Figure 7. Block Diagram

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Table 6. Instruction Set

Write or Write Status Register cycle is in progress. bit before sending a new instruction to the device. tinuously, as shown in Figure 10.. cates the status of the internal Write Enable Latch. be software protected against Write instructions. Figure 10. Read Status Register (RDSR) Sequence

the Write Enable Latch (WEL). The instruction sequence is shown in Figure 11.. Register. b6, b5 and b4 are always read as 0. pleted, the Write Enable Latch (WEL) is reset. ware Protected Mode (HPM) is entered. Table 7. Protection Modes Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 5..

the Status Register, can be used. Table 8. Address Range Bits Note: b15 to b13 are Don’t Care on the 64 Kbit devices. b15 to b12 are Don’t Care on the 32 Kbit devices. Figure 11. Write Status Register (WRSR) Sequence

64 Kbit

(S) signal can occur at any time during the cycle. ed, if a Write cycle is currently in progress. Figure 12. Read from Memory Array (READ) Sequence Note: Depending on the memory size, as shown in Table 8., the most significant address bits are Don’t Care.

lect (S) High at a byte boundary of the input data. in Progress (WIP) bit is reset to 0. Figure 13. Byte Write (WRITE) Sequence Note: Depending on the memory size, as shown in Table 8., the most significant address bits are Don’t Care.

Figure 14. Page Write (WRITE) Sequence Note: Depending on the memory size, as shown in Table 8., the most significant address bits are Don’t Care.

M95640, M95320 POWER-UP AND DELIVERY STATE Power-up State After Power-up, the device is in the following state: – Standby Power mode – deselected (after Power-up, a falling edge is required on Chip Select (S ) before any instructions can be started). – not in the Hold Condition – the Write Enable Latch (WEL) is reset to 0 – Write In Progress (WIP) is reset to 0 The SRWD, BP1 and BP0 bits of the Status Reg- ister are unchanged from the previous power- down (they are non-volatile bits). INITIAL DELIVERY STATE The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.

Table 9. may cause permanent damage to the de- Table 9. Absolute Maximum Ratings

Table 10. Operating Conditions (M95320 and M95640) Table 11. Operating Conditions (M95320-W and M95640-W) Table 12. Operating Conditions (M95320-R and M95640-R) Note: 1. This product is under development. For more information, please contact your nearest ST sales office. Table 13. Operating Conditions (M95320-S and M95640-S) Note: 1. This product is under development. For more information, please contact your nearest ST sales office. Table 14. AC Measurement Conditions Note: Output Hi-Z is defined as the point where data out is no longer driven.

Figure 15. AC Measurement I/O Waveform Table 15. Capacitance Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 5MHz. Table 16. DC Characteristics (M95320 and M95640, Device Grade 6) Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.

  1. Previous product version is identified by Process Identification letter ‘S’.
  2. Current product version is identified by Process Identification letter ‘V’’.
  3. New product version is identified by Process Identification letter ‘P’.

Table 17. DC Characteristics (M95320 and M95640, Device Grade 3) Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.

  1. Previous product version is identified by Process Identification letter ‘S’.
  2. Current product version is identified by Process Identification letters ‘B’.
  3. New product version is identified by Process Identification letters ‘P’.

Table 18. DC Characteristics (M95320-W and M95640-W, Device Grade 6) Note: 1. Previous product version is identified by Process Identification letter ‘S’.

  1. Current product version is identified by Process Identification letter ‘V’’.
  2. New product version is identified by Process Identification letter ‘P’.

Table 19. DC Characteristics (M95320-W and M95640-W, Device Grade 3) Note: 1. Current product version is identified by Process Identification letter ‘B’.

  1. New product version is identified by Process Identification letter ‘P’.

Table 20. DC Characteristics (M95320-R and M95640-R) Note: 1. This product is under qualification. For more information, please contact your nearest ST sales office. Table 21. DC Characteristics (M95320-S and M95640-S) Note: 1. This product is under qualification. For more information, please contact your nearest ST sales office.

Table 22. AC Characteristics (M95320 and M95640, Device Grade 6) Note: 1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC (max).

  1. Value guaranteed by characterization, not 100% tested in production.
  2. Previous product version is identified by Process Identification letter ‘S’.
  3. Current product version is identified by Process Identification letter ‘V’’.
  4. New product version is identified by Process Identification letter ‘P’.

Test conditions specified in Table 14. and Table 10.

Table 23. AC Characteristics (M95320 and M95640, Device Grade 3) Note: 1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC (max).

  1. Value guaranteed by characterization, not 100% tested in production.
  2. Previous product version is identified by Process Identification letter ‘S’.
  3. Current product version is identified by Process Identification letter ‘B’.
  4. New product version is identified by Process Identification letter ‘P’.

Test conditions specified in Table 14. and Table 10.

Table 24. AC Characteristics (M95320-W and M95640-W, Device Grade 6) Note: 1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC (max).

  1. Value guaranteed by characterization, not 100% tested in production.
  2. Previous product version is identified by Process Identification letter ‘S’.
  3. Current product version is identified by Process Identification letter ‘V’’.
  4. New product version is identified by Process Identification letter ‘P’.

Test conditions specified in Table 14. and Table 11.

Table 25. AC Characteristics (M95320-W and M95640-W, Device Grade 3) Note: 1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC (max).

  1. Value guaranteed by characterization, not 100% tested in production.
  2. Current product version is identified by Process Identification letter ‘V’’.
  3. New product version is identified by Process Identification letter ‘P’.

Test conditions specified in Table 14. and Table 11.

Table 26. AC Characteristics (M95320-R and M95640-R) Note: 1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC (max).

  1. Value guaranteed by characterization, not 100% tested in production.
  2. Preliminary data: this product is under qualification. For more information, please contact your nearest ST sales office.
  3. New product version is identified by Process Identification letter ‘P’.

Test conditions specified in Table 14. and Table 12.

Table 27. AC Characteristics (M95320-S Device Grade 3) Note: 1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC (max).

  1. Value guaranteed by characterization, not 100% tested in production.
  2. Preliminary data: this product is under qualification. For more information, please contact your nearest ST sales office.
  3. New product version is identified by Process Identification letter ‘P’.

Test conditions specified in Table 14. and Table 12.

Figure 18. Output Timing

Figure 19. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline Note: Drawing is not to scale. Table 28. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data

Figure 20. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline Note: Drawing is not to scale. Table 29. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data

Figure 21. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline Note: Drawing is not to scale. Table 30. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data

Figure 22. MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, Package Outline Note: Drawing is not to scale. Table 31. MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, Package Mechanical Data

Table 32. Ordering Information Scheme tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.

  1. Devices bearing the process identification letter “B” or “V” in the package marking (on the top side of the package, on the right side),

device identification, please contact your nearest ST sales office, and ask for the Product Change Notice. please contact your nearest ST Sales Office. 6 = Industrial temperature range, –40 to 85 °C.

M95640, M95320

REVISION HISTORY

Table 33. Document Revision History Test condition added ILI and ILO , and specification of tDLDH and tDHDL removed. tCLCH , tCHCL , tDLDH and tDHDL changed to 50ns for the -V range. “-V” Voltage range changed to “2.7V to 3.6V” throughout. Maximum lead soldering time and temperature conditions updated. Instruction sequence illustrations updated. “Bus Master and Memory Devices on the SPI bus” illustration updated. 18-Dec-2001 2.0 Document reformatted using the new template. No parameters changed. 08-Feb-2002 2.1 Announcement made of planned upgrade to 10MHz clock for the 5V, –40 to 85°C, range. 20MHz Clock rate added.TSSOP14 package removed and MLP8 package added. Description of Power On Reset: VCC Lock-Out Write Protect updated. Figure 17., Hold Timing updated.

M95640, M95320 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America