M95320 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Summary description
- 2 Signal description
- 2.0.1 Serial Data Output (Q)
- 2.0.2 Serial Data Input (D)
- 2.0.3 Serial Clock (C)
- 2.0.4 Chip Select (S)
- 2.0.5 Hold (HOLD )
- 2.0.6 Write Protect (W)
- 3 Connecting to the SPI bus
- 3.1 SPI modes
- 4 Operating features
- 4.1 Supply voltage (VCC )
- 4.1.1 Operating supply voltage VCC
- 4.1.2 Power-up conditions
- 4.1.3 Internal device Reset
- 4.1.4 Power-down
- 4.2 Active Power and Standby Power modes
- 4.2.1 Hold condition
- 4.3 Status Register
- 4.4 Data protection and protocol control
- 5 Memory organization
- 6 Instructions
- 6.1 Write Enable (WREN)
- 6.2 Write Disable (WRDI)
- 6.3 Read Status Register (RDSR)
- 6.3.1 WIP bit
- 6.3.2 WEL bit
- 6.3.3 BP1, BP0 bits
- 6.3.4 SRWD bit
32 Kbit and 64 Kbit Serial SPI bus EEPROMs
■ Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes) ■ Single Supply Voltage: – 4.5 to 5.5V for M95320 and M95640 – 2.5 to 5.5V for M95320-W and M95320-W – 1.8 to 5.5V for M95320-R and M95640-R ■ 10MHz, 5MHz or 2MHz clock rates ■ 5ms or 10ms Write Time ■ Status Register ■ Hardware Protection of the Status Register ■ Byte and Page Write (up to 32 Bytes) ■ Self-Timed Programming Cycle ■ Adjustable Size Read-Only EEPROM Area ■ Enhanced ESD Protection ■ More than 1 million Write cycles ■ More than 40-Year Data Retention ■ Packages – ECOPACK® (RoHS compliant) SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width MLP8 (MB) 2x3 mm
M95320, M95640, M95320-x, M95640-x Contents
Table 24. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . 38
1 Summary description
high speed SPI-compatible bus. M95640, M95640-W and M95640-R are 64Kbit devices organized as 8192 x 8 bits. are C, D and Q, as shown in Table 1 and Figure 1. can be interrupted using Hold (HOLD). ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 1. Logic diagram Figure 2. 8 pin package connections1. See Package mechanical section for package dimensions and how to identify pin-1.
Table 1. Signal names
Signal description M95320, M95640, M95320-x, M95640-x
2 Signal description
During all operations, VCC must be held stable and within the specified valid range: VCC (min) to VCC (max). All of the input and output signals must be held High or Low (according to voltages of VIH, VOH , VIL or VOL , as specified in Table 13 to Table 17). These signals are described next.
2.0.1 Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
2.0.2 Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C).
2.0.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.0.4 Chip Select (S )
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) Low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
2.0.5 Hold (HOLD )
The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
2.0.6 Write Protect (W )
The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either High or Low, and must be stable during all write operations.
3 Connecting to the SPI bus
These devices are fully compatible with the SPI protocol. others being high impedance. Figure 3. Bus master and memory devices on the SPI bus
- The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
- These pull-up resistors, R, ensure that the memory devices are not selected if the Bus Master leaves the S line in the high-
High at the same time, and so, that the tSHCH requirement is met).
3.1 SPI modes
- CPOL=0, CPHA=0
- CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in Stand-by mode and not transferring data:
- C remains at 0 for (CPOL=0, CPHA=0)
- C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. SPI modes supported
M95320, M95640, M95320-x, M95640-x Operating features
4 Operating features
4.1 Supply voltage (V CC )
4.1.1 Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC (min), VCC (max)] range must be applied (see Table 8.). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10nF to 100nF) close to the VCC /VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW ).
4.1.2 Power-up conditions
When the power supply is turned on, VCC rises from VSS to VCC . During this time, the Chip Select (S) is not allowed to float but must follow the VCC voltage, therefore the S line should be connected to VCC via a suitable pull-up resistor. In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge sensitive as well as level sensitive: after Power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S ). This ensures that Chip Select (S) must have been High, prior to going Low to start the first operation. The VCC rise time must not be faster than 1V/µs.
4.1.3 Internal device Reset
In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up (continuous rise of VCC ), the device will not respond to any instruction until VCC has reached the Power On Reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Tables XX). When V CC has passed the POR threshold, the device is reset and in the following state:
- Standby Power mode
- deselected (at next Power-up, a falling edge is required on Chip Select (S) before any instructions can be started).
- not in the Hold Condition Status Register state:
- the Write Enable Latch (WEL) is reset to 0
- Write In Progress (WIP) is reset to 0. The SRWD, BP1 and BP0 bits of the Status Register are in the same state as when the power was last removed (they are non- volatile bits).
4.1.4 Power-down
responding to any instruction sent to it. follow the voltage applied on VCC .
4.2 Active Power and Standby Power modes
device consumes ICC , as specified in Table 13 to Table 17.
4.2.1 Hold condition
resetting the clocking sequence. Input (D) and Serial Clock (C) are Don’t Care. To enter the Hold condition, the device must be selected, with Chip Select (S) Low. Normally, the device is kept selected, for the whole duration of the Hold condition. Serial Clock (C) already being Low (as shown in Figure 5). Serial Clock (C) already being Low. with Serial Clock (C) being Low. Figure 5. Hold condition activation
4.3 Status Register
detailed description of the Status Register bits.
4.4 Data protection and protocol control
within applications that could experience problems if memory bytes are corrupted.
- Write and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.
- All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: –P o w e r - u p – Write Disable (WRDI) instruction completion – Write Status Register (WRSR) instruction completion – Write (WRITE) instruction completion
- The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read- only. This is the Software Protected Mode (SPM).
- The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits to be protected. This is the Hardware Protected Mode (HPM). For any instruction to be accepted, and executed, Chip Select (S) must be driven High after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C). Two points need to be noted in the previous sentence:
- The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions).
- The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus transaction for some other device on the SPI bus.
Table 2. Write-Protected block size
5 Memory organization
The memory is organized as shown in Figure 6. Figure 6. Block diagram
1 Page
6 Instructions
Each instruction starts with a single-byte code, as summarized in Table 3. automatically deselects itself.
6.1 Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. Figure 7. Write Enable (WREN) sequence Table 3. Instruction set
6.2 Write Disable (WRDI)
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
- Power-up
- WRDI instruction execution
- WRSR instruction completion
- WRITE instruction completion.
Figure 8. Write Disable (WRDI) sequence
6.3 Read Status Register (RDSR)
to read the Status Register continuously, as shown in Figure 9.
6.3.1 WIP bit
6.3.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3 BP1, BP0 bits
Hardware Protected mode has not been set.
6.3.4 SRWD bit
Write Status Register (WRSR) instruction is no longer accepted for execution. Table 4. Status Register format
Figure 9. Read Status Register (RDSR) sequence
6.4 Write Status Register (WRSR)
executed, the device sets the Write Enable Latch (WEL). followed by the instruction code and the data byte on Serial Data Input (D). The instruction sequence is shown in Figure 10. Status Register. b6, b5 and b4 are always read as 0. driven High, the self-timed Write Status Register cycle (whose duration is tW ) is initiated. cycle is completed, the Write Enable Latch (WEL) is reset. only, as defined in Table 4. instruction is not executed once the Hardware Protected Mode (HPM) is entered. completion of the execution of Write Status Register (WRSR) instruction.
The protection features of the device are summarized in Table 2.
- If Write Protect (W) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction.
- If Write Protect (W) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:
- by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) Low
- or by driving Write Protect (W) Low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W) High. If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used.
Table 5. Protection modes
- As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
Figure 10. Write Status Register (WRSR) sequence Table 6. Address range bits(1)
- b15 to b13 are Don’t Care on the 64 Kbit devices.
b15 to b12 are Don’t Care on the 32 Kbit devices.
6.5 Read from Memory Array (READ)
that address is shifted out, on Serial Data Output (Q). incremented, and the byte of data at the new address is shifted out. Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. Figure 11. Read from Memory Array (READ) sequence
- Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
6.6 Write to Memory Array (WRITE)
shifted in, on Serial Data Input (D). the end of which the Write in Progress (WIP) bit is reset to 0. towards the end of the same page, can be written in a single internal Write cycle.
- if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before)
- if a Write cycle is already in progress
- if the device has not been deselected, by Chip Select (S) being driven High, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in)
- if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
Figure 12. Byte Write (WRITE) sequence
- Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
Figure 13. Page Write (WRITE) sequence
- Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
Power-up and delivery state M95320, M95640, M95320-x, M95640-x
7 Power-up and delivery state
7.1 Power-up state
After Power-up, the device is in the following state:
- Standby Power mode
- deselected (after Power-up, a falling edge is required on Chip Select (S) before any instructions can be started).
- not in the Hold Condition
- the Write Enable Latch (WEL) is reset to 0
- Write In Progress (WIP) is reset to 0 The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits).
7.2 Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
8 Maximum rating
Table 7. Absolute maximum ratings
- Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
9 DC and AC parameters
match the measurement conditions when relying on the quoted parameters. Figure 14. AC measurement I/O waveform Table 8. Operating conditions (M95320 and M95640) Table 9. Operating conditions (M95320-W and M95640-W) Table 10. Operating conditions (M95320-R and M95640-R)
- This product is under development. For more information, please contact your nearest ST sales office.
Table 11. AC measurement conditions(1)
- Output Hi-Z is defined as the point where data out is no longer driven.
Table 12. Capacitance(1)
- Sampled only, not 100% tested, at TA=25°C and a frequency of 5MHz.
Table 13. DC characteristics (M95320 and M95640, device grade 6)
- For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
Table 14. DC characteristics (M95320 and M95640, device grade 3)
- For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
Table 15. DC characteristics (M95320-W and M95640-W, device grade 6) Table 16. DC characteristics (M95320-W and M95640-W, device grade 3)
Table 17. DC characteristics (M95320-R and M95640-R)
- This product is under qualification. For more information, please contact your nearest ST sales office.
Table 18. AC characteristics (M95320 and M95640, device grade 6)
- tCH + tCL must never be lower than the shortest possible clock period, 1/fC (max).
- Value guaranteed by characterization, not 100% tested in production.
Table 19. AC characteristics (M95320 and M95640, device grade 3)
- tCH + tCL must never be lower than the shortest possible clock period, 1/fC (max).
- Value guaranteed by characterization, not 100% tested in production.
Table 20. AC characteristics (M95320-W and M95640-W, device grade 6)
- Current product version is identified by Process Identification letter ‘V’’.
- New product version is identified by Process Identification letter ‘P’. Please contact your nearest ST sales
- tCH + tCL must never be lower than the shortest possible clock period, 1/fC (max).
- Value guaranteed by characterization, not 100% tested in production.
Table 21. AC characteristics (M95320-W and M95640-W, device grade 3)
- tCH + tCL must never be lower than the shortest possible clock period, 1/fC (max).
- Value guaranteed by characterization, not 100% tested in production.
Table 22. AC characteristics (M95320-R)
- tCH + tCL must never be lower than the shortest possible clock period, 1/fC (max).
- Value guaranteed by characterization, not 100% tested in production.
Table 23. AC characteristics (M95640-R)
- tCH + tCL must never be lower than the shortest possible clock period, 1/fC (max).
- Value guaranteed by characterization, not 100% tested in production.
Figure 17. Output timing
Figure 18. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package outline Table 24. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package
Figure 19. TSSOP8 – 8 lead Thin Shrink Small Outline, package outline Table 25. TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data
Figure 20. MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, package outline Table 26. MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, package
11 Part numbering
of this device, please contact your nearest ST Sales Office. soldering conditions are also marked on the inner box label. Table 27. Ordering information scheme 6 = Industrial temperature range, –40 to 85 °C.
- ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
nearest ST sales office for a copy.
- The Process letter only concerns Grade-3 devices.
Table 28. Document revision history tCLCH , tCHCL , tDLDH and tDHDL changed to 50ns for the -V range. “-V” Voltage range changed to “2.7V to 3.6V” throughout. Maximum lead soldering time and temperature conditions updated. Instruction sequence illustrations updated. “Bus Master and Memory Devices on the SPI bus” illustration updated. 18-Dec-2001 2.0 Document reformatted using the new template. No parameters changed.