M95256-D-DW6G/A

M95256-DR STMICROELECTRONICS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 48

Technical content

Datasheet sections

• 1 Description
• 2 Memory organization
• 3 Signal description
• 3.1 Serial Data output (Q)
• 3.2 Serial Data input (D)
• 3.3 Serial Clock (C)
• 3.4 Chip Select (S )
• 3.5 Hold (HOLD )
• 3.6 Write Protect (W )
• 3.7 V SS ground
• 3.8 Operating supply voltage (V CC)
• 3.8.1 Device reset
• 3.8.2 Power-up conditions
• 3.8.3 Power-down
• 4 Operating features
• 4.1 Hold condition
• 4.2 Status Register
• 4.3 Data protection and protocol control
• 5 Instructions
• 5.1 Write Enable (WREN)
• 5.2 Write Disable (WRDI)
• 5.3 Read Status Register (RDSR)
• 5.3.1 WIP bit
• 5.3.2 WEL bit
• 5.3.3 BP1, BP0 bits
• 5.3.4 SRWD bit
• 5.4 Write Status Register (WRSR)
• 5.5 Read from Memory Array (READ)
• 5.6 Write to Memory Array (WRITE)

Features

■ Compatible with the Serial Peripheral Interface (SPI) bus ■ Memory array – 256 Kb (32 Kbytes) of EEPROM – Page size: 64 bytes ■ Additional Write lockable Page (Identification page) ■ Write – Byte Write within 5 ms – Page Write within 5 ms ■ Write Protect: quarter, half or whole memory array ■ High-speed clock frequency (20 MHz) ■ Single supply voltage: 1.8 V to 5.5 V ■ More than 1 Million Write cycles ■ More than 40-year data retention ■ Enhanced ESD Protection ■ Packages –E C O P A C K 2® (RoHS compliant and Halogen-free) SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width SO8 (MW) 200 mil width WLCSP (CS)

M95256-DR, M95256, M95256-W, M95256-R Contents Doc ID 12276 Rev 11 3/48

Table 22. SO8 wide – 8 lead plastic small outline, 200 mils body width, package

1 Description

compatible bus. Their memory array is organized as 32768 × 8 bits. The device is accessed by a simple serial interface that is SPI-compatible. Figure 1. Logic diagram The bus signals are C, D and Q, as shown in Table 1 and Figure 1. can be interrupted using Hold (HOLD). Figure 2. 8-pin package connections

1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1.

ST Microelectronics must never be exposed to UV light.

Figure 3. WLCSP connections (top view, marking side, with balls on the underside) Table 1. Signal names

2 Memory organization

The memory is organized as shown in Figure 4. Figure 4. Block diagram

1 Page

M95256-DR, M95256, M95256-W, M95256-R Signal description Doc ID 12276 Rev 11 9/48

3 Signal description

See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device.

3.1 Serial Data output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).

3.2 Serial Data input (D)

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C).

3.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data output (Q) changes after the falling edge of Serial Clock (C).

3.4 Chip Select (S )

When this input signal is high, the device is deselected and Serial Data output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power mode. After power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.

3.5 Hold (HOLD )

The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low.

Signal description M95256-DR, M95256, M95256-W, M95256-R 10/48 Doc ID 12276 Rev 11

3.6 Write Protect (W )

The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all write instructions.

3.7 V SS ground

VSS is the reference for the VCC supply voltage.

3.8 Operating supply voltage (V CC)

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 8, Table 9, Table 10). This voltage must remain stable and valid until the end of the transmission of the instructionand, for a Write instruction, until the completion of the internal write cycle (t W). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.

3.8.1 Device reset

In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until V CC reaches the internal Reset threshold voltage (this threshold is defined in DC tables as V RES). (this threshold is lower than the minimum VCC operating voltage defined in Table 8, Table 9 and Table 10). When VCC passes over the POR threshold, the device is reset and in the following state:

• in Standby Power mode,
• deselected (note that a further instruction must be preceded by a falling edge on Chip Select (S) to be executed),
• Status Register value: – the Write Enable Latch (WEL) is reset to 0, – Write In Progress (WIP) is reset to 0, – The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits) When V CC passes over the POR threshold, the device is reset and enters the Standby Power mode, however, the device must not be accessed until VCC reaches a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range defined in Table 8, Table 9 and Table 10).

3.8.2 Power-up conditions

When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage, it is

M95256-DR, M95256, M95256-W, M95256-R Operating features Doc ID 12276 Rev 11 11/48 therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see Figure 17). In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge sensitive as well as level sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S ). This ensures that Chip Select (S) must have been High, prior to going Low to start the first operation. The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Table 8, Table 9 and Table 10 and the rise time must not vary faster than 1 V/µs.

3.8.3 Power-down

During Power-down (continuous decrease of VCC supply voltage below the minimum VCC operating voltage defined in Table 8, Table 9 and Table 10), the device must be:

• deselected (Chip Select S should be allowed to follow the voltage applied on VCC)
• in Standby Power mode (there should not be an internal Write cycle in progress).

4 Operating features

4.1 Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data input (D) and Serial Clock (C) are Don’t Care. To enter the Hold condition, the device must be selected, with Chip Select (S) low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the Hold (HOLD ) signal is driven low at the same time as Serial Clock (C) already being low (as shown in Figure 5). The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as Serial Clock (C) already being low. Figure 5 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being low.

Figure 5. Hold condition activation

4.2 Status Register

see Section 5.3: Read Status Register (RDSR).

4.3 Data protection and protocol control

within applications that could experience problems if memory bytes are corrupted.

• Write and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.
• All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: –P o w e r - u p – Write Disable (WRDI) instruction completion – Write Status Register (WRSR) instruction completion – Write (WRITE) instruction completion
• The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be configured as read-only.
• The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits of the Status Register. For any instruction to be accepted, and executed, Chip Select (S) must be driven high after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C). Two points need to be noted in the previous sentence:
• The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions).
• The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus transaction for some other device on the SPI bus.

Table 2. Write-protected block size

5 Instructions

Each instruction starts with a single-byte code, as summarized in Table 3. Table 3. Instruction set Table 4. M95256-R instruction set

1. Address bit A10 must be 0, all other address bits are Don't Care.
2. Address bit A10 must be 1, all other address bits are Don't Care.

5.1 Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. Figure 6. Write Enable (WREN) sequence

5.2 Write Disable (WRDI)

and the bits of the instruction byte are shifted in, on Serial Data input (D).

• Power-up
• WRDI instruction execution
• WRSR instruction completion
• WRITE instruction completion

Figure 7. Write Disable (WRDI) sequence

5.3 Read Status Register (RDSR)

to read the Status Register continuously, as shown in Figure 8.

5.3.1 WIP bit

5.3.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. Latch is reset and no Write or Write Status Register instruction is accepted.

5.3.3 BP1, BP0 bits

Hardware Protected mode has not been set.

5.3.4 SRWD bit

Write Status Register (WRSR) instruction is no longer accepted for execution. Table 5. Status Register format

Figure 8. Read Status Register (RDSR) sequence

5.4 Write Status Register (WRSR)

(C). Otherwise, the Write Status Register (WRSR) instruction is not properly executed. The instruction sequence is shown in Figure 9. Latch) is also reset when the Write cycle tW is completed.

• The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as read only, as defined in Table 2.
• The SRWD bit (Status Register Write Disable bit), in accordance with the signal read on the Write Protect pin (W), allows the user to set or reset the Write protection mode of the Status Register itself, as defined in Table 6 When in Write Protected mode, the Write Status Register (WRSR) instruction is not executed. The contents of the SRWD and BP1, BP0 bits are updated after the completion of the WRSR instruction, including the tW Write cycle. The Write Status Register (WRSR) instruction has no effect on bits b6, b5, b4, b1, b0 of the Status Register. Bits b6, b5, b4 are always read as 0.

Table 6. Protection modes

1. As defined by the values in the Block Protect ( BP1, BP0) bits of the Status Register, as shown in Table 6.

The protection features of the device are summarized in Table 6.

• If Write Protect (W) input pin is driven high, it is possible to write to the Status Register (provided that the WEL bit has previously been set by a WREN instruction.
• If Write Protect (W) input pin is driven low, it is not possible to write to the Status Register even if the WEL bit has previously been set by a WREN instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:
• either by setting the SRWD bit after driving Write Protect (W) input pin low,
• or by driving Write Protect (W) input pin low after setting the SRWD bit. Once entered in the Hardware Protected mode (HPM), the only way to exit the HPM mode is to pull high the Write Protect (W) input pin. If Write Protect (W) input pin is permanently tied high, the Hardware Protected mode (HPM) can never be activated, and only the Software Protected mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used.

Figure 9. Write Status Register (WRSR) sequence

5.5 Read from Memory Array (READ)

that address is shifted out, on Serial Data output (Q). incremented, and the byte of data at the new address is shifted out. Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. Figure 10. Read from Memory Array (READ) sequence

1. The most significant address bit (b15) is Don’t Care.

5.6 Write to Memory Array (WRITE)

Table 19 and Table 20.), at the end of which the Write in Progress (WIP) bit is reset to 0. towards the end of the same page, can be written in a single internal Write cycle.

• if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before)
• if a Write cycle is already in progress
• if the device has not been deselected, by Chip Select (S) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in)
• if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits. Note: The self-timed Write cycle t W is internally executed as a sequence of two consecutive events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as “1”.

Figure 11. Byte Write (WRITE) sequence

1. The most significant address bit (b15) is Don’t Care.

Figure 12. Page Write (WRITE) sequence

1. The most significant address bit (b15) is Don’t Care.

5.6.1 ECC (error correctio n code) and Write cycling

optimize the number of Write cycles. using a cycling routine that writes to the device in multiples of 4-byte words.

5.7 Read Identification Page (available only in M95256-DR

permanently locked in Read-only mode. Reading this page is achieved with the Read Identification Page instruction (see Table 4). register is automatically incremented, and the byte of data at the new address is shifted out. 40d, as the ID page boundary is 64 bytes). The instruction is not accepted, and is not executed, if a write cycle is currently in progress. Figure 13. Read Identification Page sequence

5.8 Write Identification Page (available only in M95256-DR

permanently locked in Read-only mode. of which the Write in Progress (WIP) bit is reset to 0. has been latched in, indicating that the instruction is being used to write a single byte. are overwritten with the incoming data. (The page size of these devices is 64 bytes).

• if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a Write Enable instruction)
• if Status register bits (BP1, BP0) = (1, 1)
• if a write cycle is already in progress
• if the device has not been deselected, by Chip Select (S) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that was latched in)
• if the Identification page is locked by the Lock Status bit

Figure 14. Write Identification Page sequence

5.9 Read Lock Status (available only in M95256-DR devices)

in on Serial Data input (D). Address bit A10 must be 1, all other address bits are Don't Care. The instruction sequence is shown in Figure 15. Figure 15. Read Lock Status sequence

5.10 Lock ID (available on ly in M95256-DR devices)

Care. The data byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care. the Lock ID instruction is not executed.

• if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a Write Enable instruction)
• if Status register bits (BP1,BP0) = (1,1)
• if a write cycle is already in progress
• if the device has not been deselected, by Chip Select (S) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that was latched in)
• if the Identification page is locked by the Lock Status bit

Figure 16. Lock ID sequence

6 Delivery state

Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.

7 Connecting to the SPI bus

These devices are fully compatible with the SPI protocol. Serial Data output (Q) line at a time, the other memory devices are high impedance. Figure 17. Bus master and memory devices on the SPI bus

1. The Write Protect (W ) and Hold (HOLD) signals should be driven, high or low as appropriate.

bus master leaves the S line in the high-impedance state.

time, and so, that the tSHCH requirement is met. The typical value of R is 100 k.

7.1 SPI modes

• CPOL=0, CPHA=0
• CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 18, is the clock polarity when the bus master is in Stand-by mode and not transferring data:
• C remains at 0 for (CPOL=0, CPHA=0)
• C remains at 1 for (CPOL=1, CPHA=1)

Figure 18. SPI modes supported

8 Maximum rating

Table 7. Absolute maximum ratings

1. Compliant with JEDEC Std J-STD- 020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®

9 DC and AC parameters

match the measurement conditions when relying on the quoted parameters. Table 8. Operating conditions (M95256) Table 9. Operating conditions (M95256-W) Table 10. Operating conditions (M95256-R and M95256-DR) Table 11. AC measurement conditions (1)

1. Output Hi-Z is defined as the point where data out is no longer driven.
2. 100 pF when the clock frequency f C is less than 10 MHz, 30 pF when the clock frequency fC is equal to or

Figure 19. AC measurement I/O waveform Table 12. Capacitance (1)

1. Sampled only, not 100% tested.

Table 13. DC characteristics (M95256, device grade 3)

1. For all 5 V range devices, the device meets the out put requirements for both TTL and CMOS standards.

Table 14. DC characteristics (M95256-W, device grade 6)

1. Preliminary data: 2mA with the new product identified with process letter K.
2. For new product identified with process letter K (preliminary data)
3. Characterized value, not tested in production.
4. 3 µA with the new product identified with process letter K (Preliminary data)
5. 2 µA with the new product identified with process letter K (Preliminary data)

Table 15. DC characteristics (M95256-W, device grade 3)

1. Characterized value, not tested in production.

Table 16. DC characteristics (M95256-R, M95256-DR, device grade 6) (1)

1. New product identified with process letter K.
2. If the application uses the M95256-R, M95256-DR device with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C, please refer

to Table 14: DC characteristics (M95256-W, device grade 6) instead of the above table.

1. 2 mA for the new product identified with the process letter K (Preliminary data).
2. Only the new product identified with the process letter K can run at 5 MHz (Preliminary data)
3. Characterized value, not tested in production.

Table 17. AC characteristics (M95256, device grade 3)

1. t CH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characteri zation, not tested in production.

Table 18. AC characteristics, new M95256-W, device grade 6

1. t CH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characteriza tion, not tested in production.

Table 19. AC characteristics (M95256-W, device grade 3)

1. t CH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characteri zation, not tested in production.

Table 20. AC characteristics (M95256-DR, M95256-R device grade 6)

1. Current products are identifi ed by process letters “AB”.
2. New products are identified by process letter K. For these new products, the test flow guarantees the AC parameter values

5.0 V). The M95256-DR is available as only "new product" type.

1. t CH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characterization, not 100% tested in production.

conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 23. SO8N – 8 lead plastic small outli ne, 150 mils body width, package outline Table 21. SO8N – 8 lead plastic small outline, 150 mils body width, package data

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 24. SO8 wide – 8 lead plastic small outline, 200 mils body width, package

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 25. TSSOP8 – 8 lead thin shrink small outline, package outline Table 23. TSSOP8 – 8 lead thin shrink small outline, package mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 26. M95256-DR WLCSP, 0.5 mm pitch, package outline Table 24. M95256-DR WLCSP, 0.5 mm pitch, package mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. N is the total number of terminals.

11 Part numbering

of this device, please contact your nearest ST Sales Office. Table 25. Ordering information scheme 6 = Industrial temperature range, –40 to 85 °C.

1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.

nearest ST sales office for a copy.

1. Used only for device gr ade 3 and WLCSP packages.

soldering conditions are also marked on the inner box label. Table 26. Available M95256x products (package, voltage range, temperature grade) Table 27. Available M95256-DR products (package, voltage range, temperature

Table 28. Document revision history AC characteristics, and ordering information). products, including availability of the SO8 narrow package. M95128 datasheet merged back in. Product List summary table added.

M95256-DR part number added. Updated Section 1: Description. Table 28. Document revision history (continued)