M95128 STMICROELECTRONICS | Alldatasheet
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Technical content
Table 1. Product List Figure 1. Packages
M95256, M95128 SIGNAL DESCRIPTION During all operations, VCC must be held stable and within the specified valid range: VCC (min) to VCC (max). All of the input and output signals must be held High or Low (according to voltages of VIH, VOH , VIL or VOL , as specified in Table 13. to Table 17.). These signals are described next. Serial Data Output (Q).This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D).This input signal is used to transfer data serially into the device. It receives in- structions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C).This input signal provides the timing of the serial interface. Instructions, address- es, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select (S ).When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Stand- by Power mode. Driving Chip Select (S ) Low se- lects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. Hold (HOLD ).The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be se- lected, with Chip Select (S ) driven Low. Write Protect (W).The main purpose of this in- put signal is to freeze the size of the area of mem- ory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either High or Low, and must be stable during all write instructions.
Figure 5. SPI Modes Supported
Figure 7. shows the position of the Status Register cates the status of the internal Write Enable Latch. be software protected against Write instructions. Table 3. Status Register Format they are accepted for execution. the memory to be configured as read-only. This is the Software Protected Mode (SPM). the Hardware Protected Mode (HPM). some other device on the SPI bus. Table 4. Write-Protected Block Size
The memory is organized as shown in Figure 7.. Figure 7. Block Diagram
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Table 5. Instruction Set
Write or Write Status Register cycle is in progress. bit before sending a new instruction to the device. tinuously, as shown in Figure 10.. cates the status of the internal Write Enable Latch. be software protected against Write instructions. Figure 10. Read Status Register (RDSR) Sequence
the Write Enable Latch (WEL). The instruction sequence is shown in Figure 11.. Register. b6, b5 and b4 are always read as 0. pleted, the Write Enable Latch (WEL) is reset. ware Protected Mode (HPM) is entered. Table 6. Protection Modes Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 6..
the Status Register, can be used. Figure 11. Write Status Register (WRSR) Sequence
(S) signal can occur at any time during the cycle. ed, if a Write cycle is currently in progress. Figure 12. Read from Memory Array (READ) Sequence Note: The most significant address bits (b15 for the M95256, and bits b15 and b14 for the M95128) are Don’t Care.
lect (S) High at a byte boundary of the input data. in Progress (WIP) bit is reset to 0. Figure 13. Byte Write (WRITE) Sequence Note: The most significant address bits (b15 for the M95256, and bits b15 and b14 for the M95128) are Don’t Care.
Figure 14. Page Write (WRITE) Sequence Note: The most significant address bits (b15 for the M95256, and bits b15 and b14 for the M95128) are Don’t Care.
M95256, M95128 POWER-UP AND DELIVERY STATE Power-up State After Power-up, the device is in the following state: – Standby Power mode – deselected (after Power-up, a falling edge is required on Chip Select (S ) before any instructions can be started). – not in the Hold Condition – the Write Enable Latch (WEL) is reset to 0 – Write In Progress (WIP) is reset to 0 The SRWD, BP1 and BP0 bits of the Status Reg- ister are unchanged from the previous power- down (they are non-volatile bits). Initial Delivery State The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
Table 7. may cause permanent damage to the de- Table 7. Absolute Maximum Ratings
Table 8. Operating Conditions (M95xxx) Table 9. Operating Conditions (M95xxx-W) Note: 1. This product is under development. For more information, please contact your nearest ST sales office. Table 10. Operating Conditions (M95xxx-R) Note: 1. This product is under development. For more information, please contact your nearest ST sales office.
Table 11. AC Measurement Conditions Note: Output Hi-Z is defined as the point where data out is no longer driven. Figure 15. AC Measurement I/O Waveform Table 12. Capacitance Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 5 MHz.
Table 13. DC Characteristics (M95xxx, Device Grade 6) Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards. Table 14. DC Characteristics (M95xxx, Device Grade 3) Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards. Table 15. DC Characteristics (M95xxx-W, Device Grade 6)
Table 16. DC Characteristics (M95xxx-W, Device Grade 3) Table 17. DC Characteristics (M95xxx-R) Note: 1. This product is under development. For more infomation, please contact your nearest ST sales office.
- This is preliminary data.
Table 18. AC Characteristics (M95xxx, Device Grade 6)
- Value guaranteed by characterization, not 100% tested in production.
Test conditions specified in Table 11. and Table 8.
Table 19. AC Characteristics (M95xxx, Device Grade 3)
- Value guaranteed by characterization, not 100% tested in production.
Test conditions specified in Table 11. and Table 8.
Table 20. AC Characteristics (M95xxx-W, Device Grade 6)
- Value guaranteed by characterization, not 100% tested in production.
Test conditions specified in Table 11. and Table 9.
Table 21. AC Characteristics (M95xxx-W, Device Grade 3)
- Value guaranteed by characterization, not 100% tested in production.
Test conditions specified in Table 11. and Table 9.
Table 22. AC Characteristics (M95xxx-R)
- Value guaranteed by characterization, not 100% tested in production.
- This product is under development. For more infomation, please contact your nearest ST sales office.
- This is preliminary data.
Test conditions specified in Table 11. and Table 10.
Figure 18. Output Timing
Figure 19. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline Note: Drawing is not to scale. Table 23. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
Figure 20. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline Note: Drawing is not to scale. Table 24. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
Figure 21. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Outline Note: Drawing is not to scale. Table 25. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Mechanical Data
Figure 22. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline Note: Drawing is not to scale. Table 26. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
Table 27. Ordering Information Scheme tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. 6 = Industrial temperature range, –40 to 85 °C. 3 = Device tested with High Reliability Certified Flow1.
M95256, M95128
REVISION HISTORY
Table 28. Document Revision History 08-Feb-2002 2.7 Announcement made of planned upgrade to 10 MHz clock for the 5V , –40 to 85°C, range. availability of the SO8 narrow package.
M95256, M95128 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America