M95128_06 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Summary description
- 2 Memory organization
- 3 Signal description
- 3.1 Serial Data Output (Q)
- 3.2 Serial Data Input (D)
- 3.3 Serial Clock (C)
- 3.4 Chip Select (S)
- 3.5 Hold (HOLD )
- 3.6 Write Protect (W)
- 3.7 Supply voltage (VCC )
- 3.7.1 Operating supply voltage VCC
- 3.7.2 Power-up conditions
- 3.7.3 Internal device reset
- 3.7.4 Power-down
- 4 Operating features
- 4.1 Hold condition
- 4.2 Status Register
- 4.3 Data Protection and protocol control
- 5 Instructions
- 5.1 Write Enable (WREN)
- 5.2 Write Disable (WRDI)
- 5.3 Read Status Register (RDSR)
- 5.3.1 WIP bit
- 5.3.2 WEL bit
- 5.3.3 BP1, BP0 bits
- 5.3.4 SRWD bit
- 5.4 Write Status Register (WRSR)
- 5.5 Read from Memory Array (READ)
- 5.6 Write to Memory Array (WRITE)
128 Kbit Serial SPI bus EEPROM
■ Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes) ■ Single Supply Voltage: – 4.5 to 5.5V for M95128 – 2.5 to 5.5V for M95128-W – 1.8 to 5.5V for M95128-R ■ High Speed – 5MHz Clock Rate, 5ms Write Time ■ Status Register ■ Hardware Protection of the Status Register ■ BYTE and PAGE WRITE (up to 64 Bytes) ■ Self-Timed Programming Cycle ■ Adjustable Size Read-Only EEPROM Area ■ Enhanced ESD Protection ■ More than 100,000 Write Cycles ■ More than 40-Year Data Retention ■ Packages – ECOPACK® (RoHS compliant) SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width
M95128, M95128-W, M95128-R Contents
Table 20. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package
1 Summary description
high speed SPI-compatible bus. The memory array is organized as 16384 x 8 bits. are C, D and Q, as shown in Table 1 and Figure 1. can be interrupted using Hold (HOLD). packages. ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 1. Logic diagram Figure 2. SO and TSSOP connections
- See Section 10: Package mechanical for package dimensions, and how to identify pin-1.
Table 1. Signal names
2 Memory organization
The memory is organized as shown in Figure 3. Figure 3. Block diagram
1 Page
M95128, M95128-W, M95128-R Signal description
3 Signal description
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device.
3.1 Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
3.2 Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C).
3.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
3.4 Chip Select (S )
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) Low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
3.5 Hold (HOLD )
The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
Signal description M95128, M95128-W, M95128-R
3.6 Write Protect (W )
The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either High or Low, and must be stable during all write instructions.
3.7 Supply voltage (V CC )
3.7.1 Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage must be applied: this voltage must be a DC voltage within the specified [VCC (min), VCC (max)] range, as defined in Table 7, Table 8 and Table 9. In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10nF to 100nF) close to the VCC /VSS package pins. The VCC voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW ).
3.7.2 Power-up conditions
When the power supply is turned on, VCC rises from VSS to VCC . During this time, the Chip Select (S) signal is not allowed to float and must follow the VCC voltage. The S line should therefore be connected to VCC via a suitable pull-up resistor. In addition, the Chip Select (S) input offers a built-in safety feature, as it is both edge sensitive and level sensitive. Practically this means that after power-up, the device cannot become selected until a falling edge has first been detected on Chip Select (S). So the Chip Select (S) signal must first have been High and then gone Low before the first operation can be started.
3.7.3 Internal device reset
In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up (continuous rise of V CC ), the device will not respond to any instruction until the VCC has reached the Power On Reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Section 9: DC and AC parameters). When V CC has passed the POR threshold voltage, the device is reset and in the following state:
- in Standby Power mode
- deselected (at next Power-up, a falling edge is required on Chip Select (S) before any instructions can be executed)
- not in the Hold Condition Status Register state: – the Write Enable Latch (WEL) bit is reset to 0 – the Write In Progress (WIP) bit is reset to 0. The SRWD, BP1 and BP0 bits of the Status Register are at the same logic level as when the device was last powered down (they are non-volatile bits).
3.7.4 Power-down
the voltage applied on VCC .
4 Operating features
4.1 Hold condition
resetting the clocking sequence. Input (D) and Serial Clock (C) are Don’t Care. To enter the Hold condition, the device must be selected, with Chip Select (S) Low. Normally, the device is kept selected, for the whole duration of the Hold condition. Serial Clock (C) already being Low (as shown in Figure 4). Serial Clock (C) already being Low. with Serial Clock (C) being Low. Figure 4. Hold condition activation
4.2 Status Register
see Section 5.3: Read Status Register (RDSR).
4.3 Data Protection and protocol control
within applications that could experience problems if memory bytes are corrupted.
- Write and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.
- All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: –P o w e r - u p – Write Disable (WRDI) instruction completion – Write Status Register (WRSR) instruction completion – Write (WRITE) instruction completion
- The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read- only. This is the Software Protected Mode (SPM).
- The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits to be protected. This is the Hardware Protected Mode (HPM). For any instruction to be accepted, and executed, Chip Select (S) must be driven High after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C). Two points need to be noted in the previous sentence:
- The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions).
- The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus transaction for some other device on the SPI bus.
Table 2. Write-Protected block size
5 Instructions
Each instruction starts with a single-byte code, as summarized in Table 3.
5.1 Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. Figure 5. Write Enable (WREN) sequence Table 3. Instruction set
5.2 Write Disable (WRDI)
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
- Power-up
- WRDI instruction execution
- WRSR instruction completion
- WRITE instruction completion.
Figure 6. Write Disable (WRDI) sequence
5.3 Read Status Register (RDSR)
to read the Status Register continuously, as shown in Figure 7.
5.3.1 WIP bit
5.3.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. Latch is reset and no Write or Write Status Register instruction is accepted.
5.3.3 BP1, BP0 bits
Hardware Protected mode has not been set.
5.3.4 SRWD bit
Write Status Register (WRSR) instruction is no longer accepted for execution. Table 4. Status Register format
Figure 7. Read Status Register (RDSR) sequence
M95128, M95128-W, M95128-R Instructions
5.4 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (S ) Low, followed by the instruction code and the data byte on Serial Data Input (D). The instruction sequence is shown in Figure 8. The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the Status Register. b6, b5 and b4 are always read as 0. Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S ) is driven High, the self-timed Write Status Register cycle (whose duration is tW ) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read- only, as defined in Table 4. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W ) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0) bits are frozen at their current values from just before the start of the execution of Write Status Register (WRSR) instruction. The new, updated, values take effect at the moment of completion of the execution of Write Status Register (WRSR) instruction.
The protection features of the device are summarized in Table 2.
- If Write Protect (W) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction.
- If Write Protect (W) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:
- by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) Low
- or by driving Write Protect (W) Low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W) High. If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used.
Table 5. Protection modes
- As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 5.
Figure 8. Write Status Register (WRSR) sequence
5.5 Read from Memory Array (READ)
that address is shifted out, on Serial Data Output (Q). incremented, and the byte of data at the new address is shifted out. Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. Figure 9. Read from Memory Array (READ) sequence
- The most significant address bits (b15, b14) are Don’t Care.
5.6 Write to Memory Array (WRITE)
shifted in, on Serial Data Input (D). the end of which the Write in Progress (WIP) bit is reset to 0. towards the end of the same page, can be written in a single internal Write cycle.
- if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before)
- if a Write cycle is already in progress
- if the device has not been deselected, by Chip Select (S) being driven High, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in)
- if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
Figure 10. Byte Write (WRITE) sequence
- The most significant address bits (b15, b14) are Don’t Care.
Figure 11. Page Write (WRITE) sequence
- The most significant address bits (b15, b14) are Don’t Care.
5.6.1 ECC (Error Correction Code) and Write cycling
erroneous during a Read operation, the ECC detects it and replaces it by the correct value. The read reliability is therefore much improved by the use of this feature. Bytes in order to benefit from the larger amount of Write cycles. routine that writes to the device Page by Page (that is, by multiples of 4-Byte packets). number of 100,000 Write cycles.
6 Delivery state
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
7 Connecting to the SPI bus
These devices are fully compatible with the SPI protocol. others being high impedance. Figure 12. Bus master and memory devices on the SPI bus
- The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
- These pull-up resistors, R, ensure that the M95128, M95128-W, M95128-R are not selected if the Bus Master leaves the S
not become High at the same time, and so, that the tSHCH requirement is met).
7.1 SPI modes
- CPOL=0, CPHA=0
- CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 13, is the clock polarity when the bus master is in Stand-by mode and not transferring data:
- C remains at 0 for (CPOL=0, CPHA=0)
- C remains at 1 for (CPOL=1, CPHA=1)
Figure 13. SPI modes supported
8 Maximum rating
Table 6. Absolute maximum ratings
9 DC and AC parameters
match the measurement conditions when relying on the quoted parameters. Table 7. Operating conditions (M95128) Table 8. Operating conditions (M95128-W) Table 9. Operating conditions (M95128-R)
Figure 14. AC measurement I/O waveform Table 10. AC measurement conditions(1)
- Output Hi-Z is defined as the point where data out is no longer driven.
Table 11. Capacitance(1)
- Sampled only, not 100% tested, at TA=25°C and a frequency of 5 MHz.
Table 12. DC characteristics (M95128, Device Grade 3)
- For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
Table 13. DC characteristics (M95128-W, Device Grade 6)
- Characterized value, not tested in production.
Table 14. DC characteristics (M95128-W, Device Grade 3)
- Characterized value, not tested in production.
Table 15. DC characteristics (M95128-R)
- This is preliminary data.
- Characterized value, not tested in production.
Table 16. AC characteristics (M95128, Device Grade 3)
- tCH + tCL must never be less than the shortest possible clock period, 1 / fC (max)
- Value guaranteed by characterization, not 100% tested in production.
Table 17. AC characteristics (M95128-W, Device Grade 6)
- tCH + tCL must never be less than the shortest possible clock period, 1 / fC (max)
- Value guaranteed by characterization, not 100% tested in production.
Table 18. AC characteristics (M95128-W, Device Grade 3)
- tCH + tCL must never be less than the shortest possible clock period, 1 / fC (max)
- Value guaranteed by characterization, not 100% tested in production.
Table 19. AC characteristics (M95128-R)
- This is preliminary data.
- tCH + tCL must never be less than the shortest possible clock period, 1 / fC (max)
- Value guaranteed by characterization, not 100% tested in production.
Figure 17. Output timing
Figure 18. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package outline
Figure 19. TSSOP8 – 8 lead Thin Shrink Small Outline, package outline Table 21. TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data
11 Part numbering
of this device, please contact your nearest ST Sales Office. soldering conditions are also marked on the inner box label. Table 22. Ordering information scheme
- The M95128 5V part is offered in "V" process (F6DP26%) only.
6 = Industrial temperature range, –40 to 85 °C.
- ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
nearest ST sales office for a copy.
Table 23. Document revision history AC characteristics, and ordering information). products, including availability of the SO8 narrow package. M95128 datasheet merged back in. Product List summary table added.