M95128-DRDW8TP

M95128-DRE STMICROELECTRONICS | Alldatasheet

Document overview

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• PDF pages: 41

Technical content

Datasheet sections

• 1 Description
• 2 Signal description
• 2.1 Serial Data output (Q)
• 2.2 Serial Data input (D)
• 2.3 Serial Clock (C)
• 2.4 Chip Select (S
• 2.5 Hold (HOLD )
• 2.6 Write Protect (W )
• 2.7 V SS ground
• 2.8 V CC supply voltage
• 3 Operating features
• 3.1 Active power and Standby power modes
• 3.2 SPI modes
• 3.3 Hold mode
• 3.4 Protocol control and data protection
• 3.4.1 Protocol control
• 3.4.2 Status Register and data protection
• 3.5 Identification page
• 4 Instructions
• 4.1 Write Enable (WREN)
• 4.2 Write Disable (WRDI)
• 4.3 Read Status Register (RDSR)
• 4.4 Write Status Register (WRSR)
• 4.5 Read from Memory Array (READ)
• 4.6 Write to Memory Array (WRITE)
• 4.7 Read Identification Page (RDID)
• 4.8 Write Identification Page (WRID)
• 4.9 Read Lock Status (RDLS)
• 4.10 Lock Identification Page (LID)

Features

• Compatible with the Serial Peripheral Interface (SPI) bus
• Memory array – 128 Kbit (16 Kbytes) of EEPROM – Page size: 64 bytes – Write protection by bl ock: 1/4, 1/2 or whole memory – Additional Write lockable Page (Identification page)
• Extended temperature and voltage range – Up to 105 °C (V CC from 1.8 V to 5.5 V)
• High speed clock frequency – 20 MHz for V CC ≥ 4.5 V – 10 MHz for V CC ≥ 2.5 V – 5 MHz for V CC ≥ 1.8 V
• Schmitt trigger inputs for noise filtering
• Short Write cycle time – Byte Write within 4 ms – Page Write within 4 ms
• Write cycle endurance – 4 million Write cycles at 25 °C – 1.2 million Write cycles at 85 °C – 900 k Write cycles at 105 °C
• Data retention – more than 50 years at 105 °C – 200 years at 55 °C
• ESD Protection (Human Body Model) – 4000 V
• Packages – RoHS-compliant and halogen-free (ECOPACK2 TSSOP8 (DW) 169 mil width SO8 (MN) 150 mil width WFDFPN8 (MF) 2 x 3 mm

Table 11. Operating conditions (volt age range R, temperature range 8) Table 16. WFDFPN8 (MLP8) – 8-lead very thin fine pitch dual flat package no lead

1 Description

M95128-DRE is compliant with the level of reliability defined by the AEC-Q100 grade 2. The device is accessed by a simple serial SPI compatible interface running up to 20 MHz. an embedded Error Correction Code logic. parameters which can be later permanently locked in read-only mode. Figure 1. Logic diagram

Figure 2. 8-pin package connections

1. See Package mechanical data section for package dimensions and how to identify pin-1.

Table 1. Signal names

Signal description M95128-DRE

2 Signal description

All input signals must be held high or low (according to voltages of VIH or VIL, as specified in Table 12). These signals are described below.

2.1 Serial Data output (Q)

This output signal is used to transfer data serially out of the device during a Read operation. Data is shifted out on the falling edge of Serial Clock (C), most significant bit (MSB) first. In all other cases, the Serial Data output is in high impedance.

2.2 Serial Data input (D)

This input signal is used to transfer data serially into the device. D input receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C), most significant bit (MSB) first.

2.3 Serial Clock (C)

This input signal allows to synchronize the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

2.4 Chip Select (S )

Driving Chip Select (S) low selects the device in order to start communication. Driving Chip Select (S) high deselects the device and Serial Data output (Q) enters the high impedance state.

2.5 Hold (HOLD )

The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device.

2.6 Write Protect (W )

This pin is used to write-protect the Status Register.

2.7 V SS ground

VSS is the reference for all signals, including the VCC supply voltage.

M95128-DRE Signal description

2.8 V CC supply voltage

VCC is the supply voltage pin. Refer to Section 3.1: Active power and Standby power modes and to Section 5.1: Supply voltage (VCC).

3 Operating features

3.1 Active power and Standby power modes

When Chip Select (S) is low, the device is selected and in the Active power mode. drops to ICC1, as specified in Table 12.

3.2 SPI modes

• CPOL=0, CPHA=0
• CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 3, is the clock polarity when the bus master is in Stand-by mode and not transferring data:
• C remains at 0 for (CPOL=0, CPHA=0)
• C remains at 1 for (CPOL=1, CPHA=1)

Figure 3. SPI modes supported

3.3 Hold mode

resetting the clocking sequence. Clock (C) is or becomes low. Figure 4. Hold mode activation Deselecting the device while it is in Hold mode resets the paused communication.

3.4 Protocol control and data protection

3.4.1 Protocol control

prior to going low, in order to start the first operation.

• the Write Enable Latch (WEL) bit must be set by a Write Enable (WREN) instruction
• a falling edge and a low state on Chip Select (S) during the whole command must be decoded
• instruction, address and input data must be sent as multiple of eight bits
• the command must include at least one data byte
• Chip Select (S) must be driven high exactly after a data byte boundary Write command can be discarded at any time by a rising edge on Chip Select (S) outside of a byte boundary. To execute Read commands (READ, RDSR, RDID, RDLS), the device must decode:
• a falling edge and a low level on Chip Select (S) during the whole command
• instruction and address as multiples of eight bits (bytes) From this step, data bits are shifted out until the rising edge on Chip Select (S). (/,$ (OLD CONDITION #ONDITION (OLD CONDITION -36

3.4.2 Status Register and data protection

Note: Bits b6, b5, b4 are always read as 0. the device is ready to decode a new command. becomes ready (WIP=0) to decode a new command. executed; when WEL is set to 0, any decoded Write instruction is not executed.

• Write Disable (WRDI) instruction completion
• Write instructions (WRITE, WRSR, WRID, LID) completion including the write cycle time tW
• Power-up BP1, BP0 bits The Block Protect bits (BP1, BP0) are non-volatile. BP1,BP0 bits define the size of the memory block to be protected against write instructions, as defined in Table 2. These bits are written with the Write Status Register (WRSR) instruction, provided that the Status Register is not protected (refer to “SRWD bit and W input signal”, on page 13).

Table 2. Status Register format

Register, regardless of whether the pin Write Protect (W) is driven high or low.

• Case 1: if pin W is driven high, it is possible to write the Status Register.
• Case 2: if pin W is driven low, it is not possible to write the Status Register (WRSR is discarded) and therefore SRWD,BP1,BP0 bits cannot be changed (the size of the protected memory block defined by BP1,BP0 bits is frozen). Case 2 can be entered in either sequence:
• Writing SRWD bit to 1 after driving pin W low, or
• Driving pin W low after writing SRWD bit to 1. The only way to exit Case 2 is to pull pin W high. Note: if pin W is permanently tied high, the Status Register cannot be write-protected. The protection features of the device are summarized in Table 4.

3.5 Identification page

• Device identification: the three first bytes are programmed by STMicroelectronics with the Device identification code, as shown in Table 5.
• Application parameters: the bytes after the Device identification code are available for application specific data.

Table 3. Write-protected block size Table 4. Protection modes Status Register is writable. 1 0 Status Register is write-protected.

The Read, Write, Lock Identification Page instructions are detailed in Section 4: Instructions. Table 5. Device identification bytes

4 Instructions

byte, as summarized in Table 6. a Wait state until deselected. defined by two bytes as explained in Table 7. Table 6. Instruction set Table 7. Significant bits within the two address bytes(1)

1. A: Significant address bit.

4.1 Write Enable (WREN)

Chip Select (S) input is driven high and the WEL bit is set (Status Register bit). Figure 5. Write Enable (WREN) sequence

4.2 Write Disable (WRDI)

what the Chip Select (S) input is driven high and the WEL bit is reset (Status Register bit). the WEL bit is reset to 0 with no effect on the ongoing Write cycle. Figure 6. Write Disable (WRDI) sequence

4.3 Read Status Register (RDSR)

Status Register content is then shifted out (MSB first) on Serial Data Output (Q). Register functionality is detailed in Section 3.4.2: Status Register and data protection. Figure 7. Read Status Register (RDSR) sequence

4.4 Write Status Register (WRSR)

driving the Chip Select (S) signal high. in the Status Register (see Table 2: Status Register format). The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. Figure 8. Write Status Register (WRSR) sequence

4.5 Read from Memory Array (READ)

The READ instruction is used to read the content of the memory. (Q). The first addressed byte can be any byte within any page. read with a single READ instruction. Read cycle to be continued indefinitely. are shifted out on Serial Data Output (Q). The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. Figure 9. Read from Memory Array (READ) sequence

1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.

4.6 Write to Memo ry Array (WRITE)

The WRITE instruction is used to write new data in the memory. Select (S) high at a data byte boundary. Figure 10 shows a single byte write. Figure 10. Byte Write (WRITE) sequence

1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.

A Page write is used to write several bytes inside a page, with a single internal Write cycle. only the last 64 bytes are written. S), and continues for a period tW (as specified in Table 13).

• if a Write cycle is already in progress
• if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits
• if one of the conditions defined in Section 3.4.1 is not satisfied Note: The self-timed Write cycle t W is internally executed as a sequence of two consecutive events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as “1”. !)$ (IGH)MPEDANCE )NSTRUCTION "IT!DDRESS $ATA"YTE

Figure 11. Page Write (WRITE) sequence

1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.

4.7 Read Identification Page (RDID)

page of 64 bytes which can be written and later permanently locked in Read-only mode). (MSB first) on Serial Data output (Q). The first byte addressed can be any byte within the identification page. incremented and the byte of data at the new address is shifted out. must not exceed the page boundary. Select (S) signal can occur at any time when the data bits are shifted out. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. Figure 12. Read Identification Page sequence The first three bytes of the Identification page offer information about the device itself. Please refer to Section 3.5: Identification page for more information.

4.8 Write Identification Page (WRID)

page of 64 bytes which can also be permanently locked in Read-only mode). address bytes, and at least one data byte are shifted in (MSB first) on Serial Data input (D). the byte address inside the identification page. period tW (as specified in Table 13). Figure 13. Write Identification Page sequence these first three bytes overwrites the Device Identification code.

• If a Write cycle is already in progress
• If the Block Protect bits (BP1,BP0) = (1,1)
• If one of the conditions defined in Section 3.4.1: Protocol control is not satisfied.

4.9 Read Lock Status (RDLS)

The Read Lock Status instruction is used to read the lock status.

Figure 14. Read Lock Status sequence

4.10 Lock Identifi cation Page (LID)

Figure 15. Lock ID sequence

The instruction is discarded, and is not executed, under the following conditions:

• If a Write cycle is already in progress
• If the Block Protect bits (BP1,BP0) = (1,1)
• If one of the conditions defined in Section 3.4.1: Protocol control is not satisfied.

Application design recommendations M95128-DRE

5 Application design recommendations

5.1 Supply voltage (V CC)

5.1.1 Operating supply voltage (V CC)

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 10 and Table 11). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal Write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.

5.1.2 Power-up conditions

When the power supply is turned on, VCC continuously rises from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see Figure 16). The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Table 12. In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the internal threshold voltage (this threshold is defined in the DC characteristics Table 12 as VRES). When VCC passes over the POR threshold, the device is reset and in the following state:

• in the Standby power mode
• deselected
• Status register values: – Write Enable Latch (W EL) bit is reset to 0. – Write In Progress (WIP) bit is reset to 0. – SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
• not in the Hold condition As soon as the VCC voltage has reached a stable value within [VCC(min), VCC(max)] range, the device is ready for operation.

5.1.3 Power-down

• deselected (Chip Select (S) should be allowed to follow the voltage applied on VCC),
• in Standby power mode (there should not be any internal Write cycle in progress).

5.2 Implementing d evices on SPI bus

(Q) line. All the other devices outputs are then in high impedance. Figure 16. Bus master and memory devices on the SPI bus

1. The Write Protect (W ) and Hold (HOLD) signals must be driven high or low as appropriate.

device is not selected if the bus master leaves the /S line in the high impedance state.

Application design recommendations M95128-DRE

5.3 Cycling with Error Correction Code (ECC)

The Error Correction Code (ECC) is an internal logic function which is transparent for the SPI communication protocol. The ECC logic is implemented on each group of four EEPROM bytes(a). Inside a group, if a single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved. Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group(a). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined in Table 9: Cycling performance by groups of 4 bytes. Example1: maximum cycling limit reached with 1 million cycles per byte Each byte of a group can be equally cycled 1 million times (at 25 °C) so that the group cycling budget is 4 million cycles. Example2: maximum cycling limit reached with unequal byte cycling Inside a group, byte0 can be cycled 2 million times, byte1 can be cycled 1 million times, byte2 and byte3 can be cycled 500,000 times, so that the group cycling budget is 4 million cycles. a. A group of four bytes is located at addresses [4 *N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.

6 Delivery state

• the memory array set to all 1s (each byte = FFh),
• Status register: bit SRWD =0, BP1 =0 and BP0 =0,
• Identification page: the first three bytes define the Device identification code (value defined in Table 5). The content of the following bytes is Don’t Care.

7 Absolute maximum ratings

Table 8. Absolute maximum ratings

1. Compliant with JEDEC Std J-STD-020D (for small b ody, Sn-Pb or Pb-free assembly), the ST ECOPACK®

directive 2011/65/EU of July 2011).

1. Positive and negative pulses applied on pin pairs, in accordance with AEC-Q100-002 (compliant with

8 DC and AC parameters

Table 9. Cycling performance by groups of 4 bytes

1. The Write cycle endurance is defined for groups of four data by tes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where

Write cycle endurance is defined by characterization and qualification.

1. A Write cycle is executed when either a Page Write, a By te Write, a WRSR, a WRID or an LID instruction is decoded.

Table 10. Operating conditions (voltage range R, temperature range 8) Table 11. Operating conditions (voltage range R, temperature range 8)

Table 12. DC characteristics (voltage range R, temperature range 8)

1. Characterized only, not 100% tested.
2. Average value during the Write cycle (t

Table 13. AC characteristics

1. t CH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterizati on, not 100% tested in production.
3. t CLQV must be compatible with tCL (clock low time): if tSU is the Read setup time of the SPI bus master, tCL must be equal to

(or greater than) tCLQV+tSU.

Figure 20. Serial output timing

9 Package mechanical data

specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 21. SO8N – 8-lead plastic small outline, 150 mils body width, package outline Table 14. SO8N – 8-lead plastic small outline, 150 mils body width, package

1. Values in inches are converted fr om mm and rounded to four decimal digits.

Figure 22. TSSOP8 – 8-lead thin shrink small outline, package outline Table 15. TSSOP8 – 8-lead thin shrink small outline, package mechanical data

1. Values in inches are converted fr om mm and rounded to four decimal digits.

Figure 23. WFDFPN8 (MLP8) – 8-lead very thin fine pitch dual flat package no lead

1. The central pad (the area E2 by D2 in the above illustra tion) must be either connected to Vss or left floating

(not connected) in the end application.

1. Values in inches are converted fr om mm and rounded to four decimal digits.
2. NX is the number of terminals.
3. ND is the number of terminals on “D” sides.
4. Applied for exposed die paddle and terminals. Ex clude embedding part of exposed die paddle from mea-

10 Part numbering

of this device, please contact your nearest ST sales office. prior to any decision to use these Engineering samples to run qualification activity. Table 17. Ordering information scheme

1. All packages are ECOPACK2 ® (RoHS compliant and free of brominated, chlorinated and antimony-oxide

Table 18. Document revision history 10-Feb-2015 1 Initial release.