M93C86_08 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Description
  • 2 Connecting to the serial bus
  • 3 Operating features
  • 3.1 Supply voltage (V CC)
  • 3.1.1 Operating supply voltage V CC
  • 3.1.2 Power-up conditions
  • 3.1.3 Power-up and device reset
  • 3.1.4 Power-down
  • 4 Memory organization
  • 5 Instructions
  • 5.1 Read Data from Memory
  • 5.2 Write Enable and Write Disable
  • 5.3 Erase Byte or Word
  • 5.4 Write
  • 5.5 Erase All
  • 5.6 Write All
  • 6 READY/BUSY status
  • 7 Initial delivery state
  • 8 Common I/O operation
  • 9 Clock pulse counter
  • 10 Maximum rating
  • 11 DC and AC parameters
  • 12 Package mechanical data

Features

  • Industry standard MICROWIRE bus
  • Single supply voltage: – 4.5 V to 5.5 V for M93Cx6 – 2.5 V to 5.5 V for M93Cx6-W – 1.8 V to 5.5 V for M93Cx6-R
  • Dual organization: by word (x16) or byte (x8)
  • Programming instructions that work on: byte, word or entire memory
  • Self-timed programming cycle with auto- erase: 5 ms
  • READY/BUSY signal during programming
  • 2 MHz clock rate
  • Sequential read operation
  • Enhanced ESD/latch-up behavior
  • More than 1 million write cycles
  • More than 40 year data retention
  • Packages – ECOPACK® (RoHS compliant)

Table 1. Product list

M93C86, M93C76, M93C66, M93C56, M93C46 Contents

Table 24. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package Table 26. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data . . 31

1 Description

(D) and Serial Data output (Q) using the MICROWIRE bus protocol. Figure 1. Logic diagram sizes of the memories are as shown in Table 3. Table 2. Signal names

detail in Table 5. to Table 7.). be read in an internal address register. The data at this address is then clocked out serially. when the highest address is reached). Table 3. Memory size versus organization Table 4. Instruction set for the M93Cx6

Figure 2. DIP, SO, TSSOP and MLP connections (top view)

  1. See Package mechanical data section for package dimensions, and how to identify pin-1.

2 Connecting to the serial bus

Figure 3 shows an example of three memory devices connected to an MCU, on a serial bus. line at a time, the other devices are high impedance. bus master leaves the S line in the high impedance state. SLCH requirement is met. The typical value of R is 100 kΩ. Figure 3. Bus master and memory devices on the serial bus

Operating features M93C86, M93C76, M93C66, M93C56, M93C46

3 Operating features

3.1 Supply voltage (V CC)

3.1.1 Operating supply voltage V CC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied. In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (t W).

3.1.2 Power-up conditions

When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float and should be driven to VSS, it is therefore recommended to connect the S line to VSS via a suitable pull-down resistor. The VCC rise time must not vary faster than 1 V/µs.

3.1.3 Power-up and device reset

In order to prevent inadvertent Write operations during power-up, a power on reset (POR) circuit is included. At power-up (continuous rise of VCC), the device does not respond to any instruction until VCC has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 9, Table 10 and Table 11). When VCC passes the POR threshold, the device is reset and is in the following state:

  • Standby Power mode
  • deselected (assuming that there is a pull-down resistor on the S line)

3.1.4 Power-down

At power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any instruction sent to it. During power-down, the device must be deselected and in the Standby Power mode (that is, there should be no internal Write cycle in progress).

M93C86, M93C76, M93C66, M93C56, M93C46 Memory organization

4 Memory organization

The M93Cx6 memory is organized either as bytes (x8) or as words (x16). If Organization Select (ORG) is left unconnected (or connected to VCC) the x16 organization is selected; when Organization Select (ORG) is connected to Ground (VSS) the x8 organization is selected. When the M93Cx6 is in Standby mode, Organization Select (ORG) should be set either to V SS or VCC for minimum power consumption. Any voltage between VSS and VCC applied to Organization Select (ORG) may increase the Standby current.

5 Instructions

Table 5. to Table 7.. Each instruction consists of the following parts, as shown in Figure 4.:

  • Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock (C) being held low.
  • A start bit, which is the first ‘1’ read on Serial Data Input (D) during the rising edge of Serial Clock (C).
  • Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock (C). (Some instructions also use the first two bits of the address to define the op-code).
  • The address bits of the byte or word that is to be accessed. For the M93C46, the address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization (see Table 5.). For the M93C56 and M93C66, the address is made up of 8 bits for the x16 organization or 9 bits for the x8 organization (see Table 6.). For the M93C76 and M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8 organization (see Table 7.). The M93Cx6 devices are fabricated in CMOS technology and are therefore able to run as slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in Table 20. to Table 23..

Table 5. Instruction set for the M93C46

Table 6. Instruction set for the M93C56 and M93C66

  1. Address bit A8 is not decoded by the M93C56.
  2. Address bit A7 is not decoded by the M93C56.

Table 7. Instruction set for the M93C76 and M93C86

  1. Address bit A10 is not decoded by the M93C76.
  2. Address bit A9 is not decoded by the M93C76.

Instructions M93C86, M93C76, M93C66, M93C56, M93C46

5.1 Read Data from Memory

The Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q). When the instruction is received, the op-code and address are decoded, and the data from the memory is transferred to an output shift register. A dummy 0 bit is output first, followed by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are triggered by the rising edge of Serial Clock (C). The M93Cx6 automatically increments the internal address register and clocks out the next byte (or word) as long as the Chip Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read.

5.2 Write Enable and Write Disable

The Write Enable (WEN) instruction enables the future execution of erase or write instructions, and the Write Disable (WDS) instruction disables it. When power is first applied, the M93Cx6 initializes itself so that erase and write instructions are disabled. After an Write Enable (WEN) instruction has been executed, erasing and writing remains enabled until an Write Disable (WDS) instruction is executed, or until V CC falls below the power-on reset threshold voltage. To protect the memory contents from accidental corruption, it is advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read Data from Memory (READ) instruction is not affected by the Write Enable (WEN) or Write Disable (WDS) instructions.

Figure 4. READ, WRITE, WEN, WDS sequences

5.3 Erase Byte or Word

5.4 Write

Data Input (D) is sampled on the rising edge of Serial Clock (C). line, as described later in this document. instruction before a Write Data to Memory (WRITE) instruction. Figure 5. ERASE, ERAL sequences

5.5 Erase All

5.6 Write All

Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word, be provided. Figure 6. WRAL sequence

READY/BUSY status M93C86, M93C76, M93C66, M93C56, M93C46

6 READY/BUSY status

While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high. (Please note, though, that there is an initial delay, of tSLSH, before this status information becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1) indicates that the M93Cx6 is ready to receive the next instruction. Serial Data Output (Q) remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is decoded.

7 Initial delivery state

The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).

8 Common I/O operation

Serial Data Output (Q) and Serial Data Input (D) can be connected together, through a current limiting resistor, to form a common, single-wire data bus. Some precautions must be taken when operating the memory in this way, mostly to prevent a short circuit current from flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output (Q). Please see the application note AN394 for details.

9 Clock pulse counter

the writing of erroneous data at an erroneous address. instruction is aborted, and the contents of the memory are not modified.

1 Start bit

Figure 7. Write sequence with one clock glitch

10 Maximum rating

Program and other relevant quality documents. Table 8. Absolute maximum ratings

  1. T LEADmax must not be applied for more than 10 s.
  2. Compliant with JEDEC Std J-STD-020C (for smal l body, Sn-Pb or Pb assembly), the ST ECOPACK®

11 DC and AC parameters

match the measurement conditions when relying on the quoted parameters. Table 9. Operating conditions (M93Cx6) Table 10. Operating conditions (M93Cx6-W) Table 11. Operating conditions (M93Cx6-R) Table 12. AC measurement conditions (M93Cx6) (1)

  1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 8. AC testing input output waveforms Table 13. AC measurement conditions (M93Cx6-W and M93Cx6-R) (1)

  1. Output Hi-Z is defined as the point where data out is no longer driven.

Table 14. Capacitance (1)

  1. Sampled only, not 100% tested, at T A = 25 °C and a frequency of 1 MHz.

Table 15. DC characteristics (M93Cx6, device grade 6)

  1. The input and output levels are co mpatible with TTL logic levels.

Table 16. DC characteristics (M93Cx6, device grade 3) Table 17. DC characteristics (M93Cx6-W, device grade 6)

Table 18. DC characteristics (M93Cx6-W, device grade 3)

  1. New product: identified by Process Identification letter W or G or S.

Table 19. DC characteristics (M93Cx6-R)

  1. This product is under development. For more inform ation, please contact your nearest ST sales office.

Table 20. AC characteristics (M93Cx6, device grade 6 or 3) Test conditions specified in Table 12. and Table 9.

  1. Chip Select Input (S) must be brought low for a minimum of t SLSH between consecutive instruction cycles.

Table 21. AC characteristics (M93Cx6-W, device grade 6) Test conditions specified in Table 13. and Table 10.

  1. Chip Select Input (S) must be brought low for a minimum of t SLSH between consecutive instruction cycles.

Table 22. AC characteristics (M93Cx6-W, device grade 3) Test conditions specified in Table 13. and Table 10.

  1. Chip Select Input (S) must be brought low for a minimum of t SLSH between consecutive instruction cycles.

Test conditions specified in Table 13. and Table 10.

Figure 9. Synchronous timing (start and op-code input) Table 23. AC characteristics (M93Cx6-R) Test conditions specified in Table 13. and Table 11.

  1. This product is under development. For more inform ation, please contact your nearest ST sales office.
  2. Chip Select Input (S) must be brought low for a minimum of t SLSH between consecutive instruction cycles.

trademark. ECOPACK specifications are available at www.st.com. Figure 12. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package

  1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package Table 25. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package

  1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 14. UFDFPN8 (MLP8) 8-lead ultra th in fine pitch dual flat package no lead

  1. The central pad (the area E2 by D2 in the abov e illustration) is pulled, internally, to VSS. It must not be
  2. The circle in the top view of the package indicates the position of pin 1.

Table 26. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

  1. Values in inches are converted from mm and rounded to 4 decimal digits.
  2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from

Figure 15. TSSOP8 – 8 lead thin shrink small outline, package outline Table 27. TSSOP8 – 8 lead thin shrink small outline, package mechanical data

  1. Values in inches are converted from mm and rounded to 4 decimal digits.

13 Part numbering

of this device, please contact your nearest ST sales office. Table 28. Ordering information scheme 6 = Industrial temperature range, –40 to 85 °C.

  1. ST strongly recommends the use of the Automo tive Grade devices for use in an automotive

environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.

  1. Used only for device grade 3.

Table 29. Available M93C46-x products (package, voltage range, temperature Table 30. Available M93C56-x products (package, voltage range, temperature Table 31. Available M93C66-x products (package, voltage range, temperature Table 32. Available M93C76-x products (package, voltage range, temperature Table 33. Available M93C86-x products (package, voltage range, temperature

Table 34. Document revision history Document reformatted, and reworded, using the new template. added. VIL(min) improved to –0.45V. removed. Product list summary added. characteristics for current product removed from Tables 20 and 21. Clock rate added to Features. Table 8.: Absolute maximum ratings.

Document reformatted. TSSOP8 3 × 3 mm (DS) package removed. STANDBY POWER MODES section removed. and Table 19. Note 1 added to Table 15. Section 12: Package mechanical data). Table 29, Table 30, Table 31, Table 32 and Table 33 added. 8 lead thin shrink small outline, package mechanical data. Section 2: Connecting to the serial bus added. Device grade 7 removed. M93C76-R root part number added. Section 3.1.2: Power-up conditions corrected. TLEAD modified in Table 8: Absolute maximum ratings. M93C56-R is also offered in TSSOP8 package (see Table 30). TSSOP8 (DW) package specifications updated. Table 34. Document revision history (continued)