M93C86_05 STMICROELECTRONICS | Alldatasheet
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Technical content
Table 1. Product List Figure 1. Packages
using the MICROWIRE bus protocol. offers these devices in ECOPACK® packages. Figure 2. Logic Diagram Table 2. Signal Names memories are as shown in Table 3. Table 3. Memory Size versus Organization Table 5. to Table 7.). Table 4. Instruction Set for the M93Cx6
Figure 3. DIP, SO, TSSOP and MLP mensions, and how to identify pin-1. use by STMicroelectronics during test sequences.
M93C86, M93C76, M93C66, M93C56, M93C46 MEMORY ORGANIZATION The M93Cx6 memory is organized either as bytes (x8) or as words (x16). If Organization Select (ORG) is left unconnected (or connected to VCC ) the x16 organization is selected; when Organiza- tion Select (ORG) is connected to Ground (VSS ) the x8 organization is selected. When the M93Cx6 is in stand-by mode, Organization Select (ORG) should be set either to VSS or VCC for minimum power consumption. Any voltage between VSS and VCC applied to Organization Select (ORG) may increase the stand-by current. INTERNAL DEVICE RESET In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up and Power-down, the device must not be selected (that is, the Chip Select Input (S) must be driven Low) until the supply voltage reaches the operating voltage VCC (as defined in Tables 9, 10 and 11). During Power-up (phase during which VCC is low- er than VCC min but increases continuously), the device will not respond to any instruction until VCC has reached the Power On Reset threshold volt- age (this threshold is lower than the minimum V CC operating voltage defined in DC AND AC PARAM- ETERS ). Once VCC has passed the POR thresh- old, the device is reset. Prior to selecting the memory and issuing instruc- tions to it, a valid and stable VCC voltage must be applied. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW ). During Power-down (phase during which VCC de- creases continuously), as soon as VCC drops from the normal operating voltage below the Power On Reset threshold voltage, the device stops re- sponding to any instruction sent to it. ACTIVE POWER AND STANDBY POWER MODES When Chip Select (S) is High, the device is select- ed and in the Active Power mode. It consumes I CC , as specified in Tables 15, 16, 17, 18 and 19. When Chip Select (S) is Low, the device is dese- lected. If no Erase/Write cycle is in progress when Chip Select goes Low, the device enters the Standby Power mode, and the power consumption drops to ICC1 . For the M93Cx6 devices (5V range) the POR threshold voltage is around 3V. For the M93Cx6- W (3V range) and M93Cx6-R (2V range) the POR threshold voltage is around 1.5V.
- to Table 7.. Each instruction consists of the fol-
(D) during the rising edge of Serial Clock (C). the address to define the op-code). 11 bits for the x8 organization (see Table 7.). imum ratings specified in Table 20. to Table 23.. Table 5. Instruction Set for the M93C46 Note: 1. X = Don't Care bit.
Table 6. Instruction Set for the M93C56 and M93C66 Note: 1. X = Don't Care bit.
- Address bit A8 is not decoded by the M93C56.
- Address bit A7 is not decoded by the M93C56.
Table 7. Instruction Set for the M93C76 and M93C86 Note: 1. X = Don't Care bit.
- Address bit A10 is not decoded by the M93C76.
- Address bit A9 is not decoded by the M93C76.
tinuous stream of data can be read. Figure 4. READ, WRITE, EWEN, EWDS Sequences Note: For the meanings of An, Xn, Qn and Dn, see Table 5., Table 6. and Table 7..
- Once the address has been correctly decoded,
sampled on the rising edge of Serial Clock (C). described later in this document. Write Data to Memory (WRITE) instruction. Figure 5. ERASE, ERAL Sequences Note: For the meanings of An and Xn, please see Table 5., Table 6. and Table 7..
the whole memory (all memory bits are set to 1). scribed in the READY/BUSY STATUS section. Ready/Busy line, as described next. Figure 6. WRAL Sequence Note: For the meanings of Xn and Dn, please see Table 5., Table 6. and Table 7..
state, the M93Cx6 ignores any data on the bus. brought Low or until a new start bit is decoded. array set to 1 (each byte contains FFh). contents of the memory are not modified.
1 Start bit
Figure 7. Write Sequence with One Clock Glitch
Table 8. Absolute Maximum Ratings Note: 1. TLEAD max must not be applied for more than 10s.
Table 9. Operating Conditions (M93Cx6) Table 10. Operating Conditions (M93Cx6-W) Table 11. Operating Conditions (M93Cx6-R)
Table 12. AC Measurement Conditions (M93Cx6) Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. Table 13. AC Measurement Conditions (M93Cx6-W and M93Cx6-R) Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 8. AC Testing Input Output Waveforms Table 14. Capacitance Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 1MHz.
Table 15. DC Characteristics (M93Cx6, Device Grade 6) Table 16. DC Characteristics (M93Cx6, Device Grade 7 or 3)
Table 17. DC Characteristics (M93Cx6-W, Device Grade 6)
Table 18. DC Characteristics (M93Cx6-W, Device Grade 7 or 3) Note: 1. New product: identified by Process Identification letter W or G or S. Table 19. DC Characteristics (M93Cx6-R) Note: 1. This product is under development. For more information, please contact your nearest ST sales office.
Table 20. AC Characteristics (M93Cx6, Device Grade 6, 7 or 3) Note: 1. tCHCL + tCLCH ≥ 1 / fC .
- Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
Test conditions specified in Table 12. and Table 9.
Table 21. AC Characteristics (M93Cx6-W, Device Grade 6) Note: 1. tCHCL + tCLCH ≥ 1 / fC .
- Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
Test conditions specified in Table 13. and Table 10.
Table 22. AC Characteristics (M93Cx6-W, Device Grade 7 or 3) Note: 1. tCHCL + tCLCH ≥ 1 / fC .
- Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
Test conditions specified in Table 13. and Table 10.
Table 23. AC Characteristics (M93Cx6-R) Note: 1. tCHCL + tCLCH ≥ 1 / fC .
- Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
- This product is under development. For more information, please contact your nearest ST sales office.
Test conditions specified in Table 13. and Table 11.
Figure 12. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline Note: Drawing is not to scale. Table 24. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
Figure 13. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline Note: Drawing is not to scale. Table 25. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Data
Figure 14. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Note: 1. Drawing is not to scale.
- The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS . It must not be allowed to be connected to
any other voltage or signal line on the PCB, for example during the soldering process. Table 26. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Figure 15. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Note: Drawing is not to scale. Table 27. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size,
Figure 16. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline Note: Drawing is not to scale. Table 28. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
Table 29. Ordering Information Scheme tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.
- Used only for Device Grade 3.
are also marked on the inner box label. 6 = Industrial temperature range, –40 to 85 °C. 3 = Device tested with High Reliability Certified Flow(1).
M93C86, M93C76, M93C66, M93C56, M93C46
REVISION HISTORY
Table 30. Document Revision History Document reformatted, and reworded, using the new template. Temperature range 1 removed. MLP package added. Absolute Maximum Ratings for VIO(min) and VCC (min) changed. information added. Turned-die package option removed. Product list summary added. Tables 20 and 21. Clock rate added to FEATURES SUMMARY . “Q = open” added to ICC Test conditions in DC Characteristics Tables 15, 16, 17, 18 and 19. POWER AND STANDBY POWER MODES . INITIAL DELIVERY STATE added.
M93C86, M93C76, M93C66, M93C56, M93C46 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America