M93S66 STMICROELECTRONICS | Alldatasheet
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Figure 1. Packages
M93S66, M93S56, M93S46 An internal Power-on Data Protection mechanism in the M93Sx6 inhibits the device when the supply is too low. POWER-ON DATA PROTECTION To prevent data corruption and inadvertent write operations during power-up, a Power-On Reset (POR) circuit resets all internal programming cir- cuitry, and sets the device in the Write Disable mode. – At Power-up and Power-down, the device must not be selected (that is, Chip Select Input (S) must be driven Low) until the supply voltage reaches the operating value V CC specified in Table 5. to Table 6.. – When V CC reaches its valid level, the device is properly reset (in the Write Disable mode) and is ready to decode and execute incoming instructions. For the M93Sx6 devices (5V range) the POR threshold voltage is around 3V. For the M93Sx6- W (3V range) and M93Sx6-R (2V range) the POR threshold voltage is around 1.5V. INSTRUCTIONS The instruction set of the M93Sx6 devices con- tains seven instructions, as summarized in Table 2. to Table 3.. Each instruction consists of the fol- lowing parts, as shown in Figure 4.: ■ Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock (C) being held Low. ■ A start bit, which is the first ‘1’ read on Serial Data Input (D) during the rising edge of Serial Clock (C). ■ Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock (C). (Some instructions also use the first two bits of the address to define the op-code). ■ The address bits of the byte or word that is to be accessed. For the M93S46, the address is made up of 6 bits (see Table 2.). For the M93S56 and M93S66, the address is made up of 8 bits (see Table 3.). The M93Sx6 devices are fabricated in CMOS technology and are therefore able to run as slow as 0 Hz (static input signals) or as fast as the max- imum ratings specified in Table 16. to Table 19..
Table 2. Instruction Set for the M93S46 Note: 1. X = Don’t Care bit.
Table 3. Instruction Set for the M93S66, M93S56 Note: 1. X = Don’t Care bit.
- Address bit A7 is not decoded by the M93S56.
Figure 4. READ, WRITE, WEN and WDS Sequences Note: For the meanings of An, Xn, Qn and Dn, see Table 2. and Table 3..
M93S66, M93S56, M93S46 Read The Read Data from Memory (READ) instruction outputs serial data on Serial Data Output (Q). When the instruction is received, the op-code and address are decoded, and the data from the mem- ory is transferred to an output shift register. A dum- my 0 bit is output first, followed by the 16-bit word, with the most significant bit first. Output data changes are triggered by the rising edge of Serial Clock (C). The M93Sx6 automatically increments the internal address register and clocks out the next byte (or word) as long as the Chip Select In- put (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words) and a con- tinuous stream of data can be read. Write Enable and Write Disable The Write Enable (WEN) instruction enables the future execution of write instructions, and the Write Disable (WDS) instruction disables it. When power is first applied, the M93Sx6 initializes itself so that write instructions are disabled. After an Write En- able (WEN) instruction has been executed, writing remains enabled until an Write Disable (WDS) in- struction is executed, or until V CC falls below the power-on reset threshold voltage. To protect the memory contents from accidental corruption, it is advisable to issue the Write Disable (WDS) in- struction after every write cycle. The Read Data from Memory (READ) instruction is not affected by the Write Enable (WEN) or Write Disable (WDS) instructions. Write The Write Data to Memory (WRITE) instruction is composed of the Start bit plus the op-code fol- lowed by the address and the 16 data bits to be written. Write Enable (W) must be held High before and during the instruction. Input address and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C). After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. While the M93Sx6 is performing a write cycle, but after a delay (t SLSH ) before the status information becomes available, Chip Select Input (S) can be driven High to monitor the status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle is complete, and the M93Sx6 is ready to receive a new instruction. The M93Sx6 ignores any data on the bus while it is busy on a write cycle. Once the M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low. Programming is internally self-timed, so the exter- nal Serial Clock (C) may be disconnected or left running after the start of a write cycle.
Figure 5. PAWRITE and WRAL Sequence Note: For the meanings of An, Xn and Dn, please see Table 2. and Table 3..
M93S66, M93S56, M93S46 be started, and the addressed location will not be programmed. While the M93Sx6 is performing a write cycle, but after a delay (tSLSH ) before the status information becomes available, Chip Select Input (S) can be driven High to monitor the status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle is complete, and the M93Sx6 is ready to receive a new instruction. The M93Sx6 ignores any data on the bus while it is busy on a write cycle. Once the M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low. Programming is internally self-timed, so the exter- nal Serial Clock (C) may be disconnected or left running after the start of a write cycle. Write All The Write All Memory with same Data (WRAL) in- struction is valid only after the Protection Register has been cleared by executing a Protection Reg- ister Clear (PRCLEAR) instruction. The Write All Memory with same Data (WRAL) instruction simul- taneously writes the whole memory with the same data word given in the instruction. Write Enable (W) must be held High before and during the instruction. Input address and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C). After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. While the M93Sx6 is performing a write cycle, but after a delay (t SLSH ) before the status information becomes available, Chip Select Input (S) can be driven High to monitor the status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle is complete, and the M93Sx6 is ready to receive a new instruction. The M93Sx6 ignores any data on the bus while it is busy on a write cycle. Once the M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low. Programming is internally self-timed, so the exter- nal Serial Clock (C) may be disconnected or left running after the start of a write cycle.
Figure 6. PREAD, PRWRITE and PREN Sequences Note: For the meanings of An, Xn and Dn, please see Table 2. and Table 3..
Figure 7. PRCLEAR and PRDS Sequences Note: For the meanings of An, Xn and Dn, please see Table 2. and Table 3..
M93S66, M93S56, M93S46 WRITE PROTECTION AND THE PROTECTION REGISTER The Protection Register on the M93Sx6 is used to adjust the amount of memory that is to be write protected. The write protected area extends from the address given in the Protection Register, up to the top address in the M93Sx6 device. Two flag bits are used to indicate the Protection Register status: – Protection Flag: this is used to enable/disable protection of the write-protected area of the M93Sx6 memory – OTP bit: when set, this disables access to the Protection Register, and thus prevents any further modifications to the value in the Protection Register. The lower-bound memory address is written to the Protection Register using the Protection Register Write (PRWRITE) instruction. It can be read using the Protection Register Read (PRREAD) instruc- tion. The Protection Register Enable (PREN) instruc- tion must be executed before any PRCLEAR, PRWRITE or PRDS instruction, and with appropri- ate levels applied to the Protection Enable (PRE) and Write Enable (W) signals. Write-access to the Protection Register is achieved by executing the following sequence: – Execute the Write Enable (WEN) instruction – Execute the Protection Register Enable (PREN) instruction – Execute one PRWRITE, PRCLEAR or PRDS instructions, to set a new boundary address in the Protection Register, to clear the protection address (to all 1s), or permanently to freeze the value held in the Protection Register. Protection Register Read The Protection Register Read (PRREAD) instruc- tion outputs, on Serial Data Output (Q), the con- tent of the Protection Register, followed by the Protection Flag bit. The Protection Enable (PRE) signal must be driven High before and during the instruction. As with the Read Data from Memory (READ) in- struction, a dummy 0 bit is output first. Since it is not possible to distinguish between the Protection Register being cleared (all 1s) or having been writ- ten with all 1s, the user must check the Protection Flag status (and not the Protection Register con- tent) to ascertain the setting of the memory protec- tion. Protection Register Enable The Protection Register Enable (PREN) instruc- tion is used to authorize the use of instructions that modify the Protection Register (PRWRITE, PRCLEAR, PRDS). The Protection Register En- able (PREN) instruction does not modify the Pro- tection Flag bit value. Note: A Write Enable (WEN) instruction must be executed before the Protection Register Enable (PREN) instruction. Both the Protection Enable (PRE) and Write Enable (W) signals must be driv- en High during the instruction execution. Protection Register Clear The Protection Register Clear (PRCLEAR) in- struction clears the address stored in the Protec- tion Register to all 1s, so that none of the memory is write-protected by the Protection Register. How- ever, it should be noted that all the memory re- mains protected, in the normal way, using the Write Enable (WEN) and Write Disable (WDS) in- structions. The Protection Register Clear (PRCLEAR) in- struction clears the Protection Flag to 1. Both the Protection Enable (PRE) and Write Enable (W) signals must be driven High during the instruction execution. Note: A Protection Register Enable (PREN) in- struction must immediately precede the Protection Register Clear (PRCLEAR) instruction. Protection Register Write The Protection Register Write (PRWRITE) instruc- tion is used to write an address into the Protection Register. This is the address of the first word to be protected. After the Protection Register Write (PRWRITE) instruction has been executed, all memory locations equal to and above the speci- fied address are protected from writing. The Protection Flag bit is set to 0, and can be read with Protection Register Read (PRREAD) instruc- tion. Both the Protection Enable (PRE) and Write Enable (W) signals must be driven High during the instruction execution. Note: A Protection Register Enable (PREN) in- struction must immediately precede the Protection Register Write (PRWRITE) instruction, but it is not necessary to execute first a Protection Register Clear (PRCLEAR). Protection Register Disable The Protection Register Disable (PRDS) instruc- tion sets the One Time Programmable (OTP) bit. This instruction is a ONE TIME ONLY instruction which latches the Protection Register content, this content is therefore unalterable in the future. Both the Protection Enable (PRE) and Write Enable (W) signals must be driven High during the instruction execution. The OTP bit cannot be directly read, it can be checked by reading the content of the Pro- tection Register, using the Protection Register Read (PRREAD) instruction, then by writing this same value back into the Protection Register, us-
status cannot appear on Serial Data Output (Q). pears on Serial Data Output (Q). Register Disable (PRDS) instruction. Figure 8. Write Sequence with One Clock Glitch
1 Start bit
Table 4. Absolute Maximum Ratings
Table 5. Operating Conditions (M93Sx6) Table 6. Operating Conditions (M93Sx6-W) Table 7. Operating Conditions (M93Sx6-R) Table 8. AC Measurement Conditions (M93Sx6) Note: Output Hi-Z is defined as the point where data out is no longer driven. Table 9. AC Measurement Conditions (M93Sx6-W and M93Sx6-R) Note: Output Hi-Z is defined as the point where data out is no longer driven.
Figure 9. AC Testing Input Output Waveforms Table 10. Capacitance Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 1 MHz.
Table 11. DC Characteristics (M93Sx6, Device Grade 6) Note: 1. Current product: identified by Process Identification letter F or M.
- New product: identified by Process Identification letter W or G.
Table 12. DC Characteristics (M93Sx6, Device Grade 3) Note: 1. Current product: identified by Process Identification letter F or M.
- New product: identified by Process Identification letter W or G.
Table 13. DC Characteristics (M93Sx6-W, Device Grade 6) Note: 1. Current product: identified by Process Identification letter F or M.
- New product: identified by Process Identification letter W or G.
Table 14. DC Characteristics (M93Sx6-W, Device Grade 3) Note: 1. New product: identified by Process Identification letter W or G. Table 15. DC Characteristics (M93Sx6-R) Note: 1. Preliminary Data: this product is under development. For more infomation, please contact your nearest ST sales office.
Table 16. AC Characteristics (M93Sx6, Device Grade 6 or 3) Note: 1. tCHCL + tCLCH ≥ 1 / fC .
- Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
- Current product: identified by Process Identification letter F or M.
- New product: identified by Process Identification letter W or G.
Test conditions specified in Table 8. and Table 5.
Table 17. AC Characteristics (M93Sx6-W, Device Grade 6) Note: 1. tCHCL + tCLCH ≥ 1 / fC .
- Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
- Current product: identified by Process Identification letter F or M.
- New product: identified by Process Identification letter W or G.
Test conditions specified in Table 9. and Table 6.
Table 18. AC Characteristics (M93Sx6-W, Device Grade 3) Note: 1. tCHCL + tCLCH ≥ 1 / fC .
- Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
- New product: identified by Process Identification letter W or G.
Test conditions specified in Table 9. and Table 6.
Table 19. AC Characteristics (M93Sx6-R) Note: 1. tCHCL + tCLCH ≥ 1 / fC .
- Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
- Preliminary Data: this product is under development. For more infomation, please contact your nearest ST sales office.
Test conditions specified in Table 9. and Table 7.
Figure 12. Synchronous Timing (Read or Write)
Figure 13. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline Note: Drawing is not to scale. Table 20. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
Figure 14. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline Note: Drawing is not to scale. Table 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
Figure 15. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline Note: Drawing is not to scale. Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data
Figure 16. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline Note: Drawing is not to scale. Table 23. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
Table 24. Ordering Information Scheme tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.
- Available only on new products: identified by the Process Identification letter W or G.
memory content set at all 1s (FFh). Table 25. How to Identify Current and New Products by the Process Identification Letter Sales Office for Process Change Notice PCN MPG/EE/0059 (PCEE0059).
M93S66, M93S56, M93S46
REVISION HISTORY
Table 26. Document Revision History Document reformatted, and reworded, using the new template. Temperature range 1 removed. corresponding parameters adjusted). with Process Identification Letter W. 24-Nov-2003 3.0 Table of contents, and Pb-free options added. VIL(min) improved to -0.45V.
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