M89 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Table 1. Signal Names
Figure 2A. PLCC Connections PB0 PB1 PB2 PB3 PB4 PB5 GND PB6 PB7 CNTL1 CNTL2 RESET CNTL0 PA7 PA6 PA5 PA4 PA3 GND PA2 PA1 PA0 AD0 AD1 AD2 AD3 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 VCC AD7 AD6 AD5 AD4 PD2 PD1 PD0 PC7 PC6 PC5 PC4 VCC GND PC3 PC2 PC1 PC0 AI02857 Figure 2B. PQFP Connections
39 AD15
38 AD14
37 AD13
36 AD12
35 AD11
34 AD10
33 AD9
32 AD8
31 VCC
30 AD7
29 AD6
28 AD5
27 AD4
Table 2. Product Range1
- SRAM may be backed up using an external battery.
DESCRIPTION
The FLASH+PSD family of memory systems for microcontrollers (MCUs) brings In-System- Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. FLASH+PSD devices combine many of the peripheral functions found in MCU based applications. FLASH+PSD provides a glueless interface to most commonly-used ROMless MCUs. Table 2 summarizes all the devices in the M89 Family. The FLASH+PSD device includes a JTAG Serial Programming interface, to allow In-System Programming (ISP) of the entire device. This feature reduces development time, simplifies the manufacturing flow, and dramatically lowers the cost of field upgrades. Using ST’s special Fast- JTAG programming, a design can be rapidly programmed into the FLASH+PSD. The innovative FLASH+PSD family solves key problems faced by designers when managing discrete Flash memory devices, such as: – Complex address decoding – In-System (first-time) Programming (ISP) – Concurrent EEPROM or Flash memory programming (IAP). The JTAG Serial Interface block allows In-System Programming (ISP). Embedded dual-bank memories eliminates the need for an external Boot
Figure 3. FLASH+PSD Block Diagram
1 OR 2 MBIT MAIN FLASH
8 SECTORS
256 KBIT SECONDARY
4 SECTORS
16 OR 64 KBIT BATTERY
Sometimes computers try to be too clever for their own good. Take this illustration for instance. just to weight the average in this direction.
multiple functions and are user configurable. sectors that are individually selectable. sectors. Each sector is individually selectable. different address space as defined by the user. the address latching and DPLD decoding time. Table 3. The functional partitioning of the PLDs performance, and eases design entry. signals and other combinatorial logic functions. the power management features. can be configured to be open drain. signals, which are also used as inputs to the PLDs. For examples, please see the full data sheet. JTAG is also fully supported.
functional blocks of the FLASH+PSD. functional blocks based on system requirements. mode that helps reduce power consumption. the next transition on its inputs. the full data sheet for details. bit can be cleared is to erase the entire chip. Table 3. PLD I/O Table 4. JTAG SIgnals on Port C Table 5. Methods of Programming Different Functional Blocks of the FLASH+PSD
- The code, configuration, and PLD logic are
loaded using the programming procedure. contact your nearest ST Sales Office. Table 6. Ordering Information Scheme Note: 1. Available on the 4.5 to 5.5 V range, only.
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