M8438A

M8438A STMICROELECTRONICS | Alldatasheet

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STI 7) SGS-THOMSON MICROELECTRONICS M8438A SERIAL INPUT LCD DRIVER = DRIVES UP TO 32 LCD SEGMENTS = DATA TRANSFER : FIXED ENABLE MODE FOR DIP-40, ENABLE AND LATCH-MODE FOR 44PLCC = INPUTS ARE CMOS, NMOS AND TTL COMPA- TIBLE B c = CASCADABLE DIP-40 44 PLoc = REQUIRES ONLY 3 CONTROL LINES (Prastic) (Plastic Chip Carrier) = ON CHIP OSCILLATOR ORDER CODE : M8438A_ DIE 1 = CMOS TECHNOLOGY FOR WIDE SUPPLY MB438A 86 VOLTAGE RANGE MB438A, C5 = — 40 TO 85 °C TEMPERATURE RANGE PIN CONNECTIONS Pa ’ ws) seo scons mp seor sec 204s wb vs sends xb 00 seo ned? xpos sec mda ap secs ston ab sees seo nfo nb ose seczedn wh ae DESCRIPTION Sec ofes mb scos The M8438A isa CMOS integrated circuit that drives. songs apstcre an LCD display, usually under microprocessor stone Shae control. The part acts as a smart peripheral that secondo nb ston drives up to 32 LCD segments. It needs only three sto dro np secu control lines due to its serial input construction. It Tee latches the data to be displayed and relieves the microprocessor from the task of generating the re- ecncaseect quired waveforms. eggeergeiie The M8438A can drive any standard or custom pa- a Aer a ralle| drive LCD whether it be field effect or dynamic sod Sp cs scattering. Several drivers can be cascaded, if more onde Bact than 32 segments are to be driven. The AC frequen- wen pases cy of the LCD waveforms can be supplied by the song pS user or can be generated by attaching a capacitor med opsee to the OSC input which determines the frequency of sends sptce an internal oscillator. ede een P The M8438A is available in DIE form and assem- Wey bied in 40 pin dual-in line plastic or 44 PLCC SRRRRRES Ese packages. September 1988 v7 705

O _ 9 ose GENERATOR BP 32 SEGMENT OUTPUTS > SEG. g 6 32 SEGMENT DRIVERS

32 LATCHES

~ ane 010 te STATIC SHIFT REG. O 00 fo $ 8307 OSC + Oscillator (capacitor or drive signal) 00: Serial data output EL Enable Latch control input BP = Backplane output MS = Mode select input (not availabe in 40 Pin DIL) SEG | Segment output signal 01: Serial data input i SS, —— 706

[_symboi [Parameter | Vatue | Unit | | Po | Power Dissipation | 850, ‘Stresses in excess of those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of tho cevce at these or anyother condone in ices of those indicated nthe operational secons ofthis specication rot impled. Exposure absolze maximum raling condone for extended periods may affect vice rely. ELECTRICAL CHARACTERISTICS (Tam) = 25 °C and Vpp = 5 V unless otherwise noted) [Symboi[ Parameter | Test conditions | Min. | Max. | Unit | STATIC ELECTRICAL CHARACTERISTICS [Yoo [Suopyvorge 8 tT [too _[ Supply Curent | Oscitator Ske || 60 | A_| | ta__| Quiescent Curent VoostoV Tt A Input High Level po V0 | oo |v | Input Low Level crock Po evo |v [Cm [tat cure }e. [os fo Input Capacitance _ bof Vin _| Input High Level Driven Mode 8Vol | v_ | Input Low Level ose | Orven Mode | too | Vv |__| input Current [ Driven Mode | | et | | | Rion | Segment Output Impedance [m= towA | tok | i Impedance Output Offset Voltage C= 250 pF between Each Pei | _ a SEG Output and BP ion | Data Output Impecance w=100nd Ts ko DYNAMIC ELECTRICAL CHARACTERISTICS: |_trn_| Transition Time Osc | Driven Mode | 500 | ns | [ten | Data Setup Time Fig tang2 | ts fs [two [DataHoid time Fig tanga | 50 fs [ tee [etsetuptime gt 00 Ps | te [etHogtime ot 00 Ts [ twe [et Putco width 2 ts Ts [ toe [Obockioettime Fg 2 ts |_| | toa | 00 Propagation Delay | Fig. 2: =550F || 500 [ns _| [+ [Clock Rate [ Yoo = 10 60 % Duty Cycle; | oc | 15 | mez | G57 S&S:THOMsoN 37 ATW, BYE ratnociscrmomcs age

LCD-AC-Generator ENABLE MODE Fig. 3 shows a timing diagram 0 This block generates a 50 % duty cycle signalforthe _the enable mode. Data is serially shifted in and ou backplane output. The circuit can be usedin two di. of the shift register on the negative transition of the ferent modes : oscillator or driven clock. Serial entry into the shift register is permittec : when the enable/latch control EL is high. When El OSCILLATOR MODE : In this mode the backplane —_ ig iow it causes the shift register clock to be inhibi frequency is determined by the internal RC oscilla- ted and the content of the shift register to be loadec tor together with an 8-stage frequency divider. For _into the latches that control the segment drivers. generating the backplane output signal of 50 % du- ‘ ty cycle the oscillator frequency is divided by 256. LATCH MODE Fig. 4 shows a timing diagram of the The RC oscilator requires an external capacttor to ‘latch mode, Data is serially shifted in and out of th be connected between input OSC and Vee, A value shift register on the negative transition of the clock of 18 pF gives a backplane frequency of 80 Hz Serial entry into the shift register is permitted inde +30 % at Voo = 5 V. The variation of the backplane _-Pendently of the enablevlatch control EL. When El frequency over the entire temperature and supply _'S high it causes a parallel load of the content in the voltage range is + 80 % the EL'tne high Thon the itches are ranepare : ine hi nthe late! ranspar DRIVEN MODE : Inthis mode the signal at the back- ang only two lines, clock and data input, would ther plane output BP is in phase with an external driving be needed for data transfer. signal applied to input OSC. This mode is used to synchronize the LCD drive of twoormore cascaded + Power-on logic driver circuits. Apower on reset pulse is generated internally wher DETECTIONLOGIC The circuitis able todistinguish the supply voltage is being turned on. The genera between the conditions for oscillator or driven mode. __tion of the reset pulse is level dependent and will oc Ifthe circuit is to be in the oscillator mode, the OSC_—_cur even on a slowly rising supply voltage. The po pin has acapacitor connected tot. The oscillator will wer on reset pulse resets all shift register stages anc start as soon as the supply voltage exceed a certain the latches that control the segment drivers. There minimum value. The signal at pin OSC swings within fore all segment outputs are initially in phase wit range from 0.3 Voo to 0.7 Voo. If the circuit is to the backplane output. This causes the display to bs be in the driven mode, the OSC pinhas tobe forced blanked and no arbitrary data to show up. This to logic levels by an external source. The transition condition is maintained unti! data is shifted into the time between the logic levels must be short, so that register and loaded into the latches. the circuit does not react on the voltage level inbe- CONDITIONS FOR POWER-ON RESET FUNC tween. In the driven mode the 8-stage frequency di- TION ; The POR circuit triggers on the rising slopé vider is by-passed. of the positive supply voltage Voo. A reset pulse wil Segment outputs be generated, if conditions a) through d) are given Aogic 0 at the data input DI causes a segment out- _a) Level yy put signal to be in phase with the backplane signal Rising slope from and turns the segment off. A logic 1 causes a seg- V1 to V2 (av ment output to be in opposite phase to the backplane V1 max =0.5V signal and turns the segment on. V2 min = 3.0 V ee Microprocessor interface b) Rise time Le The circuit can o temin = 10 us (oa perate in two different data transfer H modes : Enable mode and latch mode. One of either tmax= 1s pe mode can be chosen with the mode select input MS. _¢) Rise function he An internal pull up device is provided between this The function of Vop between tt and t2 may be input and Voo. Enable mode is selected if MS is left nonlinear, but should not show a maximum and open or connected to Voo. should not exceed 0.25 Vius. Latch mode is selected if MS is connected to Vss. 4) recovery time The input MSis notavailable, ifthedeviceisas- “)FrCweY Ime sembled in the 40 pin package, and is internally Vente fixed to operate in ENABLE MODE. " “7 ‘SGS-THOMSON 708