M76DW52003TA STMICROELECTRONICS | Alldatasheet
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Technical content
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Figure 1. Package
conjunction with the M29DW323D datasheet. plied with all the bits erased (set to ‘1’). Figure 2. Logic Diagram Table 1. Signal Names
Figure 3. LFBGA Connections (Top view through package)
M76DW52003TA, M76DW52003BA SIGNAL DESCRIPTION See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A17). Addresses A0-A17 are common inputs for the Flash and the SRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they con- trol the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable (EF) and Write Enable (W) signals, while the SRAM is accessed through two Chip Enable signals (E1S and E2S) and the Write Enable signal (W). Address Inputs (A18-A20). Addresses A18-A20 are inputs for the Flash component only. The Flash memory is accessed through the Chip En- able (EF) and Write Enable (W) signals Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ8-DQ14). The Data I/O outputs the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A– 1). When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the ad- dressed Word, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to in- clude this pin when BYTE is Low except when stated explicitly otherwise. Flash Chip Enable (EF). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip En- able is at VILand RPF is at VIH the device is in ac- tive mode. When Chip Enable is at VIH the memory is deselected, the outputs are high imped- ance and the power consumption is reduced to the stand-by level. Output Enable (G). The Output Enable, G, con- trols the Bus Read operation of the device. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the device. VPP/Write Protect (VPP/WP). The VPP/Write Protect pin provides two functions. The VPP func- tion allows the Flash memory to use an external high voltage power supply to reduce the time re- quired for Program operations. This is achieved by bypassing the unlock cycles and/or using the Double Word or Quadruple Byte Program com- mands. The Write Protect function provides a hardware method of protecting the two outermost boot blocks in the Flash memory. When VPP/Write Protect is Low, VIL, the memory protects the two outermost boot blocks; Program and Erase operations in these blocks are ignored while VPP/Write Protect is Low, even when RPF is at VID. When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status of the two outermost boot blocks. Program and Erase oper- ations can now modify the data in these blocks un- less the blocks are protected using Block Protection. When VPP/Write Protect is raised to VPP the mem- ory automatically enters the Unlock Bypass mode. When VPP/Write Protect returns to VIH or VIL nor- mal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the M29DW323D datasheet for more details. Reset/Block Temporary Unprotect (RPF). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. Note that if VPP/WP is at VIL, then the two outer- most boot blocks will remain protected even if RPF is at VID. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the M29DW323D datasheet for more details. Holding RPF at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the Flash memory is performing a Program or Erase operation. During Program or Erase op- erations Ready/Busy is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode.
M76DW52003TA, M76DW52003BA After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy be- comes high-impedance. Byte/Word Organization Select (BYTE). The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus modes of the Flash memory. When Byte/Word Organization Se- lect is Low, VIL, the Flash memory is in x8 mode, when it is High, VIH, the Flash memory is in x16 mode. SRAM Chip Enable (E1S, E2S). The Chip En- able inputs activate the SRAM memory control logic, input buffers and decoders. E1S at VIH or E2S at VIL deselects the memory and reduces the power consumption to the standby level. E1S and E2S can also be used to control writing to the SRAM memory array, while W remains at VIL. It is not allowed to set EF at VIL, E1S at VIL and E2S at VIH at the same time. SRAM Upper Byte Enable (UBS). The Upper Byte Enable enables the upper bytes for SRAM (DQ8-DQ15). UBS is active low. SRAM Lower Byte Enable (LBS). The Lower Byte Enable enables the lower bytes for SRAM (DQ0-DQ7). LBS is active low. VCCF Supply Voltage (2.7V to 3.3V). VCCF pro- vides the power supply to the internal core of the Flash Memory device. It is the main power supply for all operations (Read, Program and Erase). VCCS Supply Voltage (2.7V to 3.3V). VCCS pro- vides the power supply for the SRAM control pins. VSS Ground. VSS is the ground reference for all voltage measurements in the Flash and SRAM chips.
Figure 4. Functional Block Diagram
32 Mbit (x16)
4 Mbit (x16)
Table 2. Main Operation Modes, BYTE = VIH(2) Note: 1. X = Don’t Care = VIL or VIH.
- This table is also valid when BYTE = VIL, with the only difference that DQ15-DQ8 are always high impedance in this case.
- For the Block Protect and Unprotect features, see the M29DW323D datasheet. Only the In-System Technique is available in the
- The Read Manufacturer Code and Read Device Code operations are not available in the stacked product (see the ““Bus Opera-
STMicroelectronics web site, www.st.com. same as the Flash voltage supply. Figure 5. SRAM Logic Diagram
M76DW52003TA, M76DW52003BA SRAM OPERATIONS There are five standard operations that control the SRAM component. These are Bus Read, Bus Write, Standby/Power-down, Data Retention and Output Disable. A summary is shown in Table 2, Main Operation Modes Read. Read operations are used to output the contents of the SRAM Array. The SRAM is in Read mode whenever Write Enable, WS, is at VIH, Out- put Enable, GS, is at VIL, Chip Enable, E1S, is at VIL, Chip Enable, E2S, is at VIH, and Byte Enable inputs, UBS and LBS are at VIL. Valid data will be available on the output pins after a time of tAVQV after the last stable address. If the Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tE1LQV, tE2HQV, or tGLQV) rath- er than the address. Data out may be indetermi- nate at tE1LQX, tE2HQX and tGLQX, but data lines will always be valid at tAVQV (see Table 8, Table 8, Figures 8 and 9, SRAM Read AC Characteristics). Write. Write operations are used to write data to the SRAM. The SRAM is in Write mode whenever W and E1S are at VIL, and E2S is at VIH. Either the Chip Enable inputs, E1S and E2S, or the Write En- able input, WS, must be deasserted during ad- dress transitions for subsequent write cycles. A Write operation is initiated when E1S is at VIL, E2S is at VIH and W is at VIL. The data is latched on the falling edge of E1S, the rising edge of E2S or the falling edge of WS, whichever occurs last. The Write cycle is terminated on the rising edge of E1S, the rising edge of W or the falling edge of E2S, whichever occurs first. If the Output is enabled (E1S=VIL, E2S=VIH and GS=VIL), then W will return the outputs to high im- pedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of op- eration. The Data input must be valid for tDVWH be- fore the rising edge of Write Enable, for tDVE1H before the rising edge of E1S or for tDVE2L before the falling edge of E2S, whichever occurs first, and remain valid for tWHDX, tE1HAX or tE2LAX (see Table 9, SRAM Write AC Characteristics, Figures 11, 12, 13 and 14). Standby/Power-Down. The SRAM component has a chip enabled power-down feature which in- vokes an automatic standby mode (see Table 8, SRAM Read AC Characteristics, Figure 10, SRAM Standby AC Waveforms). The SRAM is in Standby mode whenever either Chip Enable is deasserted, E1S at VIH or E2S at VIL. It is also possible when UBS and LBS are at VIH. Data Retention. The SRAM data retention per- formance as VCCS goes down to VDR are de- scribed in Table 10, SRAM Low VCCS Data Retention Characteristic, and Figure 15, SRAM Low VCCS Data Retention AC Waveforms, E1S or UBS / LBS Controlled. In E1S controlled data reten- tion mode, the minimum standby current mode is entered when E1S ≥VCCS – 0.2V and E2S ≤0.2V or E2S ≥VCCS – 0.2V. In E2S controlled data re- tention mode, minimum standby current mode is entered when E2S ≤0.2V. Output Disable. The data outputs are high im- pedance when the Output Enable, GS, is at VIH with Write Enable, WS, at VIH.
Table 3. Absolute Maximum Ratings
Table 6. Flash DC Characteristics Note: 1. Sampled only, not 100% tested.
- In Dual operations the Supply Current will be the sum of ICC1(read) and ICC3 (program/erase).
Table 7. SRAM DC Characteristics Note: 1. Sampled only, not 100% tested.
Table 8. SRAM Read AC Characteristics Note: 1. Sampled only. Not 100% tested.
Figure 11. SRAM Write AC Waveforms, W Controlled impedance). If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance.
- The I/O pins are in output mode and input signals must not be applied.
Figure 12. SRAM Write AC Waveforms, E1S Controlled impedance). If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance.
- If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance.
- The I/O pins are in output mode and input signals must not be applied.
Table 9. SRAM Write AC Characteristics
Figure 15. SRAM Low VCCS Data Retention AC Waveforms, E1S or UBS / LBS Controlled Table 10. SRAM Low VCCS Data Retention Characteristic
- Sampled only. Not 100% tested.
Figure 16. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline Note: Drawing is not to scale.
Table 11. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Package Mechanical Data
Table 12. Ordering Information Scheme Devices are shipped from the factory with the memory content bits erased to ’1’. please contact the STMicroelectronics Sales Office nearest to you.
M76DW52003TA, M76DW52003BA
REVISION HISTORY
Table 13. Document Revision History
M76DW52003TA, M76DW52003BA Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States