M74HC125

MM74HC125 FAIRCHILD | Alldatasheet

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■ Typical propagation delay: 13 ns ■ Wide operating voltage range: 2–6V ■ Low input current: 1 µA maximum ■ Low quiescent current: 80 µA maximum (74HC) ■ Fanout of 15 LS-TTL loads Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A.) Connection Diagrams Pin Assignments for DIP , SOIC, SOP and TSSOP Top View (MM74HC125) Top View (MM74HC126) Truth Tables Order Number Package Number Package Description MM74HC125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body MM74HC125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC125N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide MM74HC126M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body MM74HC126SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC126MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC126N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Inputs Output AC Y HL H LL L XH Z Inputs Output AC Y HH H LH L XL Z

www.fairchildsemi.com 2 MM74HC125/MM74HC126 Absolute Maximum Ratings(Note 1) (Note 2) Recommended Operating Conditions Note 1: Absolute Maximum Ratings are those values beyond which dam- age to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/ °C from 65°C to 85°C. Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH , and VOL ) occur for HC at 4.5V. Thus the 4.5V values should be used when (IIN, ICC , and IOZ ) occur for CMOS at the higher voltage and so the 6.0V values should be used. Supply Voltage (VCC ) −0.5 to +7.0V DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT ) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK ) ±20 mA DC Output Current, per pin (IOUT ) ±35 mA DC V CC or GND Current, per pin (ICC ) ±70 mA Storage Temperature Range (TSTG ) −65°C to +150°C Power Dissipation (PD ) (Note 3) 600 mW S.O. Package only 500 mW Lead Temperature (T (Soldering 10 seconds) 260 °C Min Max Units Supply Voltage (VCC )2 6 V DC Input or Output Voltage 0 V CC V (VIN, VOUT ) Operating Temperature Range (TA) −40 +85 °C Input Rise or Fall Times (tr, tf) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Symbol Parameter Conditions VCC TA = 25°CT A = −40 to 85°CT A = −40 to 125°C Units Typ Guaranteed Limits VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V Input Voltage 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V VIN = VIH or VIL VOL Maximum LOW Level V IN = VIH or VIL 2.0V 0 0.1 0.1 0.1 V Output Voltage |I OUT | ≤ 20 µA 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V VIN = VIH or VIL IOZ Maximum 3-STATE Output V IN = VIH or VIL 6.0V ±0.5 ±5 ±10 µA Leakage Current V OUT = VCC or GND C n = Disabled IIN Maximum Input Current V IN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent V IN = VCC or GND 6.0V 8.0 80 160 µA Supply Current I OUT = 0 µA

3 www.fairchildsemi.com MM74HC125/MM74HC126 VCC = 5V, TA = 25°C, CL = 45 pF, tr = tf = 6 ns VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Note 5: C PD determines the no load dynamic power consumption, PD = CPD VCC 2f + ICC VCC , and the no load dynamic current consumption, IS = CPD VCC f + ICC . Symbol Parameter Conditions Typ Guaranteed Limit Units tPHL , tPLH Maximum 13 18 ns Propagation Delay Time tPZH Maximum R L = 1 kΩ 13 25 ns Output Enable Time to HIGH Level tPHZ Maximum R L = 1 kΩ 17 25 ns Output Disable Time from HIGH Level C L = 5 pF tPZL Maximum R L = 1 kΩ 18 25 ns Output Enable Time to LOW Level tPLZ Maximum R L = 1 kΩ 13 25 ns Output Disable Time from LOW Level C L = 5 pF Symbol Parameter Conditions VCC TA = 25°CT A = −40 to 85°CT A = −40 to 125°C Units Typ Guaranteed Limits tPHL , tPLH Maximum Propagation 2.0V 40 100 125 150 ns Delay Time 4.5V 14 20 25 30 ns 6.0V 12 17 21 25 ns t PLH , tPHL Maximum Propagation C L = 150 pF 2.0V 35 130 163 195 ns Delay Time 4.5V 14 26 33 39 ns 6.0V 12 22 28 39 ns tPZH , tPZL Maximum Output R L = 1 kΩ 2.0V 25 125 156 188 ns Enable Time 4.5V 14 25 31 38 ns 6.0V 12 21 26 31 ns tPHZ , tPLZ Maximum Output R L = 1 kΩ 2.0V 25 125 156 188 ns Disable Time 4.5V 14 25 31 38 ns 6.0V 12 21 26 31 ns tPZL , tPZH Maximum Output C L = 150 pF 2.0V 35 140 175 210 ns Enable Time R L = 1 kΩ 4.5V 15 28 35 42 ns 6.0V 13 24 30 36 ns tTLH , tTHL Maximum Output C L = 50 pF 2.0V 30 60 75 90 ns Rise and Fall Time 4.5V 7 12 15 18 ns 6.0V 6 10 13 15 ns C IN Input Capacitance 5 10 10 10 pF C OUT Output Capacitance Outputs 15 20 20 20 pF C PD Power Dissipation (per gate) Capacitance (Note 5) Enabled 45 pF Disabled 6 pF

www.fairchildsemi.com 4 MM74HC125/MM74HC126 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body Package Number M14A 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D

5 www.fairchildsemi.com MM74HC125/MM74HC126 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74HC125/MM74HC126 3-STATE Quad Buffers LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A