M74HC112_01 STMICROELECTRONICS | Alldatasheet

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■ HIGH SPEED : fMAX = 79MHz (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: I CC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.) ■ SYMMETRICAL OUTPUT IMPEDANCE: OH | = IOL = 4mA (MIN) ■ BALANCED PROPAGATION DELAYS: t PLH ≅ tPHL ■ WIDE OPERATING VOLTAGE RANGE: V CC (OPR) = 2V to 6V ■ PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 112

DESCRIPTION

The M74HC112 is an high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated with silicon gate C 2MOS technology. The M74HC112 dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs for each flip-flop. When the clock goes high, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is high and the bistable will function as shown in the truth table. Input data is transferred to the input on the negative going edge of the clock pulse. All inputs are equipped with protection circuits against static discharge and transient excess voltage. M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R DIP M74HC112B1R SOP M74HC112M1R M74HC112RM13TR TSSOP M74HC112TTR TSSOPDIP SOP

INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION TRUTH TABLE X : Don’t Care LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays PIN No SYMBOL NAME AND FUNCTION 1, 13 1CK , 2CK Clock Input(HIGH to LOW edge triggered) 2, 12 1K, 2K Data Inputs: Flip-Flop 1 and 2 3, 11 1J, 2J Data Inputs: Flip-Flop 1 and 2 4, 10 1PR , 2PR Set Inputs 5, 9 1Q, 2Q True Flip-Flop Outputs 6, 7 1Q , 2Q Complement Flip-Flop Outputs 15, 14 1CLR , 2CLR Reset Inputs

8 GND Ground (0V)

16 Vcc Positive Supply Voltage

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit VCC Supply Voltage -0.5 to +7 V VI DC Input Voltage -0.5 to V CC + 0.5 V VO DC Output Voltage -0.5 to V CC + 0.5 V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ICC or IGND DC V CC or Ground Current ± 50 mA PD Power Dissipation 500(*) mW Tstg Storage Temperature -65 to +150 °C TL Lead Temperature (10 sec) 300 °C Symbol Parameter Value Unit VCC Supply Voltage 2 to 6 V VI Input Voltage 0 to V CC V VO Output Voltage 0 to V CC V Top Operating Temperature -55 to 125 °C tr, tf Input Rise and Fall Time V CC = 2.0V 0 to 1000 ns VCC = 4.5V 0 to 500 ns VCC = 6.0V 0 to 400 ns

(V) TA = 25°C -40 to 85°C -55 to 125°C VIH High Level Input Voltage 2.0 1.5 1.5 1.5 V4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 VIL Low Level Input Voltage 2.0 0.5 0.5 0.5 V4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 VOH High Level Output Voltage V VOL Low Level Output Voltage V II Input Leakage Current 6.0 VI = VCC or GND ± 0.1 ± 1 ± 1 µA ICC Quiescent Supply Current 6.0 VI = VCC or GND 22 0 4 0 µA

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC /2 (per FLIP/ FLOP) Symbol Parameter Test Condition Value UnitVCC (V) TA = 25°C -40 to 85°C -55 to 125°C tTLH tTHL Output Transition Time 2.0 30 75 95 110 ns4 . 5 8 1 51 92 2 6 . 0 7 1 31 61 9 tPLH tPHL Propagation Delay Time (CK - Q, Q) 2.0 52 125 155 190 ns4.5 16 25 31 38 6.0 14 21 26 32 tPLH tPHL Propagation Delay Time (CLR, PR - Q, Q) 2.0 68 135 170 205 ns4.5 17 27 34 41 6.0 14 23 29 35 fMAX Maximum Clock Frequency 2.0 8 16 6.4 5.4 MHz4.5 40 68 32 27 6.0 47 79 38 32 tW(H) tW(L) Minimum Pulse Width (CLOCK) 2.0 20 75 95 110 ns4 . 5 5 1 51 92 2 6 . 0 4 1 31 61 9 tW(L) Minimum Pulse Width (CLR, PR) 2.0 20 75 95 110 ns4 . 5 5 1 51 92 2 6 . 0 4 1 31 61 9 ts Minimum Set-up Time 2.0 28 75 95 110 ns4 . 5 7 1 51 92 2 6 . 0 6 1 31 61 9 th Minimum Hold Time 2.0 0 0 0 ns4.5 0 0 0 6.0 0 0 0 tREM Minimum Removal Time (CLR, PR) 2.0 24 50 60 70 ns4 . 5 4 1 01 21 4 6.0 3 9 10 12 Symbol Parameter Test Condition Value UnitVCC (V) TA = 25°C -40 to 85°C -55 to 125°C C IN Input Capacitance 5 . 0 5 1 01 01 0 p F C PD Power Dissipation Capacitance (note 5.0 33 pF

C L = 50pF or equivalent (includes jig and probe capacitance) R T = ZOUT of pulse generator (typically 50Ω ) WAVEFORM 1: PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (CK), SETUP AND HOLD TIME (J to CK) (f=1MHz; 50% duty cycle)

WAVEFORM 2 : PROPAGATIONS DELAY TIME, MINIMUM PULSE WIDTH (CLR , PR) (f=1MHz; 50% duty cycle)

WAVEFORM 3 : MINIMUM REMOVAL TIME (CLR to CK) (f=1MHz; 50% duty cycle) WAVEFORM 4 : MINIMUM REMOVAL TIME (PR to CK) (f=1MHz; 50% duty cycle)

DIM. mm. inch a1 0.51 0.020 B 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L 3.3 0.130 Z 1.27 0.050 Plastic DIP-16 (0.25) MECHANICAL DATA P001C

DIM. mm. inch A 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M 0.62 0.024 S8 ° ( m a x . ) SO-16 MECHANICAL DATA PO13H

DIM. mm. inch A 1.2 0.047 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 e 0.65 BSC 0.0256 BSC K0 ° 8 °0 ° 8 ° TSSOP16 MECHANICAL DATA c Eb A2A D PIN 1 IDENTIFICATION LKe 0080338D

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