M54HC109 STMICROELECTRONICS | Alldatasheet

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DUAL J-K FLIP FLOP WITH PRESET AND CLEAR B1R (Plastic Package) ORDER CODES : M54HC109F1R M74HC109M1R M74HC109B1R M74HC109C1R F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) PIN CONNECTIONS (top view) NC = No Internal Connecti on INPUT AND OUTPUT EQUIVALENT CIRCUIT

DESCRIPTION

.HIGH SPEED fMAX = 63 MHz (TYP.) AT VCC =5V .LOW POWER DISSIPATION ICC =2 µA (MAX.) AT TA =2 5°C .HIGH NOISE IMMUNITY VNIH =V NIL =2 8%V CC (MIN.) .OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

.SYMMETRICAL OUTPUT IMPEDANCE IOH  =IOL = 4 mA (MIN.) .BALANCED PROPAGATION DELAYS tPLH =tPHL .WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V .PIN AND FUNCTION COMPATIBLE WITH 54/74LS109 The M54/74HC109 is a high speed CMOS DUAL J- K FLIP-FLOP WITH PRESET AND CLEAR fabri- cated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. In accordance with the logic level on the J and K input is device changes state on positive going tran- sitions of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished bya low logic level on the corresponding input. All inputs are equipped with protection circuits against static discharge and transient excess volt- age.

PIN No SYMBOL NAME AND FUNCTION 1, 15 1CLR, 2CLR Asynchronous Reset Direct Input Syncronous Inputs; Flip-flops 1 and 2 4, 12 1CK, 2CK Clock Input 5, 11 1PR, 2PR Asynchronous Set Direct Input (Active LOW) 6, 10 1Q, 2Q True Flip-flop Outputs 7, 9 1Q, 2Q Complement Flip-flop Outputs

8 GND Ground (0V)

16 V CC Positive Supply Voltage

X = DON’T CARE M54/M74HC109

RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit VCC Supply Voltage 2 to 6 V VI Input Voltage 0 to V CC V VO Output Voltage 0 to V CC V Top Operating Temperature:M54HC Series M74HC Series -55 to +125 -40 to +85 oC oC tr,tf Input Rise and Fall Time V CC = 2 V 0 to 1000 ns VCC = 4.5 V 0 to 500 VCC = 6 V 0 to 400 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCC Supply Voltage -0.5 to +7 V VI DC Input Voltage -0.5 to V CC + 0.5 V VO DC Output Voltage -0.5 to V CC + 0.5 V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Source Sink Current Per Output Pin ± 25 mA ICC or IGND DC V CC or Ground Current ± 50 mA P D Power Dissipation 500 (*) mW Tstg Storage Temperature -65 to +150 oC TL Lead Temperature (10 sec) 300 oC Absolute MaximumRatings are those values beyond whichdamage tothe device may occu r. Functional operation under these condition isnotimplied. (*) 500 mW:≅ 65 oC derate to 300 mW by 10mW/oC: 65oCt o 8 5oC M54/M74HC109

(V) TA =2 5oC 54HC and 74HC -40 to 85oC 74HC -55 to 125oC 54HC VIH High Level Input Voltage 2.0 1.5 1.5 1.5 V4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 V IL Low Level Input Voltage 2.0 0.5 0.5 0.5 V4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 V OH High Level Output Voltage

2.0 VI =

IO =-20µA 1.9 2.0 1.9 1.9 V VOL Low Level Output Voltage IO =2 0µA 0.0 0.1 0.1 0.1 V II Input Leakage Current 6.0 VI =V CC or GND ±0.1 ±1 ±1 µA ICC Quiescent Supply Current

6.0 V I =V CC or GND 2 20 40 µA

AC ELECTRICAL CHARACTERISTICS (CL =5 0p F ,I n p u ttr =t f =6n s ) Symbol Parameter Test Conditions Value UnitVCC (V) TA =2 5oC 54HC and 74HC -40 to 85oC 74HC -55 to 125oC 54HC tTLH tTHL Output Transition Time 2.0 30 75 95 110 ns4 . 5 8 1 51 92 2 6 . 0 7 1 31 61 9 tPLH tPHL Propagation Delay Time (CK-Q, Q) 2.0 50 150 190 225 ns4.5 16 30 38 45 6.0 13 26 32 38 t PLH tPHL Propagation Delay Time (CLR, PR-Q, Q) 2.0 50 150 190 225 ns4.5 16 30 38 45 6.0 13 26 32 38 f MAX Maximum Clock Frequency 2.0 6.2 17 5 4.2 MHz4.5 31 59 25 21 6.0 37 67 30 25 tW(H) tW(L) Minimum Pulse Width (CLOCK) 2.0 15 75 95 110 ns4 . 5 6 1 51 92 2 6 . 0 6 1 31 61 9 tW(L) Minimum Pulse Width (CLR, PR) 2.0 15 75 95 110 ns4 . 5 6 1 51 92 2 6 . 0 6 1 31 61 9 ts Minimum Set-up Time 2.0 17 75 95 110 ns4 . 5 5 1 51 92 2 6 . 0 4 1 31 61 9 th Minimum Hold Time 2.0 0 0 0 ns4.5 0 0 0 6.0 0 0 0 tREM Minimum Removal Time (CLR, PR) 2.0 13 50 65 75 ns4 . 5 4 1 01 31 5 6.0 3 9 11 13 C IN Input Capacitance 5 10 10 10 pF C PD (*) Power Dissipation Capacitance 41 pF (*) CPD is defined as the value of the IC’s internal equivalent capac itance which is calculated from the operating current consump tion without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC (opr) = CPD •VCC •fIN +ICC /2 (per Flip-flop) M54/M74HC109

SWITCHING CHARACTERISTICS TEST WAVEFORM TEST CIRCUIT ICC (Opr.) INPUT WAVEFORMIS THE SAME AS THAT IN CASE OF SWITCHINGCHARACTERISTICS TEST. M54/M74HC109

Plastic DIP16 (0.25) MECHANICAL DATA DIM. mm inch a1 0.51 0.020 B 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L 3.3 0.130 Z 1.27 0.050 P001C M54/M74HC109

Ceramic DIP16/1 MECHANICAL DATA DIM. mm inch A 20 0.787 B 7 0.276 D 3.3 0.130 E 0.38 0.015 e3 17.78 0.700 F 2.29 2.79 0.090 0.110 G 0.4 0.55 0.016 0.022 H 1.17 1.52 0.046 0.060 L 0.22 0.31 0.009 0.012 M 0.51 1.27 0.020 0.050 N 10.3 0.406 P 7.8 8.05 0.307 0.317 Q 5.08 0.200 P053D M54/M74HC109

SO16 (Narrow) MECHANICAL DATA DIM. mm inch A 1.75 0.068 a1 0.1 0.2 0.004 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45 ° (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M 0.62 0.024 S8 ° (max.) P013H M54/M74HC109

DIM. mm inch A 9.78 10.03 0.385 0.395 B 8.89 9.04 0.350 0.356 D 4.2 4.57 0.165 0.180 d1 2.54 0.100 d2 0.56 0.022 E 7.37 8.38 0.290 0.330 e 1.27 0.050 e3 5.08 0.200 F 0.38 0.015 G 0.101 0.004 M 1.27 0.050 M1 1.14 0.045 P027A M54/M74HC109

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