M74DW66500B STMICROELECTRONICS | Alldatasheet
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Technical content
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Figure 1. Package
Figure 7. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline15
plied with all the bits erased (set to ‘1’). Figure 2. Logic Diagram Table 1. Signal Names
Figure 3. LFBGA Connections (Top view through package)
See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A21).Address lines A0-A20 are common inputs for the Flash Memory and PSRAM components. Address line A21 is an input that is common for the two Flash Memory compo- nents. The Address Inputs select the cells in the memory array to access during Bus Read opera- tions. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. The Flash memory is ac- cessed through the Chip Enable ( EF) and Write Enable (W) signals, while the PSRAM is accessed through two Chip Enable signals (E1S and E2S) and the Write Enable signal (W). Data Inputs/Outputs (DQ0-DQ7).The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ8-DQ14).The Data I/O outputs the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A– 1).When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the ad- dressed Word, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to in- clude this pin when BYTE is Low except when stated explicitly otherwise. Flash-1 Chip Enable (EF1) and Flash-2 Chip En- able (EF2). The Chip Enable input activates the memory to which it is attached, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V IH, all other pins are ig- nored. Output Enable (G).The Output Enable, G, con- trols the Bus Read operation of the Flash Memory and PSRAM components. Write Enable (W).The Write Enable, W, controls the Bus Write operation of the Flash Memory and PSRAM components. VPP/Write Protect (VPP /WP ). The V PP /Write Protect pin provides two functions. The VPP func- tion allows the Flash memory to use an external high voltage power supply to reduce the time re- quired for Program operations. This is achieved by bypassing the unlock cycles and/or using the multiple Word (2 or 4 at-a-time) or multiple Byte Program (2, 4 or 8 at-a-time) commands. The Write Protect function provides a hardware meth- od of protecting the four outermost boot blocks (two at the top, and two at the bottom of the ad- dress space). When V PP /Write Protect is Low, VIL, the memory protects the four outermost boot blocks; Program and Erase operations in these blocks are ignored while VPP /Write Protect is Low, even when RPF is at VID. When V PP /Write Protect is High, VIH, the memory reverts to the previous protection status of the four outermost boot blocks (two at the top, and two at the bottom of the address space). Program and Erase operations can now modify the data in these blocks unless the blocks are protected using Block Protection. When V PP /Write Protect is raised to VPP the mem- ory automatically enters the Unlock Bypass mode. When V PP /Write Protect returns to VIH or VIL nor- mal operation resumes. During Unlock Bypass Program operations the memory draws I PP from the pin to supply the programming circuits. See the description of the Unlock Bypass command in the Command Interface section. The transitions from V IH to VPP and from VPP to VIH must be slower than tVHVPP . See the M29DW640D datasheet for more details. Never raise VPP /Write Protect to VPP from any mode except Read mode, otherwise the memory may be left in an indeterminate state. The V PP /Write Protect pin must not be left floating or unconnected or the device may become unreli- able. A 0.1µF capacitor should be connected be- tween the V PP /Write Protect pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program, I PP . Reset/Block Temporary Unprotect (RPF).The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. Note that if V PP /WP is at VIL, then the two outer- most boot blocks will remain protected even if RPF is at VID. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX . After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or
tRHEL , whichever occurs last. See the M29DW640D datasheet for more details. Holding RPF at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH . Ready/Busy Output (RB).The Ready/Busy pin is an open-drain output that can be used to identify when the Flash memory is performing a Program or Erase operation. During Program or Erase op- erations Ready/Busy is Low, V OL . Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy be- comes high-impedance. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Byte/Word Organization Select (BYTE ).The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus modes of the Flash memory. When Byte/Word Organization Se- lect is Low, V IL, the Flash memory is in x8 mode, when it is High, VIH, the Flash memory is in x16 mode. PSRAM Chip Enable inputs (E1P, E2P). The Chip Enable inputs activate the PSRAM control logic, input buffers and decoders. E1P at VIH with E2P at VIH deselects the memory, reducing the power consumption to the standby level, whereas E2P at VIL deselects the memory and reduces the power consumption to the Power-down level, re- gardless of the level of E1P. E1P and E2P can also be used to control writing to the PSRAM memory array, while W P remains at VIL. It is not allowed to set EF1 or EF2 at VIL, E1P at VIL and E2P at VIH at the same time. PSRAM Upper Byte Enable (UBP). The Upper Byte Enable input enables the upper byte for PSRAM (DQ8-DQ15). UB P is active low. PSRAM Lower Byte Enable (LBP). The Lower Byte Enable input enables the lower byte for PSRAM (DQ0-DQ7). LB P is active low. VCCF Supply Voltage (2.7 to 3.3V). VCCF pro- vides the power supply for Flash memory opera- tions (Read, Program and Erase). The Command Interface is disabled when the VCCF Supply Voltage is less than the Lockout Volt- age, VLKO . This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. A 0.1µF capacitor should be connected between the V CCF Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Program and Erase operations, I CC3 . VCCP Supply Voltage (2.7 to 3.3V). VCCP pro- vides the power supply for the PSRAM. VSS Ground. VSS is the ground reference for all voltage measurements in the Flash and PSRAM chips.
component to be in active mode at the same time. Table 2. Main Operation Modes Note: 1. X = Don’t Care (VIL or VIH).
- UBP and LBP are tied together.
- This table is valid when BYTE = VIH. This table is also valid when BYTE = VIL, with the only difference that DQ15-DQ8 are always
high impedance when the Flash Memory components are being accessed.
- For the Block Protect and Unprotect features, refer to the M29DW640D datasheet. Only the In-System Technique is available in
- To read the Manufacturer Code, the Device Code, the Block Protection Status and the Extended Block indicator bit, refer to the
“Auto Select Command” in the M29DW640D datasheet.
Figure 4. Functional Block Diagram
32 Mbit
64 Mbit
The M74DW66500B contains two 64Mbit Flash memories. For detailed information on how to use these, see the M29DW640D datasheet, which is available on the STMicroelectronics web site, www.st.com. PSRAM DEVICE The M74DW66500B contains a 32Mbit Pseudo SRAM. For detailed information on how to use it, see the M69AW048B datasheet, which is avail- able from your local STMicroelectronics distribu- tor.
Table 3. Absolute Maximum Ratings
when relying on the quoted parameters. Table 4. Operating and AC Measurement Conditions Figure 5. AC Measurement I/O Waveform Figure 6. AC Measurement Load Circuit Table 5. Device Capacitance Note: Sampled only, not 100% tested.
Table 6. Flash DC Characteristics Note: 1. Sampled only, not 100% tested.
- In Dual operations the Supply Current will be the sum of ICC1 (read) and ICC3 (program/erase).
Table 7. PSRAM DC Characteristics Note: 1. Maximum DC voltage on input and I/O pins is VCC +0 . 2 V . During voltage transitions, input may positive overshoot to VCC + 1.0V for a period of up to 5ns.
- Minimum DC voltage on input or I/O pins is –0.3V.
During voltage transitions, input may positive overshoot to VSS + 1.0V for a period of up to 5ns.
Figure 7. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline Note: Drawing is not to scale.
Table 8. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Package Mechanical Data
Table 9. Ordering Information Scheme information contact your nearest ST sales office. Devices are shipped from the factory with the memory content bits erased to ’1’. please contact the STMicroelectronics Sales Office nearest to you.
REVISION HISTORY
Table 10. Document Revision History
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States