74AC574 STMICROELECTRONICS | Alldatasheet

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■ HIGH SPEED: fMAX = 250MHz (TYP.) at VCC = 5V ■ LOW POWER DISSIPATION: I CC = 4µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.) ■ 50Ω TRANSMISSION LINE DRIVING CAPABILITY ■ SYMMETRICAL OUTPUT IMPEDANCE: OH | = IOL = 24mA (MIN) ■ BALANCED PROPAGATION DELAYS: t PLH ≅ tPHL ■ OPERATING VOLTAGE RANGE: V CC (OPR) = 2V to 6V ■ PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 574

■ IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74AC574 is an advanced high-speed CMOS OCTAL D-TYPE FLIP-FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. These 8 bit D-Type Flip-Flop are controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic that were setup at the D inputs. While the (OE ) input is low, the 8 outputs will be in a normal logic state (high or low logic level); while OE is in high level, the outputs will be in a high impedance state. The output control does not affect the internal operation of flip-flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74AC574 OCTAL D-TYPE FLIP-FLOP WITH 3 STATE OUTPUTS (NON INVERTED) PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R DIP 74AC574B SOP 74AC574M 74AC574MTR TSSOP 74AC574TTR TSSOPDIP SOP

INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION TRUTH TABLE X : Don’t Care Z : High Impedance LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays PIN No SYMBOL NAME AND FUNCTION 1O E 3-State Output Enable (Active LOW) 2, 3, 4, 5, 6, 7, 8, 9 D0 to D7 Data Inputs 12, 13, 14, 15, 16, 17, 18, 19 Q0 to Q7 3-State Outputs

11 CLOCK Clock Input (LOW-to-HIGH

Edge Trigger)

10 GND Ground (0V)

CC Positive Supply Voltage INPUTS OUTPUT OE CK D Q HXXZ L X NO CHANGE LL L LH H

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. RECOMMENDED OPERATING CONDITIONS 1) VIN from 30% to 70% of VCC Symbol Parameter Value Unit VCC Supply Voltage -0.5 to +7 V VI DC Input Voltage -0.5 to V CC + 0.5 V VO DC Output Voltage -0.5 to V CC + 0.5 V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 50 mA ICC or IGND DC V CC or Ground Current ± 400 mA Tstg Storage Temperature -65 to +150 °C TL Lead Temperature (10 sec) 300 °C Symbol Parameter Value Unit VCC Supply Voltage 2 to 6 V VI Input Voltage 0 to V CC V VO Output Voltage 0 to V CC V Top Operating Temperature -55 to 125 °C dt/dv Input Rise and Fall Time VCC = 3.0, 4.5 or 5.5V (note 1) 8 ns/V

1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω Symbol Parameter Test Condition Value UnitVCC (V) TA = 25°C -40 to 85°C -55 to 125°C VIH High Level Input Voltage 3.0 VO = 0.1 V or VCC -0.1V 2.1 1.5 2.1 2.1 VIL Low Level Input Voltage 3.0 VO = 0.1 V or VCC -0.1V 1.5 0.9 0.9 0.9 VOH High Level Output Voltage V 3.0 IO =-12 mA 2.56 2.46 2.4 4.5 IO =-24 mA 3.86 3.76 3.7 5.5 IO =-24 mA 4.86 4.76 4.7 VOL Low Level Output Voltage V 3.0 IO =12 mA 0.36 0.44 0.5 4.5 IO =24 mA 0.36 0.44 0.5 5.5 IO =24 mA 0.36 0.44 0.5 II Input Leakage Current 5.5 VI = VCC or GND ± 0.1 ± 1 ± 1 µA Ioz High Impedance Output Leakege Current 5.5 V I = VIH or VIL VO = VCC or GND ± 0.5 ± 2.5 ± 5 µA ICC Quiescent Supply Current 5.5 VI = VCC or GND 44 0 8 0 µA IOLD Dynamic Output Current (note 1, 2)5.5 VOLD = 1.65 V max 75 50 mA IOHD VOHD = 3.85 V min -75 -50 mA

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω , Input tr = tf = 3ns) (*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ± 0.5V CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC /n (per circuit) Symbol Parameter Test Condition Value UnitVCC (V) TA = 25°C -40 to 85°C -55 to 125°C tPLH tPHL Propagation Delay Time CK to Q ns tPZL tPZH Output Enable Time ns tPLZ tPHZ Output Disable Time ns tW CLOCK Pulse Width HIGH or LOW ns ts Setup Time D to CK, HIGH or LOW ns th Hold Time D to CK, HIGH or LOW ns fMAX Maximum Clock Frequency 3.3(*) 75 220 60 60 MHz 5.0(**) 95 250 85 85 Symbol Parameter Test Condition Value UnitVCC (V) TA = 25°C -40 to 85°C -55 to 125°C C IN Input Capacitance 5.0 4 pF C OUT Output Capacitance 5.0 8 pF C PD Power Dissipation Capacitance (note 5.0 fIN = 10MHz 18 pF

C L = 50pF or equivalent (includes jig and probe capacitance) R L = R1 = 500Ω or equivalent R T = ZOUT of pulse generator (typically 50Ω ) WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) TEST SWITCH tPLH , tPHL Open tPZL , tPLZ 2VCC tPZH , tPHZ Open

WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: PULSE WIDTH (f=1MHz; 50% duty cycle)

DIM. mm inch a1 0.254 0.010 B 1.39 1.65 0.055 0.065 b0 . 4 5 0 . 0 1 8 b1 0.25 0.010 D 25.4 1.000 E8 . 5 0 . 3 3 5 e2 . 5 4 0 . 1 0 0 e3 22.86 0.900 F7 . 1 0 . 2 8 0 I3 . 9 3 0 . 1 5 5 L3 . 3 0 . 1 3 0 Z1 . 3 4 0 . 0 5 3 P001J Plastic DIP-20 (0.25) MECHANICAL DATA

DIM. mm inch A2 . 6 5 0 . 1 0 4 a1 0.10 0.20 0.004 0.007 a2 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C0 . 5 0 0 . 0 2 0 c1 45 (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e1 . 2 7 0 . 0 5 0 e3 11.43 0.450 F 7.40 7.60 0.291 0.299 L 0.50 1.27 0.19 0.050 M0 . 7 5 0 . 0 2 9 S8 ( m a x . ) P013L SO-20 MECHANICAL DATA

DIM. mm inch A1 . 1 0 . 4 3 3 b 0.19 0.30 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 e 0.65 BSC 0.0256 BSC o 4o 8o 0o 4o 8o c Eb A2A D PIN 1 IDENTIFICATION A1 LKe TSSOP20 MECHANICAL DATA

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