M7232

ICM7231 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

• ICM7231 Drives 8 Digits of 7 Segments with Two Independent Annunciators Per Digit Address and Data Input in Parallel Format
• ICM7232 Drives 10 Digits of 7 Segments with Two Independent Annunciators Per Digit Address and Data Input in Serial Format
• All Signals Required to Drive Rows and Columns of Triplexed LCD Display are Provided
• Display Voltage Independent of Power Supply
• On-Chip Oscillator Provides All Display Timing
• Total Power Consumption Typically 200µW, Maximum 500µW at 5V
• Low-Power Shutdown Mode Retains Data With 5µW Typical Power Consumption at 5V, 1µW at 2V
• Direct Interface to High-Speed Microprocessors

Description

The ICM7231 and ICM7232 family of integrated circuits are designed to generate the voltage levels and switching wave- forms required to drive triplexed liquid-crystal displays. These chips also include input buffer and digit address decoding circuitry allowing six bits of input data to be decoded into 64 independent combinations of the output segments of the selected digit. The family is designed to interface to modern high- performance microprocessors and microcomputers and ease system requirements for ROM space and CPU time needed to service a display.

Ordering Information

PART NUMBER TEMP. RANGE ( oC) PACKAGE NUMBER OF DIGITS INPUT FORMAT PKG. NO. ICM7231BFIJL -25 to 85 40 Ld CERDIP 8 Digit Parallel F40.6 ICM7231BFIPL -25 to 85 40 Ld PDIP 8 Digit Parallel E40.6 ICM7232BFIPL -25 to 85 40 Ld PDIP 10 Digit Serial E40.6 ICM7232CRIPL -25 to 85 40 Ld PDIP 10 Digit Serial E40.6 NOTE: All versions intended for triplexed LCD displays. File Number 3161.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

(PDIP, CERDIP) TOP VIEW ICM7232AF, BF (PDIP, CERDIP) TOP VIEW ICM7232CR (PDIP) TOP VIEW CS VDISP BP1 BP2 BP3 b1, c1,an11 a1,g1,d1 f1,e1,an21 b2,c2,an12 a2,g2,d2 f2,e2,an22 b3, c3,an13 a3,g3,d3 f3, e3,an23 b4,c4,an14 a4,g4,d4 f4,e4,an24 b5,c5,an15 a5,g5,d5 f5,e5,an25 V DD VSS BD3 BD2 BD1 BD0 AN2 AN1 f8,a8,an28 a8,g8,d8 b8,c8,an18 f7,e7,an27 a7,g7,d7 b7,c7,an17 f6,e6,an26 a6,g6,d6 b6,c6,an16 DATA CLOCK VDISP BP1 BP2 BP3 b1,c1,an11 a1,g1,d1 f1,e1,an21 b2, c2,an12 a2,g2,d2 f2,e2,an22 b3,c3,an13 a3,g3,d3 f3,e3,an23 b4,c4, an14 a4,g4,d4 f4,e4,an24 b5,c5,an15 a5,g5, d5 f5,e5,an25 V DD WRITE INPUT DATA INPUT DATA ACCEPTED VSS b6,c6, an16 a6,g6,d6 f6,e6, an26 b7,c7,an17 a7,g7,d7 a9,g9,d9 f9,e9,an29 b10,c10,an110 a10,g10,d10 f10,e10,an210 f7,e7,an27 b8,c8,an18 a8,g8,d8 f8,a8,an28 b9,c9,an19 OUTPUT INPUT DATA CLOCK VDISP BP1 BP2 BP3 b1,c1,an11 a1,g1,d1 f1,e1, an21 b2,c2,an12 a2,g2,d2 f2,e2,an22 b3,c3,an13 a3,g3,d3 f3,e3, an23 b4, c4,an14 a4,g4,d4 f4,e4,an24 b5, c5,an15 a5,g5,d5 f5,e5, an25 V DD WRITE INPUT DATA INPUT DATA ACCEPTED VSS b6,c6,an16 a6,g6,d6 f6,e6,an26 b7,c7,an17 a7,g7,d7 a9,g9,d9 f9,e9,an29 b10,c10,an110 a10,g10,d10 f10,e10,an210 f7,e7,an27 b8,c8,an18 a8,g8,d8 f8,a8,an28 b9,c9,an19 OUTPUT INPUT ICM7231, ICM7232

NOTE: See Figure 13 for display segment connections. SEGMENT LINE DRIVERS

3 WIDE

9 WIDE

PIN 2 (INPUT) ADDRESS INPUTSDATA INPUTS f2,e2,an22 a2,g2, d2 b2, c2,an12 f1,e1,an21 a1,g1,d1 b1,c1,an11 COMMON LINE DRIVERS DIGIT ADDRESS DECODER DATA INPUT LATCHES AN1 BD0 BD2 AN2 BD1 BD3 EN ADDRESS INPUT LATCHES EN A2A1A0 ONE SHOT DISPLAY TIMING GENERATOR 9 999999 ICM7231, ICM7232

NOTE: See Figures 13 and 14 for display segment connections. Functional Block Diagrams (Continued) SEGMENT LINE DRIVERS V DD VH VL VDISP ON CHIP DISPLAY VOLTAGE LEVEL GENERATOR PIN 2 (INPUT) SHIFT REGISTER DATA COMMON LINE DRIVERS DIGIT ADDRESS DECODER AN1 BD0 BD2AN2 BD1 BD3 SERIAL INPUT CONTOL LOGIC DISPLAY TIMING GENERATOR D9 D8 9 9 9 9 9 9 9 9 9 INPUT DATA CLOCK WRITE INPUT DATA ACCEPTED INPUT OUTPUTSHIFTS RIGHT TO LEFT ON RISING EDGE OF DATA CLOCK CLOCK DATAA2A1A0 A3 f2,e2,an22 a2,g2, d2 b2, c2,an12 f1,e1,an21 a1,g1,d1 b1,c1,an11 ICM7231, ICM7232

Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 2)θJA (oC/W) θJC (oC/W) Maximum Junction Temperature oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Due to the SCR structure inherent in these devices, connecting any display terminal or the display voltage terminal to a voltage outside the power supply to the chip may cause destructive device latchup. The digital inputs should never be connected to a voltage less than -0.3V below ground, but maybe connected to voltages above VDD but not more than 6.5V above VSS . 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsV+ = 5V +10%, VSS = 0V, TA = -25oC to 85oC, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Power Supply Voltage, VDD 4.5 >4 5.5 V Data Retention Supply Voltage, VDD Guaranteed Retention at 2V 2 1.6 - V Logic Supply Current, IDD Current from VDD to Ground Excluding Display. VDISP = 2V - 30 100 µA Shutdown Total Current, IS VDISP Pin 2 Open - 1 10 µA Display Voltage Range, VDISP VSS ≤ VDISP ≤ VDD 0- V DD V Display Voltage Setup Current, IDISP VDISP = 2V, Current from VDD to VDISP On-Chip - 15 30 µA Display Voltage Setup Resistor Value, RDISP One of Three Identical Resistors in String 40 75 - k Ω DC Component of Display Signals (Sample Test Only) - 1/4 1% ( V DD - VDISP) Display Frame Rate, fDISP See Figure 5 60 90 120 Hz Input Low Level, VIL ICM7231, Pins 30 - 35, 37 - 39, 1 ICM7232, Pins 1, 38, 39 (Note 2) - - 0.8 V Input High Level, VIH 2.0 - - V Input Leakage, IILK - 0.1 1 µA Input Capacitance, CIN -5- p F Output Low Level, VOL Pin 37, ICM7232, IOL = 1mA - - 0.4 V Output High Level, VOH VDD = 4.5V, IOH = -500µA 4.1 - - V Operating Temperature Range, TOP Industrial Range -25 - +85 oC AC Specifications VDD = 5V +10% VSS = 0V, -25oC to 85oC PARAMETER TEST CONDITIONS MIN TYP MAX UNITS PARALLEL INPUT (ICM7231) See Figure 1 Chip Select Pulse Width, tCS (Note 1) 500 350 - ns Address/Data Setup Time, tDS (Note 1) 200 - - ns Address/Data Hold Time, tDH (Note 1) 0 -20 - ns Inter-Chip Select Time, tICS (Note 1) 3 - - µs SERIAL INPUT (ICM7232) See Figures 2, 3 Data Clock Low Time, tCL (Note 1) 350 - - ns Data Clock High Time, tCL (Note 1) 350 - - ns Data Setup Time, tDS (Note 1) 200 - - ns Data Hold Time, tDH (Note 1) 0 -20 - ns Wr ite Pulse Width, tWP (Note 1) 500 350 - ns Wr ite Pulse to Clock at Initialization, tWLL (Note 1) 1.5 - - µs Data Accepted Low Output Delay, tODL (Note 1) - 200 400 ns Data Accepted High Output Delay, tODH (Note 1) - 1.5 3 µs Write Delay After Last Clock, tCWS (Note 1) 350 - - ns ICM7231, ICM7232

TYPE NUMBER OUTPUT CODE ANNUNCIATOR LOCATIONS INPUT OUTPUT ICM7231BF Code B Both Annunciators on BP3 Parallel Entry, 4-bit Data, 2-bit Annunciators, 3-bit Address

8 Digits plus

16 Annunciators

ICM7232AF Hexadecimal Both Annunciators on BP3 Serial Entry, 4-bit Data, 2-bit Annunciators, 4-bit Address

10 Digits plus

20 AnnunciatorsICM7232BF Code B

ICM7232CR Code B 1 Annunciator BP1

1 Annunciator BP3

Terminal Definitions TERMINAL PIN NO. DESCRIPTION FUNCTION ICM7231 PARALLEL INPUT NUMERIC DISPLAY AN1 30 Annunciator 1 Control Bit High = ON AN2 31 Annunciator 2 Control Bit Low = OFF See Table 3 BD0 32 Least Significant 4-bit Binary Data Inputs Input Data (See Table 1) HIGH = Logical One (1) LOW = Logical Zero (0)BD1 33 BD2 34 BD3 35 Most Significant A0 37 Least Significant 3-bit Digit Address Inputs Input Address (See Table 2)A1 38 A2 39 Most Significant CS 1 Data Input Strobe/Chip Select (Note 2) Trailing (Positive going) edge latches data, causes data input to be decoded and sent out to addressed digit ICM7232 SERIAL DATA AND ADDRESS INPUT Data Input 38 Data+ Address Shift Register Input HIGH = Logical One (1) LOW = Logical Zero (O) WRITE Input 39 Decode, Output, and Reset Strobe When DATA ACCEPTED Output is LOW, positive going edge ofWRITE causes data in shift register to be decoded and sent to addressed digit, then shift register and control logic to be reset. When DATA ACCEPTED Output is HIGH, positive going edge of WRITE triggers reset only. Data Clock Input

1 Data Shift Register and Control Logic

Positive going edge advances data in shift register. ICM7232: Elev- enth edge resets shift register and control logic. DATA ACCEPTED Output 37 Handshake Output Output LOW when correct number of bits entered into shift register. ALL DEVICES Display Voltage V DlSP

2 Negative end of on-chip resistor string

used to generate intermediate voltage levels for display. Shutdown Input. Display voltage control. When open (or less than 1V from V DD ) chip is shutdown; oscillator stops, all display pins to VDD . Common Line Driver Outputs 3, 4, 5 Drive display commons, or rows Segment Line Driver Outputs 6 - 29 6 - 35 (On ICM7231) (On ICM7232) Drive display segments, or columns. V DD 40 Chip Positive Supply VSS 36 Chip Negative Supply NOTES: 1. For Design reference only, not 100% tested. 2. CS has a special “mid-level” sense circuit that establishes a test mode if it is held near 3V for several ms. Inadvertent triggering of this mode can be avoided by pulling it high when inactive, or ensuring frequent activity. ICM7231, ICM7232

ister depending on subsequent DATA CLOCK inputs. the eleventh clock resets the shift register and control logic. chip ready to accept data for the next digit/character. ciators off, as shown in Figure 3. is to be turned on, all ten bits are used. pulse, none of the outputs will be changed. tors per digit. See Table 3 for annunciator input controls. The “A” and “B” suffix chips place both annunciators on BP3. supply Code B outputs (see Table 1). the right hand annunciator (usually a decimal point) on BP3. TABLE 1. BlNARY DATA DECODING ICM7231 AND ICM7232

1111 BLANK

FIGURE 15. 10MHz FREQUENCY/PERIOD POINTER WITH LCD DISPLAY

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 ICM7231, ICM7232