M7040N STMICROELECTRONICS | Alldatasheet

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Technical content

Figure 1. 388-ball PBGA Package

Table 2. Signal Names See DESCRIPTIONS FOR CONNECTION DIAGRAM (Figure 3, page 9), page 152 for individual connection details.

  1. In the previous versions of this specification, this signal was called,“CLK_OUT. ”
  2. In previous versions of this specification, this signal was called,“PLL_BYPASS. ”
  3. ACK and EOT Signals require a weak, external pull-down resistor of 47 KΩ or 100 KΩ .

Figure 3. Connections

Figure 4. M7040N Block Diagram

Table 3. Absolute Maximum Ratings Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

tions when using the quoted parameters. Table 4. DC and AC Measurement Conditions Note: 1. Maximum allowable applies to overshoot only (VDDQ is 3.3V supply).

  1. Minimum allowable applies to undershoot only.

Table 5. Capacitance Note: 1. Effective capacitance measured with power supply. Sampled only, not 100% tested. Table 6. DC Characteristics Note: 1. Valid for Ambient Operating Temperature: TA =0t o7 0°C; VDD =1 . 5 V .

Figure 8. AC Timing Waveforms with CLK2X

Figure 9. AC Timing Waveforms with CLK1X

Table 7. AC Timing Parameters with CLK2X Note: 1. Valid for Ambient Operating Temperature: TA =0t o7 0°C; VDD =1 . 5 V .

  1. Values are based on 50% signal levels.
  2. Based on an AC load of CL = 30pF (see Figure 5, Figure 6, and Figure 7, page 13).
  3. These parameters are sampled and not 100% tested, and are based on an AC load of 5pF.

Table 8. AC Timing Parameters with CLK1X Note: 1. Valid for Ambient Operating Temperature: TA =0t o7 0°C; VDD =1 . 5 V .

  1. Values are based on 50% signal levels and a 50/50% duty cycle of CLK1X.
  2. Based on an AC load of CL = 30pF (see Figure 5, Figure 6, and Figure 7, page 13).
  3. These parameters are sampled and not 100% tested, and are based on an AC load of 5pF.

CMD[10:0] carries the command and its associat- ed parameter. DQ[71:0] is used for data transfer to and from the database entries. These entries com- prise a data and a mask field that are organized as data and mask arrays. The DQ Bus carries the search data (of the data and mask arrays and in- ternal registers) during the SEARCH command as well as the address and data during READ and/or WRITE operations. The DQ Bus can also carry the address information for the flow-through accesses to the external SRAMs and/or SSRAMs. Database Entry (Data Array and Mask Array) Each database entry comprises a data and a mask field. The resultant value of the entry is“1,”“0,”or “X (don’t care),”depending on the value in the data and mask bits. The on-chip priority encoder se- lects the first matching entry in the database that is nearest to location“0.” Arbitration Logic When multiple Search Engines are cascaded to create large databases, the data being searched is presented to all Search Engines simultaneously in the cascaded system. If multiple matches occur within the cascaded devices, arbitration logic on the Search Engines will enable the winning device (with a matching entry that is closest to address“0” of the cascaded database) to drive the SRAM bus. Pipeline and SRAM Control Pipeline latency is added to give enough time to a cascaded system’s arbitration logic to determine the device that will drive the index of the matching entry on the SRAM bus. Pipeline logic adds laten- cy to both the SRAM access cycles and the SSF and SSV signals to align them to the host ASIC re- ceiving the associated data. Full Logic Bit[0] in each of the 72-bit entries has a special purpose for the LEARN command (0 = empty, 1 = full). When all the data entries have bit[0] = 1, the database asserts the FULL Flag, indicating all the Search Engines in the depth-cascaded array are full. Connection Descriptions CLOCK MODE (CLK_MODE). This signal allows the selection of clock input to the CLK1X/CLK2X pin. If the CLK_MODE pin is low, CLK2X must be supplied on that pin. PHS_L must also be sup- plied. If the CLK_MODE pin is high, CLK1X must be supplied on the CLK2X/CLK1X pin, and the PHS_L signal is not required. When the CLK_MODE is high, PHS_L is unused and should be externally grounded. Master Clock (CLK2X/CLK1X).Depending on the CLK_MODE pin, either the CLK2X or the CLK1X must be supplied. M7040N samples con- trol and data signals on both the edges of CLK1X if CLK1X is supplied. M7040N samples all the data and control pins on the positive edge of CLK2X if the CLK2X and PHS_L signals are supplied. All signals are driven out of the device on the rising edge of CLK1X if CLK1X is supplied, and are driv- en on the rising edge of CLK2X (when PHS_L is low) if CLK2X is supplied. Phase (PHS_L). This signal runs at half the fre- quency of CLK2X and generates an internal clock from CLK2X (see Figure 10, page 21). Test Output (TEST_CO).This is test output and will stay unconnected in the application of the de- vice. Test Input (TEST).This signal should be con- nected to ground. Test Input (TEST_FM).This signal should be connected to ground. Reset (RST_L).Driving RST_L low initializes the device to a known state. Test Input (TEST_PB).This signal should be connected to ground. Configuration.When CFG_L is low, M7040N will operate in backward compatibility mode with M7010 and M7020. When CFG_L is low, the CMD[10:9] should be externally grounded. With CFG_L low, the device will behave identically with M7010 and M7020, and the new feature added to M7040N will be disabled. When CFG_L is high, the additional command CMD[10:9] can be used and the following addition- al features will be supported: 1. 16 pairs of Global Masks are supported instead of eight; 2. Parallel WRITE to the data and mask arrays is supported (see Parallel WRITE, page 38); and 3. configuring tables of up to three different widths does not require table identification bits in the data array, thus saving two bits from each 72-bit

Command Bus (CMD[10:0]. [1:0] specifies the command; [10:2] contains the command parame- ters. The descriptions of individual commands ex- plains the details of the parameters. The encoding of commands based on the [1:0] field are: – 00: PIO READ – 01: PIO WRITE – 10: SEARCH – 11: LEARN Command Valid ( CMDV) . Qualifies the CMD bus as follows: – 0: No Command – 1: Command Address/Data Bus (DQ[71:0]). Carries the Read and WRITE address as well as the data during register, data, and mask array operations. It car- ries the compare data during search operations. It also carries the SRAM address during SRAM PIO accesses. READ Acknowledge (ACK). Indicates that valid data is available on the DQ Bus during register, data, and mask array READ operations, or the data is available on the SRAM data bus during SRAM READ operations. Note: ACK Signals require a weak external pull- down resistor such as 47 or 100 KΩ . End of Transfer (EOT).Indicates the end of burst transfer during READ or WRITE burst oper- ations. Note: EOT Signals require a weak external pull- down resistor such as 47 KΩ or 100 KΩ . SEARCH Successful Flag (SSF).When assert- ed, this signal indicates that the device is the glo- bal winner in a SEARCH operation. SEARCH Successful Flag Valid (SSV).When asserted, this signal qualifies the SSF signal. Multiple Hit Flag (MULTI_HIT).When asserted, this signal indicates that there is more than one lo- cation having a match on this device. High Speed (HIGH_SPEED). When this signal is high, the device will run up to 100MHz and perform 100 million searches per second. However, in this mode, a TLSZ value of '00' is not supported in a system of a single device. Furthermore, the device will only support a TLSZ of '00' and '01' if more than one device is cascaded to form database ta- bles. Clock Tune [3:0] (CLK_TUNE[3:0]).These test pins should be set to logic level 1001. SRAM Address (SADR[23:0]). This bus con- tains address lines to access off-chip SRAMs that contain associative data. See Table 52, page 128 for the details of the generated SRAM address. In a database of multiple M7040Ns, each corre- sponding bit of SADR from all cascaded devices must be connected. SRAM Chip Enable (CE_L). This is Chip Enable control for external SRAMs. In a database of mul- tiple M7040Ns, CE_L of all cascaded devices must be connected. This signal is then driven by only one of the devices. S R A MW r i t eE n a b l e( W E _ L ) .This is Write En- able control for external SRAMs. In a database of multiple M7040Ns, WE_L of all cascaded devices must be connected together. This signal is then driven by only one of the devices. SRAM Output Enable (OE_L). This is Output Enable control for external SRAMs. Only the last device drives this signal (with the LRAM bit set). Address Latch Enable (ALE_L).When this sig- nal is low, the addresses are valid on the SRAM Address Bus. In a database of multiple M7040Ns, the ALE_L of all cascaded devices must be con- nected. This signal is then driven by only one of the devices. Local Hit In (LHI[6:0]).These pins depth-cas- cade the device to form a larger table size. One signal of this bus is connected to the LHO[1] or LHO[0] of each of the upstream devices in a block. Connect all unused LHI pins to a logic '0.' (For more information, see DEPTH-CASCADING, page 124.) Local Hit Out (LHO[1:0]).LHO[1] and LHO[0] are the same logical signal. LHO[1] or LHO[0] is connected to one input of the LHI bus of up to four downstream devices (in a block that contains up to eight devices). (For more information, see DEPTH-CASCADING, page 124.) Block Hit In (BHI[2:0]).Inputs from the previous BHO[2:0] are tied to the BHI[2:0] of the current de- vice (see DEPTH-CASCADING, page 124). In a four-block system, the last block can contain only seven devices because the ID code 11111 is used for broadcast access. Block Hit Out (BHO[2:0]).These outputs from the last device in a block are connected to the BHI[2:0] inputs of the devices in the downstream blocks (see DEPTH-CASCADING, page 124).

Figure 12. Clocks for All Timing Diagrams that is generated by multiplying CLK1X by two. in the timing specification section. described in the following subsections. Table 9. Register Overview 32–47, 96–111 MASKS RW 16 Global Mask Registers Pairs. 48–55 SSR0 –7 R 8 SEARCH Successful Index Registers. 56 COMMAND RW Command Register. 57 INFO R Information Register. 58 RBURREG RW Burst Read Register. 59 WBURREG RW Burst Write Register. 60 NFA R Next Free Address Register.

Table 10. SEARCH-Successful Register (SSR) Description

Table 11. Command Register Field Descriptions automatically resets to a '0' the reset cycle has completed. output signals LHO[1:0] and BHO[2:0] to '0.' It also keeps the DQ Bus in input mode. devices power up in the system. table and is the default driver for the SSF and SSV signals.

Table 12. Information Register Field Descriptions OE_L is always driven by the device for which this bit is set. Bits [10:9] apply to configuring the 1st quadrant in the address space. Bits [12:11] apply to configuring the 2nd quadrant in the address space. Bits [14:13] apply to configuring the 3rd quadrant in the address space. Bits [16:15] apply to configuring the 4th quadrant in the address space. Bits [18:17] apply to configuring the 5th quadrant in the address space. Bits [20:19] apply to configuring the 6th quadrant in the address space. Bits [22:21] apply to configuring the 7th quadrant in the address space. Bits [24:23] apply to configuring the 8th quadrant in the address space. for each revision of the device. Implementation [6:4] 001 This is the M7040N implementation number. Device ID [15:8] 00000100 This is the Device Identification Number.

programmed before burst read. Table 13. Read Burst Register Description be programmed before burst write. Table 14. Write Burst Register Description '1' to indicate full/empty status. (e.g., '10' or '01' settings are invalid). Table 15. NFA Register field must be reinitialized for the next operation. field must be reinitialized for the next operation.

60 Reserved Index

ue of the CFG bits in the command register. successful search during a SEARCH operation. and mask array addressing procedure. Figure 15. M7040N Database Width Configuration

32 K 16 K

Table 16. Bit Position Match Figure 16. Multi-width Configuration Example Figure 17. M7040N Data and Mask Array Addressing

4 K 144

2 K 288

Table 17. Command Codes

00 READ Reads one of the following: data array, mask array, device registers, or external

01 WRITE Writes one of the following: data array, mask array, device registers, or external

10 SEARCH Searches the data array for a desired pattern using the specified register from the

global mask register array and local mask associated with each data cell.

11 LEARN

the NFA register) using the LEARN Instruction.

Table 18. Command Parameters Note: 1. Use only CMD[8:0] and connect the CMD[10:9] to ground with CFG_L low.

  1. For a description of CMD[9] and CMD[2] see subsections on search 288-bit configured tables and mixed-size searches with CFG_L
  2. The 288-bit-configured devices or 288-bit-configured quadrants within devices do not support the LEARN Instruction.

0 Normal

1 Parallel

T h eR E A Dc a nb eas i n g l er e a do fad a t aa r r a y ,a mask array, an SRAM, or a register location (CMD[2] = 0). It can be a burst READ (CMD[2] = 1) or mask array locations using an internal auto-in- crementing address register (RBURADR). Table 19, page 34 describes each type of READ com- mand. A single-location READ operation lasts six cycles, as shown in Figure 18, page 33. The burst READ adds two cycles for each successive READ. The SADR[23:21] bits supplied in the READ Instruction Cycle A drive SADR[23:21] signals during the READ of an SRAM location. The single READ operation takes six CLK cycles, in the following sequence: – Cycle 1:The host ASIC applies the READ In- struction on the CMD[1:0] (CMD[2] = 0), using CMDV = 1, and the DQ Bus supplies the ad- dress, as shown in Table 20, page 34 and Table 21, page 35. The host ASIC selects the M7040N for which ID[4:0] matches the DQ[25:21] lines. If the DQ[25:21] = 11111, the host ASIC selects the M7040N with the LDEV Bit set. The host ASIC also supplies SADR[23:21] on CMD[8:6] in Cycle A of the READ Instruction if the READ is directed to the external SRAM. – Cycle 2:The host ASIC floats DQ[71:0] to 3- state condition. – Cycle 3:The host ASIC keeps DQ[71:0] in 3- state condition. – Cycle 4:The selected device starts to drive the DQ[71:0] Bus and drives the ACK signal from Z to low. – Cycle 5:The selected device drives the read data from the addressed location on the DQ[71:0] Bus and drives the ACK signal high. – Cycle 6:The selected device floats DQ[71:0] to 3-state condition and drives the ACK signal low. At the termination of Cycle 6, the selected device releases the ACK line to 3-state condition. The READ Instruction is complete, and a new opera- tion can begin. Note:The latency of the SRAM READ will be dif- ferent than the one described above (see SRAM PIO Access, page 128). Table 20, page 34 lists and describes the format of the READ address for a data array, mask array, or SRAM. In a burst READ operation, the READ lasts 4 + 2n CLK-cycles (where“n” stands for the number of accesses in the burst specified by the BLEN field of the RBURREG). Table 21, page 35 describes the READ address format for the internal registers. Figure 19, page 33 illustrates the timing diagram for the burst READ of the data or mask array. This operation assumes that the host ASIC has pro- grammed the RBURREG with the starting address (ADR) and the length of transfer (BLEN) before ini- tiating the burst READ command. – Cycle 1:The host ASIC applies the READ In- struction on the CMD[1:0] (CMD[2] = 1), using CMDV=1 and the address supplied on the DQ Bus, as shown in Table 22, page 35. The host ASIC selects the M7040N for which ID[4:0] matches the DQ[25:21] lines. If the DQ[25:21] = 11111, the host ASIC selects the M7040N with the LDEV Bit set. – Cycle 2:The host ASIC floats DQ[71:0] to the 3- state condition. – Cycle 3:The host ASIC keeps DQ[71:0] in the 3-state condition. – Cycle 4:The selected device starts to drive the DQ[71:0] Bus and drives ACK and EOT from Z to low. – Cycle 5:The selected device drives the READ data from the addressed location on the DQ[71:0] Bus and drives the ACK signal high. Note:Cycles four and five repeat for each addi- tional access until all the accesses specified in the burst length (BLEN) field of RBURREG are complete. On the last transfer, the M7040N drives the EOT signal high. – Cycle (4 + 2n):The selected device drives the DQ[71:0] to 3-state condition and drives the ACK and the EOT signals low. At the termination of Cycle 4 + 2n, the selected de- vice floats the ACK line to 3-state condition. The burst READ Instruction is complete, and a new op- eration can begin (see Table 22, page 35 for burst READ address formats).

Table 19. READ Command Parameters Table 20. Data and Mask Array, SRAM Read Address Format Note: 1.“|”stands for Logical OR operation.“{}”stands for concatenation operator.

0 Single Read Reads a single location of the data array, mask array, external SRAM,

or device registers. All access information is applied on the DQ Bus.

1 Burst Read

auto-increments the address for each access. All other access information is applied on the DQ Bus. address of data array location. address of mask array location.

Table 21. READ Address Format for Internal Registers Table 22. READ Address Format for Data and Mask Arrays

  1. The burst WRITE adds one extra cycle for

mask array location in {CMD[10], CMD[5:3]}. sets CMD[9] to '0' for the normal WRITE. cle, another operation can begin.

register) of the selected device. a new instruction can begin. Figure 20. Single Location WRITE Cycle Timing

Figure 21. Burst WRITE of the Data and Mask Arrays (BLEN = 4) Table 23. (Single) WRITE Address Format for Data and Mask Arrays or SRAM Note: 1.“|”stands for Logical OR operation.“{}”stands for concatenation operator. address of the data array location. address of the mask array location. address of the data SRAM location.

Table 24. WRITE Address Format for Internal Registers Table 25. WRITE Address Format for Data and Mask Array (Burst Write) ther the data or mask array.

  1. Mixed-sizes on tables configured with differ-

0000000000000000) for one set of parameters. '1,' and LDEV to '1' in the command register. single 72-bit SEARCH command. grammed with the same value.

Figure 23. 72-Bit Configuration SEARCH Timing Diagram for One Device

Figure 24. x72 Table with One Device Table 26. Latency of SEARCH from Instruction to SRAM Access Cycle, 72-bit Table 27. Shift of SSF and SSV from SADR

Table 28. Hit/Miss Assumption Figure 25. Hardware Diagram for a Table with Eight Devices

Figure 26. x72 Table with Eight Devices

Figure 27. Timing Diagram for 72-bit SEARCH For Device 0 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.

Figure 28. Timing Diagram for 72-bit SEARCH For Device 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.

Figure 29. Timing Diagram for 72-bit SEARCH For Device 7 (Last Device) Note: 1. |(LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.

grammed with the same value. ed by the GMR Index in the command’s Cycle A. LEARN command only in the first non-full device. be the default driver for such missed cycles. Table 31. Hit/Miss Assumption

Figure 30. Hardware Diagram for a Table with 31 Devices

Figure 31. Hardware Diagram for a Block of Up To Eight Devices

Figure 32. x72 Table with 31 Devices

Figure 33. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 34. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 35. Timing Diagram for the Globally Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 36. Timing Diagram for Devices Below the Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 37. Timing Diagram for Devices Above the Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 38. Timing Diagram for the Globally Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 39. Timing Diagram for Devices Below the Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 40. Timing Diagram for Devices Above the Winning Device in Block Number 3 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 41. Timing Diagram for the Globally Winning Device in Block Number 3 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 42. Timing Diagram for Devices Below the Winning Device in Block Number 3 (except Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 43. Timing Diagram for Device 6 in Block Number 3 (Device 30 in Depth-Cascaded Table) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Table 32. Latency of SEARCH from Instruction to SRAM Access Cycle Table 33. Shift of SSF and SSV from SADR MAND CODES AND PARAMETERS, page 30). SEARCH command ('10') on CMD[1:0]. data ([71:0]), compared to all odd locations.

Figure 45. Timing Diagram for a 144-bit SEARCH for 1 Device

Figure 46. x144 Table with One Device Table 34. Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit Table 35. Shift of SSF and SSV from SADR

Table 36. Hit/Miss Assumption Figure 47. Hardware Diagram for a Table with Eight Devices

Figure 48. x144 Table with Eight Devices

Figure 49. Timing Diagram for 144-bit SEARCH for Device Number 0 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.

Figure 50. Timing Diagram for 144-bit SEARCH for Device Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.

Figure 51. Timing Diagram for 144-bit SEARCH for Device Number 7 (Last Device) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.

MAND CODES AND PARAMETERS, page 30). compared against all odd locations. in a depth-cascaded table of more than one block. will be the default driver for such missed cycles. The SEARCH command is a pipelined operation. HLAT, as specified in Table 41, page 90. Table 39. Hit/Miss Assumption

Figure 52. Hardware Diagram for a Table with 31 Devices

Figure 53. Hardware Diagram for a Block of Up to Eight Devices

Figure 54. x144 Table with 31 Devices

Figure 55. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 56. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 57. Timing Diagram for the Globally Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 58. Timing Diagram for Devices Below the Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 59. Timing Diagram for Devices Above the Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 60. Timing Diagram for the Globally Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 61. Timing Diagram for Devices Below the Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 62. Timing Diagram for Devices Above the Winning Device in Block Number 3 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 63. Timing Diagram for the Globally Winning Device in Block Number 3 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 64. Timing Diagram for Devices Below the Winning Device in Block Number 3 (except Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 65. Timing Diagram for Device 6 in Block Number 3 (Device 30 in Depth-Cascaded Table) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Table 40. Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit Table 41. Shift of SSF and SSV from SADR “1”in the four 72-bits-word page. used for bits [143:0] of the data being searched. Instruction is not supported for x288 tables. that apply to DQ data in Cycles C and D.

Figure 67. Timing Diagram for 288-bit SEARCH (One Device)

Figure 68. x288 Table with One Device Table 42. Latency of SEARCH from Cycles C and D to SRAM Access Cycle Table 43. Shift of SSF and SSV from SADR

Cycles is shown in Table 45, page 101. specified in Table 46, page 101. Table 44. Hit/Miss Assumption

Figure 69. Hardware Diagram for a Table with Eight Devices

Figure 70. x288 Table with Eight Devices

Figure 71. Timing Diagram for 288-bit SEARCH for Device Number 0 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.

Figure 72. Timing Diagram for 288-bit SEARCH for Device Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.

Figure 73. Timing Diagram for 288-bit SEARCH for Device Number 7 (Last Device) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.

Table 45. Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 288-bit Table 46. Shift of SSF and SSV from SADR of eight devices is shown in Figure 75, page 104. LRAM = 1 and LDEV = 1 (Device 30 in this case). one device with the matching entry in each block.

The following is the sequence of operation for a single 288-bit SEARCH command (see COM- MAND CODES AND PARAMETERS, page 30). – Cycle A:The host ASIC drives the CMDV high and appliesSEARCH command code ('10') on CMD[1:0] signals. {CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair used for bits [287:144] of the data being searched. DQ[71:0] must be driven with the 72- bit data ([287:216])to be compared to all loca- tions“0” in the four 72-bit-word page. The CMD[2] signal must be driven to logic '1.' Note: CMD[2] = 1 signals that the search is a x288-bit search. CMD[8:6] is ignored in this cy- cle. – Cycle B:The host ASIC continues to drive the CMDV high and applies SEARCH command ('10') on CMD[1:0]. The DQ[71:0] is driven with the 72-bit data ([215:144]) to be compared to all locations '1' in the four 72-bits-word page. – Cycle C:The host ASIC drives the CMDV high and appliesSEARCH command code ('10') on CMD[1:0] signals. {CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair used for the bits [143:0] of the data being searched. CMD[8:6] signals must be driven with the bits that will be driven by this device on SADR[23:21] if it has a hit. DQ[71:0] must be driven with the 72-bit data ([143:72]) to be com- pared to all locations“2”in the four 72-bit-word page. The CMD[2] signal must be driven to logic '0.' – Cycle D:The host ASIC continues to drive the CMDV high and continues to apply SEARCH command code ('10') on CMD[1:0]. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the Hit Flag (see SEARCH- Successful Registers (SSR[0:7]), page 24). The DQ[71:0] is driven with the 72-bit data ([71:0]) to be compared to all locations“3”in the four 72- bit-word page. CMD[5:2] is ignored because the LEARN Instruction is not supported for x288 ta- bles. Note:For 288-bit searches, the host ASIC must supply four distinct 72-bit data words on DQ[71:0] during Cycles A, B, C, and D. The GMR Index in Cycle A selects a pair of GMRs in each of the 31 devices that apply to DQ data in Cycles A and B. The GMR Index in Cycle C se- lects a pair of GMRs in each of the 31 devices that apply to DQ data in Cycles C and D. The logical 288-bit SEARCH operation is as shown in Figure 76, page 105. The entire table of 288-bit entries is compared to a 288-bit word K that is presented on the DQ Bus in Cycles A, B, C, and D of the command using the GMR and local mask bits. The GMR is the 288-bit word specified by the two pairs of GMRs selected by the GMR In- dexes in the command’s Cycles A and C in each of the 31 devices. The 288-bit word K that is pre- sented on the DQ Bus in Cycles A, B, C, and D of the command is compared to each entry in the ta- ble starting at location“0.”The first matching en- try’s location address,“L,”is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see SRAM ADDRESSING, page 128). Note:The matching address is always going to be location“0”in a four-entry page for 288-bit search (two LSBs of the matching index will be '00'). The SEARCH command is a pipelined operation and executes a search at one-fourth the rate of the frequency of CLK2X for 288-bit searches in x288- configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 288-bit SEARCH command (measured in CLK cycles) from the CLK2X cycle that contains Cycles C and D shown in Table 48, page 117. The latency of a SEARCH from command to SRAM access cycle is 6 for only a single device in the table and TLSZ = 10. In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 49, page 117 The 288-bit SEARCH operation is pipelined and executes as follows: – Four cycles from the last cycle of the SEARCH command each of the devices knows the out- come internal to it for that operation. – In the fifth cycle from the SEARCH command, the devices in a block (which is less than or equal to eight devices resolving the winner with- in them using an LHI[6:0] and LHO[1:0] signal- ling mechanism) arbitrate for a winner. – In the sixth cycle after the SEARCH command, the blocks of devices resolve the winning block through a BHI[2:0] and BHO[2:0] signalling mechanism. The winning device within the win- ning block is the global winning device for the SEARCH operation.

Table 47. Hit/Miss Assumption Figure 74. Hardware Diagram for a Table with 31 Devices

Figure 75. Hardware Diagram for a Block of Up to Eight Devices

Figure 76. x288 Table with 31 Devices

Figure 77. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 78. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 79. Timing Diagram for the Globally Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 80. Timing Diagram for Devices Below the Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 81. Timing Diagram for Devices Above the Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 82. Timing Diagram for the Globally Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 83. Timing Diagram for Devices Below the Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 84. Timing Diagram for Devices Above the Winning Device in Block Number 3 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 85. Timing Diagram for the Globally Winning Device in Block Number 3 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 86. Timing Diagram for Devices Below the Winning Device in Block Number 3 (except Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 87. Timing Diagram of the Last Device in Block Number 3 (Device 30 in the Table) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

  1. Each bit in LHO[1:0] is the same logical signal.
  2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
  3. Each bit in BHO[2:0] is the same logical signal.

Figure 88. Timing Diagram for Mixed SEARCH (One Device)

Figure 89. Multi-Width Configurations Example Table 50. Searches with CFG_L Set HIGH the device with the LDEV Bit set.

Bit [0] of each 72-bit data location specifies wheth- er an entry in the database is occupied. If all the entries in a device are occupied, the device as- serts FULO signal to inform the downstream de- vices that it is full. The result of this communication between depth- cascaded devices determines the global FULL signal for the entire table. The FULL signal in the last device determines the fullness of the depth- cascaded table. In a depth-cascaded table, only a single device will learn the entry through the application of a LEARN Instruction. The determination of which device is going to learn is based on the FULI and FULO sig- nalling between the devices. The first non-full de- vice learns the entry by storing the contents of the specified comparand registers to the location(s) pointed to by NFA. In a x72-configured table the LEARN command writes a single 72-bit location. In a x144-config- ured table the LEARN command writes the next even and odd 72-bit locations. In 144-bit mode, Bit[0] of the even and odd 72-bit locations is '0,' which indicates they are cascaded empty, or '1,' which indicates they are occupied. The global FULL signal indicates to the Table Con- troller (the host ASIC) that all entries within a block are occupied and that no more entries can be learned. The M7040N updates the signal after each WRITE or LEARN command to a data array. The LEARN command generates a WRITE cycle to the external SRAM, also using the NFA register as part of the SRAM address (see SRAM AD- DRESSING, page 128). The LEARN command is supported on a single block containing up to eight devices if the table is configured either as a x72 or a x144. The LEARN command is not supported for x288-configured ta- bles. LEARN is a pipelined operation and lasts for two CLK cycles, as shown in Figure 90, page 121 where TLSZ = 00, and Figure 91, page 122 and Figure 92, page 123 where TLSZ = 01 (which as- sume the device performing the LEARN operation is not the last device in the table and has its LRAM Bit set to '0.' Note:The OE_L for the device with the LRAM Bit set goes high for two cycles for each LEARN (one during the SRAM WRITE cycle, and one the cycle before). The latency of the SRAM WRITE cycle from the second cycle of the Instruction is shown in Table 51, page 123. The sequence of operation is as follows: – Cycle 1A: The host ASIC applies the LEARN In- struction on the CMD[1:0], using CMDV = 1. The CMD[5:2] field specifies the index of the comparand register pair that will be written in the data array in the 144-bit-configured table. For a LEARN in a 72-bit-configured table, the even-numbered comparands specified by this index will be written. CMD[8:6] carries the bits that will be driven on SADR[23:21] in the SRAM WRITE cycle. – Cycle 1B: The host ASIC continues to drive CMDV to '1,' CMD[1:0] to '11,' and CMD[5:2] with the comparand pair index. CMD[6] must be set to '0' if the LEARN is being performed on a 72-bit-configured table, and to '1' if the LEARN is being performed on a 144-bit-configured ta- ble. – Cycle 2:The host ASIC drives the CMDV to '0.' At the end of Cycle 2, a new instruction can be- gin. The latency of the SRAM WRITE is the same as the search to the SRAM READ Cycle.

Figure 90. Timing Diagram of LEARN: TLSZ = 00

Figure 91. Timing Diagram of LEARN: TLSZ = 01 (Except on the Last Device)

Figure 92. Timing Diagram of LEARN on Device 7: TLSZ = 01 Table 51. Latency of SRAM WRITE Cycle from Second Cycle of LEARN Instruction

Figure 93. Depth-Cascading to Form a Single Block

Figure 94. Depth-Cascading Four Blocks

Figure 95. “FULL” Generation in a Cascaded Table

page 8 for more information). Table 52. Generating an SRAM Bus Address grammed in the device Configuration Register. grammed in the Configuration Register. by the selected device performing the access. grammed in the device Configuration Register. grammed in the configuration register. the only device to be accessed. struction on the CMD[1:0], using CMDV = 1. which the ID[4:0] matches the DQ[25:21] lines. SADR[23:21] on CMD[8:6] in this cycle.

DQ[71:0] and drives ACK from High-Z to low. a 3-state condition; it drives ACK low. Figure 96. SRAM READ Access for One Device

SRAM READ with a Table of Up to Eight Devices The following explains the SRAM READ operation completed through a table of up to eight devices using the following parameters: TLSZ = 01. Figure 97, page 131 diagrams a block of eight devices. The following assumes that SRAM access is suc- cessfully achieved through M7040N Device 0. Fig- ure 98, page 132 and Figure 99, page 133 show timing diagrams for Device 0 and Device 7, re- spectively. – Cycle 1A:The host ASIC applies the READ In- struction on the CMD[1:0] using CMDV = 1. The DQ Bus supplies the address, with DQ[20:19] set to '10' to select the SRAM address. The host ASIC selects the device for which ID[4:0] match- es the DQ[25:21] lines. During this cycle the host ASIC also supplies SADR[23:21] on CMD[8:6]. – Cycle 1B:The host ASIC continues to apply the READ Instruction on the CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. – Cycle 2:The host ASIC floats DQ[71:0] to a 3- state condition. – Cycle 3:The host ASIC keeps DQ[71:0] in a 3- state condition. – Cycle 4: T h es e l e c t e dd e v i c es t a r t st od r i v e DQ[71:0]. – Cycle 5:The selected device continues to drive DQ[71:0] and drives ACK from high-Z to low – Cycle 6:The selected device drives the READ address on SADR[23:0]. It also drives ACK high, CE_L low, WE_L high, and ALE_L low. – Cycle 7: The selected device drives CE_L, ALE_L, WE_L, and the DQ Bus in a 3-state con- dition. It continues to drive ACK low. At the end of Cycle 7, the selected device floats ACK in 3-state condition and a new command can begin.

Figure 97. Table with Eight Devices

Figure 98. SRAM READ Through Device 0 in a Block of Eight Devices

Figure 99. SRAM READ Timing for Device 7 in a Block of Eight Devices

SRAM READ with a Table of Up to 31 Devices The following explains the SRAM READ operation accomplished through a table of up to 31 devices, using the following parameters: TLSZ = 10. The di- agram of such a table is shown in Figure 100, page 135. The following assumes that SRAM access is being accomplished through M7040N Device 0 and that Device 0 is the selected device. Figure 101, page 136 and Figure 102, page 137 show the timing di- agrams for Device 0 and Device 30, respectively. – Cycle 1A:The host ASIC applies the READ In- struction to CMD[1:0] using CMDV = 1. The DQ Bus supplies the address, with DQ[20:19] set to '10,' to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. During this cycle, the host ASIC also supplies SADR[23:21] on CMD[8:6]. – Cycle 1B:The host ASIC continues to apply the READ Instruction to CMD[1:0] using CMDV = 1. The DQ Bus supplies the address, with DQ[20:19] set to '10,' to select the SRAM ad- dress. – Cycle 2:The host ASIC floats DQ[71:0] to a 3- state condition. – Cycle 3:The host ASIC keeps DQ[71:0] in a 3- state condition. – Cycle 4: T h es e l e c t e dd e v i c es t a r t st od r i v e DQ[71:0]. – Cycles 5 to 6:The selected device continues to drive DQ[71:0]. – Cycle 7:The selected device continues to drive DQ[71:0] and drives an SRAM READ cycle. – Cycle 8:The selected device drives ACK from Zt ol o w . – Cycle 9: The selected device drives ACK to high. – Cycle 10:The selected device drives ACK from high to low. At the end of Cycle 10, the selected device floats ACK in a 3-state condition.

Figure 100. Table of 31 Devices Made of Four Blocks

Figure 101. SRAM READ Through Device 0 in a Bank of 31 Devices (Device 0 Timing)

Figure 102. SRAM READ Through Device 0 in a Bank of 31 Devices (Device 30 Timing)

SRAM WRITE with a Table of One Device SRAM WRITE enables WRITE access to the off- chip SRAM that contains associative data. The la- tency from the second cycle of the WRITE Instruc- tion to the address appearing on the SRAM Bus is the same as the latency of the SEARCH Instruc- tion, and will depend on the TLSZ value parameter programmed in the device configuration register. The following explains the SRAM WRITE opera- tion accomplished with a table of only one device of the following parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and LDEV = 1. Figure 103, page 139 shows the timing diagram. For the following description the selected device refers to the only device in the table as it is the only device that will be accessed. – Cycle 1A:The host ASIC applies the WRITE In- struction on CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also sup- plies SADR[23:21] on CMD[8:6] in this cycle. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. – Cycle 1B:The host ASIC continues to apply the WRITE Instruction on CMD[1:0], using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. – Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the M7040N device. – Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the M7040N device. At the end of Cycle 3, a new command can begin. The WRITE is a pipelined operation. The WRITE Cycle appears at the SRAM Bus, however, with the same latency as that of a SEARCH Instruction, as measured from the second cycle of the WRITE command.

Figure 103. SRAM WRITE Access for One Device

S R A MW R I T Ew i t haT a b l eo fU pt oE i g h tD e v i c e s The following explains the SRAM WRITE opera- tion done through a table(s) of up to eight devices with the following parameters (TLSZ = 01). The di- agram of such a table is shown in Figure 104, page 141. The following assumes that SRAM access is done through M7040N Device 0. Figure 105, page 142 and Figure 106, page 143 show the timing dia- gram for Device 0 and Device 7, respectively. – Cycle 1A:The host ASIC applies the WRITE In- struction on CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also sup- plies SADR[23:21] on CMD[8:6] in this cycle. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. – Cycle 1B:The host ASIC continues to apply the W R I T EI n s t r u c t i o no nC M D [ 1 : 0 ]u s i n gC M D V= 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM ad- dress. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. – Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the M7040N device. – Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the M7040N device. At the end of cycle 3, a new command can begin. The WRITE is a pipelined operation. The WRITE Cycle appears at the SRAM Bus, however, with the same latency as that of a SEARCH Instruction, as measured from the second cycle of the WRITE command.

Figure 104. Table with Eight Devices

Figure 105. SRAM WRITE Through Device 0 in a Block of Eight Devices

Figure 106. SRAM WRITE Timing for Device 7 in a Block of Eight Devices

S R A MW R I T Ew i t hT a b l e ( s )o fU pt o3 1D e v i c e s The following explains the SRAM WRITE opera- tion done through a table(s) of up to 31 devices with the following parameters (TLSZ = 10). The di- agram of such table(s) is shown in Figure 107, page 145. The following assumes that SRAM ac- cess is done through M7040N Device 0– Device 0 is the selected device. Figure 108, page 146 and Figure 109, page 147 show the timing diagram for Device 0 and Device 30, respectively. – Cycle 1A:The host ASIC applies the WRITE In- struction on CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also sup- plies SADR[23:21] on CMD[8:6] in this cycle. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. – Cycle 1B:The host ASIC continues to apply the W R I T EI n s t r u c t i o no nC M D [ 1 : 0 ]u s i n gC M D V= 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM ad- dress. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. – Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the M7040N device. – Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the M7040N device. At the end of Cycle 3, a new command can begin. The WRITE is a pipelined operation. The WRITE Cycle appears at the SRAM Bus, however, with the same latency as that of a SEARCH Instruction, as measured from the second cycle of the WRITE command

Figure 107. Table of 31 Devices (Four Blocks)

Figure 108. SRAM WRITE Through Device 0 in a Bank of 31 Devices (Device 0 Timing)

Figure 109. SRAM WRITE Through Device 0 in a Bank of 31 Devices (Device 30 Timing)

definitions: TCK, TMS, TDI, TDO, and TRST_L. scribes the TAP Device ID Register. Table 53. Supported Operations Table 54. TAP Device ID Register the normal functional operation. test connectivity external to the device. using the boundary scan register to provide the I/O values. Revision Number.This is the current device revision number. Part # [27:12] 0000 0000 0000 0100 This is the part number for this device.

Table 55. Ordering Information Scheme please contact the ST Sales Office nearest to you.

Figure 110. PBGA-ZA – 388-ball Plastic Ball Grid Array Package Outline Note: Drawing is not to scale.

1.17 REF

Table 56. PBGA-ZA – 388-ball Plastic Ball Grid Array Package Mechanical Data of package body or integral heatslug.

  1. A distinguished feature is allowable on the bottom surface of the package to identify the terminal “b” corner.
  2. Exact shape of each corner is optional.

Table 57. Connections

AA24 VDD 1.5V AC26 VDDQ (2) 2.5/3.3V AA25 CMD[3] Input AC3 VDD 1.5V AC4 V SS Ground AE10 DQ[44] I/O AC5 V SS Ground AE11 DQ[42] I/O AC6 V SS Ground AE12 DQ[38] I/O AC7 V SS Ground AE13 VDDQ (2) 2.5/3.3V AC8 V SS Ground AE14 DQ[32] I/O AC9 V SS Ground AE15 DQ[28] I/O AD1 RST_L Input AE16 DQ[26] I/O AD10 DQ[46] I/O AE17 VDDQ (2) 2.5/3.3V AD11 VDD 1.5V AE18 DQ[18] I/O AD12 VDD 1.5V AE19 DQ[12] I/O AD13 VDD 1.5V AE2 VSS Ground AD14 VDD 1.5V AE20 DQ[10] I/O AD15 VDD 1.5V AE21 DQ[06] I/O AD16 VDD 1.5V AE22 VDDQ (2) 2.5/3.3V AD17 DQ[20] I/O AE23 DQ[00] I/O AD18 DQ[16] I/O AE24 V DDQ (2) 2.5/3.3V AD19 NC4 No Connect AE25 VSS Ground AD2 VDDQ (2) 2.5/3.3V AE26 CLK_TUNE[1] (1) Note 1 AD20 VDD 1.5V AE3 DQ[70] I/O AD21 VDD 1.5V AE4 VDDQ (2) 2.5/3.3V AD22 VDD 1.5V AE5 DQ[64] I/O AD23 VDD 1.5V AE6 DQ[60] I/O AD24 VDD 1.5V AE7 DQ[58] I/O AD25 CMD[8] Input AE8 DQ[54] I/O AD26 CMD[7] Input AE9 DQ[50] I/O AD3 VDD 1.5V AF1 TEST_CO No Connect AD4 VDD 1.5V AF10 VDDQ (2) 2.5/3.3V AD5 VDD 1.5 V AF11 DQ[40] I/O AD6 VDD 1.5V AF12 DQ[36] I/O AD7 VDD 1.5V AF13 DQ[34] I/O AD8 NC3 No Connect AF14 DQ[30] I/O AD9 VDDQ (2) 2.5/3.3V AF15 VDDQ (2) 2.5/3.3V Package Ball Number Signal Name Signal Type Package Ball Number Signal Name Signal Type

AE1 TEST Ground AF16 DQ[24] I/O AF17 DQ[22] I/O B23 TEST_PB Input AF18 DQ[14] I/O B24 CFG_L Input AF19 V DDQ (2) 2.5/3.3V B25 VSS Ground AF2 CLK_TUNE[2] (1) Note 1 B26 SADR[00] Output AF20 DQ[08] I/O B3 DQ[69] I/O AF21 DQ[04] I/O B4 DQ[65] I/O AF22 DQ[02] I/O B5 DQ[61] I/O AF23 SSV Output-T B6 DQ[59] I/O AF24 SSF Output-T B7 DQ[55] I/O AF25 CMD[10] Input B8 V DDQ (2) 2.5/3.3V AF26 CMD[9] Input B9 DQ[47] I/O AF3 DQ[68] I/O C1 TCK Input AF4 DQ[66] I/O C10 VDDQ (2) 2.5/3.3V AF5 DQ[62] I/O C11 VDD 1.5V AF6 VDDQ (2) 2.5/3.3V C12 VDD 1.5V AF7 DQ[56] I/O C13 VDD 1.5V AF8 DQ[52] I/O C14 VDD 1.5V AF9 DQ[48] I/O C15 VDD 1.5V B1 TDI Input C16 VDD 1.5V B10 DQ[45] I/O C17 DQ[19] I/O B11 DQ[39] I/O C18 DQ[13] I/O B12 VDDQ (2) 2.5/3.3V C19 NC7 No Connect B13 DQ[33] I/O C2 TMS Input B14 DQ[29] I/O C20 VDD 1.5V B15 DQ[27] I/O C21 VDD 1.5V B16 DQ[23] I/O C22 VDD 1.5V B17 VDDQ (2) 2.5/3.3V C23 VDD 1.5V B18 DQ[15] I/O C24 VDD 1.5V B19 DQ[11] I/O C25 SADR[01] Output B2 V SS Ground C26 VDDQ (2) 2.5/3.3V B20 DQ[07] I/O C3 VDD 1.5V B21 VDDQ (2) 2.5/3.3V C4 VDD 1.5V B22 DQ[01] I/O C5 VDD 1.5V Package Ball Number Signal Name Signal Type Package Ball Number Signal Name Signal Type

C6 VDD 1.5V E24 VDD 1.5V C7 VDD 1.5V E25 SADR[05] Output C8 NC8 No Connect E26 SADR[04] Output C9 DQ[49] I/O E3 VDD 1.5V D1 TRST_L Input E4 VSS Ground D10 VSS Ground F1 ID[1] Input D11 VDD 1.5V F2 ID[2] Input D12 VDD 1.5V F23 VSS Ground D13 VDD 1.5V F24 VDD 1.5V D14 VDD 1.5V F25 SADR[06] Output D15 VDD 1.5V F26 VDDQ (2) 2.5/3.3V D16 VDD 1.5V F3 VDD 1.5V D17 V SS Ground F4 VSS Ground D18 V SS Ground G1 ID[3] Input D19 VSS Ground G2 ID[4] Input D2 TDO Output-T G23 VSS Ground D20 V SS Ground G24 VDD 1.5V D21 V SS Ground G25 SADR[08] Output D22 VSS Ground G26 SADR[07] Output D23 VSS Ground G3 VDD 1.5V D24 VDD 1.5V G4 VSS Ground D25 SADR[03] Output H1 LHI[0] Input D26 SADR[02] Output H2 LHI[1] Input D3 VDD 1.5V H23 VSS Ground D4 V SS Ground H24 NC6 No Connect D5 VSS Ground H25 VDDQ (2) 2.5/3.3V D6 V SS Ground H26 SADR[09] Output D7 VSS Ground H3 NC1 No Connect D8 VSS Ground H4 VSS Ground D9 V SS Ground J1 LHI[2] Input E1 ID[0] Input J2 LHI[3] Input E2 VDDQ (2) 2.5/3.3V J23 VSS Ground E23 V SS Ground J24 SADR[11] Output J25 SADR[12] Output M2 BHI[0] Input Package Ball Number Signal Name Signal Type Package Ball Number Signal Name Signal Type

J26 SADR[10] Output M23 VDD 1.5V J3 VDDQ (2) 2.5/3.3V M24 VDD 1.5V J4 V SS Ground M25 VDDQ (2) 2.5/3.3V K1 LHI[6] Input M26 SADR[17] Output K2 LHI[4] Input M3 VDD 1.5V K23 V SS Ground M4 VDD 1.5V K24 SADR[13] Output N1 BHI[1] Input K25 VDDQ (2) 2.5/3.3V N11 VSS Ground K26 SADR[14] Output N12 VSS Ground K3 LHI[5] Input N13 V SS Ground K4 V SS Ground N14 VSS Ground L1 LHO[0] Output-T N15 VSS Ground L11 V SS Ground N16 VSS Ground L12 V SS Ground N2 BHI[2] Input L13 V SS Ground N23 VDD 1.5V L14 V SS Ground N24 VDD 1.5V L15 V SS Ground N25 SADR[19] Output L16 V SS Ground N26 SADR[18] Output L2 LHO[1] Output-T N3 VDD 1.5V L23 VDD 1.5V N4 VDD 1.5V L24 VDD 1.5V P1 BHO[0] Output-T L25 SADR[15] Output P11 VSS Ground L26 SADR[16] Output P12 VSS Ground L3 VDD 1.5V P13 VSS Ground L4 VDD 1.5V P14 VSS Ground M1 VDDQ (2) 2.5/3.3V P15 VSS Ground M11 V SS Ground P16 VSS Ground M12 V SS Ground P2 MULTI_HIT Output-T M13 V SS Ground P23 VDD 1.5V M14 V SS Ground P24 VDD 1.5V M15 V SS Ground P25 SADR[21] Output M16 V SS Ground P26 SADR[20] Output P3 VDD 1.5V U24 OE_L Output-T P4 VDD 1.5V U25 PHS_L Input Package Ball Number Signal Name Signal Type Package Ball Number Signal Name Signal Type

Note: 1. CLK_TUNE[3:0] should be programmed to 100%. 2. All VDDQ pins should be set to 2.5 or 3.3V. R1 VDDQ (2) 2.5/3.3V U26 CLK1X/CLK2X Input R11 VSS Ground U3 FULI[1] Input R12 VSS Ground U4 VSS Ground R13 V SS Ground V1 FULI[2] Input R14 VSS Ground V2 FULI[3] Input R15 VSS Ground V23 VSS Ground R16 V SS Ground V24 CE_L Output-T R2 BHO[1] Output-T V25 VDDQ (2) 2.5/3.3V R23 VDD 1.5V V26 WE_L Output-T R24 VDD 1.5V V3 FULI[4] Input R25 SADR[22] Output V4 VSS Ground R26 VDDQ (2) 2.5/3.3V W1 VDDQ (2) 2.5/3.3V R3 VDD 1.5V W2 FULI[5] Input R4 VDD 1.5V W23 VSS Ground T1 BHO[2] Output-T W24 NC5 No Connect T11 V SS Ground W25 CMDV Input T12 VSS Ground W26 ALE_L Output-T T13 VSS Ground W3 NC2 No Connect T14 VSS Ground W4 VSS Ground T15 V SS Ground Y1 FULI[6] Input T16 VSS Ground Y2 FULO[0] Output-T T2 V SS Ground Y23 VSS Ground T23 VDD 1.5V Y24 VDD 1.5V T24 VDD 1.5V Y25 CMD[1] Input T25 CLK_MODE Input Y26 CMD[0] Input T26 SADR[23] Output Y3 VDD 1.5V T3 VDD 1.5V Y4 VSS Ground T4 VDD 1.5V U1 FULI[0] Input U2 VDDQ (2) 2.5/3.3V U23 VSS Ground Package Ball Number Signal Name Signal Type Package Ball Number Signal Name Signal Type

REVISION HISTORY

Table 58. Document Revision History

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