M7020R-050ZA1T

M7020R STMICROELECTRONICS | Alldatasheet

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Technical content

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Figure 1. 272-ball PBGA Package

Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, Up to 8 Devices (Table 28.) 46

Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 272-bit, Up to 8 Devices . . . . 99

Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 272-bit, Up to 31 Devices . . 115

Table 2. Signal Names

1. “CLK” is an internal clock signal. Any reference to “CLK Cycles” means one cycle of CLK.
2. ACK and EOT Signals require a weak, external pull-down resistor of 47 KΩ or 100 KΩ .

Figure 3. Connections

Figure 4. M7020R Block Diagram

Table 3. Absolute Maximum Ratings Note: 1.Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

tions when using the quoted parameters. Table 4. DC and AC Measurement Conditions Note: 1. Maximum allowable applies to overshoot only (VDDQ is 3.3V supply).

1. Minimum allowable applies to undershoot only.

Table 5. Capacitance Note: 1. Effective capacitance measured with power supply. Sampled only, not 100% tested. Table 6. DC Characteristics Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VDD = 1.5V.

Figure 8. AC Timing Waveforms with CLK2X

Table 7. AC Timing Parameters with CLK2X Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VDD = 1.8V.

1. Values are based on 50% signal levels.
2. Based on an AC load of CL = 30pF (see Figure 5, Figure 6, and Figure 7, page 14).
3. These parameters are sampled and not 100% tested, and are based on an AC load of 5pF.

The following subsections contain command (CMD and DQ Bus (command and databus), data- base entry, arbitration logic, pipeline, and SRAM control, and full logic descriptions. CMD Bus and DQ Bus CMD[8:0] carries the CMD and its associated pa- rameter. DQ[67:0] is used for data transfer to and from the database entries, which comprise a data and a mask field that are organized as data and mask arrays. The DQ Bus carries the SEARCH data (of the data and mask arrays and internal reg- isters) during the SEARCH command as well as the address and data during READ and/or WRITE operations. The DQ Bus can also carry the ad- dress information for the flow-through accesses to the external SRAMs and/or SSRAMs. Database Entry (Data Array and Mask Array) Each database entry comprises a data and a mask field. The resultant value of the entry is ’1,' ’0,’ or ’X (don’t care),’ depending on the value in the data and mask bits. The on-chip priority encoder se- lects the first matching entry in the database that is nearest to location '0.' Arbitration Logic When multiple Search Engines are cascaded to create large databases, the data being searched is presented to all search engines simultaneously in the cascaded system. If multiple matches occur within the cascaded devices, arbitration logic on the search engines will enable the winning device (with a matching entry that is closest to address “0” of the cascaded database) to drive the SRAM bus. Pipeline and SRAM Control Pipeline latency is added to give enough time to a cascaded system’s arbitration logic to determine the device that will drive the index of the matching entry on the SRAM bus. Pipeline logic adds laten- cy to both the SRAM access cycles and the SSF and SSV signals to align them to the host ASIC re- ceiving the associated data. Full Logic Bit[0] in each of the 68-bit entries has a special purpose for the LEARN command (0 = empty, 1 = full). When all the data entries have bit[0] = 1, the database asserts the FULL Flag, indicating all the search engines in the depth-cascaded array are full.

Master Clock (CLK2X).M7020R samples all the data and control pins on the positive edge of CLK2X. All signals are driven out of the device on the rising edge of CLK2X (when PHS_L is low). Phase (PHS_L). This signal runs at half the fre- quency of CLK2X and generates an internal CLK from CLK2X see Figure 9, page 20. Test Input (TEST - for Cypress Semiconductor Use Only).This signal should be connected to ground. Reset (RST_L).Driving RST_L low initializes the device to a known state. CMD and DQ Bus CMD Bus (CMD[8:0]. [1:0] specifies the com- mand; [8:2] contains the CMD parameters. The descriptions of individual commands explains the details of the parameters. The encoding of com- mands based on the [1:0] field are: – 00: PIO READ – 01: PIO WRITE – 10: SEARCH –1 1 : L E A R N CMD Valid ( CMDV) . Qualifies the CMD bus: – 0: No Command – 1: Command Address/Data Bus (DQ[67:0]). This signal carries the READ and WRITE address and data during register, data, and mask array operations. It car- ries the compare data during SEARCH opera- tions. It also carries the SRAM address during SRAM PIO accesses. READ Acknowledge (ACK). This signal indi- cates that valid data is available on the DQ Bus during register, data, and mask array READ oper- ations, or the data is available on the SRAM data bus during SRAM READ operations. Note: ACK Signals require a weak external pull- down resistor such as 47 or 100 KΩ . End of Transfer (EOT).This signal indicates the end of burst transfer to the data or mask array dur- ing READ or WRITE burst operations. Note: EOT Signals require a weak external pull- down resistor such as 47 KΩ or 100 KΩ . SEARCH Successful Flag (SSF).When assert- ed, this signal indicates that the device is the glo- bal winner in a SEARCH operation. SEARCH Successful Flag Valid (SSV).When asserted, this signal qualifies the SSF signal. SRAM Interface SRAM Address (SADR[21:0]). This bus con- tains address lines to access off-chip SRAMs that contain associative data. See Table 50, page 127 for the details of the generated SRAM address. In a database of multiple M7020Rs, each corre- sponding bit of SADR from all cascaded devices must be connected. SRAM Chip Enable (CE_L). This is chip enable control for external SRAMs. In a database of mul- tiple M7020Rs, CE_L of all cascaded devices must be connected. This signal is then driven by only one of the devices. SRAM Write Enable (WE_L).This is write en- able control for external SRAMs. In a database of multiple M7020Rs, WE_L of all cascaded devices must be connected together. This signal is then driven by only one of the devices. SRAM Output Enable (OE_L). This is output en- able control for external SRAMs. Only the last de- vice drives this signal (with the LRAM bit set). Address Latch Enable (ALE_L).When this sig- nal is low, the addresses are valid on the SRAM Address Bus. In a database of multiple M7020Rs, the ALE_L of all cascaded devices must be con- nected. This signal is then driven by only one of the devices. Cascade Interface Local Hit In (LHI[6:0]).These pins depth-cas- cade the device to form a larger table size. One signal of this bus is connected to the LHO[1] or LHO[0] of each of the upstream devices in a block. All unused LHI pins are connected to a logic '0.' (For more information, see DEPTH-CASCADING, page 122.) Local Hit Out (LHO[1:0]).LHO[1] and LHO[0] are the same logical signal. LHO[1] or LHO[0] is connected to one input of the LHI bus of up to four downstream devices in a block of up to eight de- vices. (For more information, see DEPTH-CAS- CADING, page 122.) Block Hit In (BHI[2:0]).Inputs from the previous BHO[2:0] are tied to the BHI[2:0] of the current de- vice. In a four-block system, the last block can contain only seven devices because the ID code 11111 is used for broadcast access. Block Hit Out (BHO[2:0]).These outputs from the last device in a block are connected to the BHI[2:0] inputs of the devices in the downstream blocks. Full In (FULI[6:0]).Each signal in this bus is con- nected to FULO[0] or FULO[1] of an upstream de- vice to generate the FULL signal for the depth- cascaded block.

scribed in the following subsections. Table 8. Register Overview 32–47 MASKS RW 8 Global Mask Registers Array. 48–55 SSR0–7 R 8 SEARCH Successful Index Registers. 56 COMMAND RW Command Register. 57 INFO R Information Register. 58 RBURREG RW Burst Read Register. 59 WBURREG RW Burst Write Register. 60 NFA R Next Free Address Register.

Table 9. SEARCH-Successful Register (SSR) Description

Table 10. Command Register Field Descriptions by the following number of CLK cycles. for the SSF and SSV signals. OE_L is always driven by the device for which this bit is set.

Table 11. Information Register Field Descriptions Note: 1. This field may change in future versions. Bits [10:9] apply to configuring the 1st quadrant in the address space. for each revision of the device. Implementation [6:4] 001 This is the M7020R implementation number. Device ID [11:8] 0001 or 0010 This is the Device Identification Number. Device ID [15:13] 00000100 This is the Device Identification Number.

programmed before burst READ (see Table 12). '1' to indicate full/empty status. (e.g., '10' or '01' settings are invalid). Table 12. Read Burst Register Description Table 13. Write Burst Register Description Table 14. NFA Register field must be reinitialized for the next operation. must be reinitialized for the next operation.

60 Reserved Index

ue of the CFG bits in the command register. successful search during a SEARCH operation. drive(s) the SRAM Bus, SSF, and SSV signals. and mask array addressing procedure. Figure 12. M7020R Database Width Configuration

16 K 8 K

Table 15. Bit Position Match Figure 13. Multi-width Configuration Example Figure 14. M7020R Data and Mask Array Addressing

Table 16. Command Codes Table 17. Command Parameters Note: 1. The 272-bit-configured devices or 272-bit-configured quadrants within devices do not support the LEARN Instruction.

00 READ Reads one of the following: data array, mask array, device registers, or external

01 WRITE Writes one of the following: data array, mask array, device registers, or external

10 SEARCH Searches the data array for a desired pattern using the specified register from the

global mask register array and local mask associated with each data cell.

11 LEARN

the NFA register) using the LEARN Instruction.

The READ can be a single read of a data array, a mask array, an SRAM, or a register location (CMD[2] = 0). It can be a burst READ (CMD[2] = 1) or mask array locations using an internal auto-in- crementing address register (RBURADR). Table 18, page 32 describes each type of READ com- mand. A single-location READ operation lasts six cycles, as shown in Figure 15, page 31. The burst READ adds two cycles for each successive READ. The SADR[21:20] bits supplied in the READ Instruction Cycle A drive SADR[21:20] signals during the READ of an SRAM location. The single READ operation takes six CLK cycles, in the following sequence: – Cycle 1: The host ASIC applies the READ In- struction on the CMD[1:0] (CMD[2] = 0), using CMDV = 1, and the DQ Bus supplies the ad- dress, as shown in Table 19, page 32 and Table 20, page 33. The host ASIC selects the M7020R for which ID[4:0] matches the DQ[25:21] lines. If the DQ[25:21] = 11111, the host ASIC selects the M7020R with the LDEV Bit set. The host ASIC also supplies SADR[21:20] on CMD[8:7] in Cycle A of the READ Instruction if the READ is directed to the external SRAM. – Cycle 2: The host ASIC floats DQ[67:0] to 3- state condition. – Cycle 3: The host ASIC keeps DQ[67:0] in 3- state condition. – Cycle 4: The selected device starts to drive the DQ[67:0] Bus and drives the ACK signal from Z to low. – Cycle 5: The selected device drives the read data from the addressed location on the DQ[67:0] Bus and drives the ACK signal high. – Cycle 6: The selected device floats DQ[67:0] to 3-state condition and drives the ACK signal low. At the termination of Cycle 6, the selected device releases the ACK line to 3-state condition. The READ Instruction is complete, and a new opera- tion can begin. Note: The latency of the SRAM READ will be dif- ferent than the one described above (see SRAM PIO Access, page 126). Table 19, page 32 lists and describes the format of the READ address for a data array, mask array, or SRAM. In a burst READ operation, the READ lasts 4 + 2n CLK-cycles (where “n” stands for the number of accesses in the burst specified by the BLEN field of the RBURREG). Table 20, page 33 describes the READ address format for the internal registers. Figure 16, page 31 illustrates the timing diagram for the burst READ of the data or mask array. This operation assumes that the host ASIC has pro- grammed the RBURREG with the starting address (ADR) and the length of transfer (BLEN) before ini- tiating the burst READ command. – Cycle 1: The host ASIC applies the READ In- struction on the CMD[1:0] (CMD[2] = 1), using CMDV=1 and the address supplied on the DQ Bus, as shown in Table 21, page 33. The host ASIC selects the M7020R for which ID[4:0] matches the DQ[25:21] lines. If the DQ[25:21] = 11111, the host ASIC selects the M7020R with the LDEV Bit set. – Cycle 2: The host ASIC floats DQ[67:0] to the 3- state condition. – Cycle 3: The host ASIC keeps DQ[67:0] in the 3-state condition. – Cycle 4: The selected device starts to drive the DQ[67:0] Bus and drives ACK and EOT from Z to low. – Cycle 5: The selected device drives the READ data from the addressed location on the DQ[67:0] Bus and drives the ACK signal high. Note: Cycles four and five repeat for each addi- tional access until all the accesses specified in the burst length (BLEN) field of RBURREG are complete. On the last transfer, the M7020R drives the EOT signal high. – Cycle (4 + 2n): The selected device drives the DQ[67:0] to 3-state condition and drives the ACK and the EOT signals low. At the termination of Cycle 4 + 2n, the selected de- vice floats the ACK line to 3-state condition. The burst READ Instruction is complete, and a new op- eration can begin (see Table 21, page 33 for burst READ address formats).

Table 18. READ Command Parameters Table 19. Data and Mask Array, SRAM Read Address Format Note: 1.“|” stands for Logical OR operation. “{ }” stands for concatenation operator.

0 Single Read Reads a single location of the data array, mask array, external SRAM,

or device registers. All access information is applied on the DQ Bus.

1 Burst Read

auto-increments the address for each access. All other access information is applied on the DQ Bus. address of data array location. address of mask array location.

Table 20. READ Address Format for Internal Registers Table 21. READ Address Format for Data and Mask Arrays

1. The burst WRITE adds one extra cycle for

CMD[9] to '0' for the normal WRITE. cle, another operation can begin.

register) of the selected device. the BLEN field of the WBURREG). a new instruction can begin. Figure 17. Single Location WRITE Cycle Timing

Figure 18. Burst WRITE of the Data and Mask Arrays (BLEN = 4) Table 22. (Single) WRITE Address Format for Data and Mask Arrays or SRAM Note: 1.“|” stands for Logical OR operation. “{ }” stands for concatenation operator. address of the data array location. address of the mask array location. address of the data SRAM location.

Table 23. WRITE Address Format for Internal Registers Table 24. WRITE Address Format for Data and Mask Array (Burst Write) to '1' in the command register. single 68-bit SEARCH command. grammed with the same value.

Figure 20. Timing Diagram for a 68-bit Configuration SEARCH for One Device

Figure 21. x68 Table with One Device Table 25. Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, 1 Device Table 26. Shift of SSF and SSV from SADR

Table 27. Hit/Miss Assumption Figure 22. Hardware Diagram for a Table with Eight Devices

Figure 23. x68 Table with Eight Devices

Figure 24. 68-bit SEARCH For Device 0 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.

Figure 25. 68-bit SEARCH For Device 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.

Figure 26. 68-bit SEARCH For Device 7 (Last Device) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.

on SADR[21:20] by this device if it has a hit. grammed with the same value. ed by the GMR Index in the command’s Cycle A. LEARN command only in the first non-full device. be the default driver for such missed cycles. Table 30. Hit/Miss Assumption

Figure 27. Hardware Diagram for a Table with 31 Devices

Figure 28. Hardware Diagram for a Block of Up To Eight Devices

Figure 29. x68 Table with 31 Devices

Figure 30. Each Device in Block Number 0 (Miss on Each Device) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 31. Each Device Above the Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 32. Globally Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 33. Devices Below the Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 34. Devices Above the Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 35. Globally Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 36. Devices Below the Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 37. Devices Above the Winning Device in Block Number 3 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 38. Globally Winning Device in Block Number 3 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 39. Devices Below the Winning Device in Block Number 3 (not Device 30 - Last Device) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 40. Device 6 in Block Number 3 (Device 30 in Depth-Cascaded Table) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Table 31. Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, Up to 31 Devices Table 32. Shift of SSF and SSV from SADR MAND CODES AND PARAMETERS, page 29). on SADR[21:20] by this device if it has a hit. SEARCH command ('10') on CMD[1:0]. data ([67:0]), compared to all odd locations.

Figure 42. Timing Diagram for a 136-bit SEARCH for One Device

Figure 43. x136 Table with One Device Table 33. Latency of SEARCH from Instruction to SRAM Access Cycle, 136-bit, 1 Device Table 34. Shift of SSF and SSV from SADR

Table 35. Hit/Miss Assumption Figure 44. Hardware Diagram for a Table with Eight Devices

Figure 45. x136 Table with Eight Devices

Figure 46. 136-bit SEARCH for Device Number 0 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.

Figure 47. 136-bit SEARCH for Device Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.

Figure 48. 136-bit SEARCH for Device Number 7 (Last Device) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.

MAND CODES AND PARAMETERS, page 29). SADR[21:20] by this device if it has a hit. compared against all odd locations. in a depth-cascaded table of more than one block. will be the default driver for such missed cycles. The SEARCH command is a pipelined operation. HLAT, as specified in Table 40, page 88. Table 38. Hit/Miss Assumption

Figure 49. Hardware Diagram for a Table with 31 Devices

Figure 50. Hardware Diagram for a Block of Up to Eight Devices

Figure 51. x136 Table with 31 Devices

Figure 52. Each Device in Block Number 0 (Miss on Each Device) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 53. Each Device Above the Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 54. Globally Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 55. Devices Below the Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 56. Devices Above the Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 57. Globally Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 58. Devices Below the Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 59. Devices Above the Winning Device in Block Number 3 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 60. Globally Winning Device in Block Number 3 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 61. Devices Below the Winning Device in Block Number 3 (not Device 30 - Last Device) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 62. Device 6 in Block Number 3 (Device 30 in Depth-Cascaded Table) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Table 39. Latency of SEARCH from Instruction to SRAM Access Cycle, 136-bit, Up to 31 Devices Table 40. Shift of SSF and SSV from SADR bits [271:136] of the data being searched. “1” in the four 68-bits-word page. bits [135:0] of the data being searched. Instruction is not supported for x272 tables. that apply to DQ data in Cycles C and D.

Figure 64. Timing Diagram for a 272-bit SEARCH for One Device

Figure 65. x272 Table with One Device Table 41. Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 272-bit, 1 Device Table 42. Shift of SSF and SSV from SADR

Cycles is shown in Table 44, page 99. specified in Table 45, page 99. Table 43. Hit/Miss Assumption

Figure 66. Hardware Diagram for a Table with Eight Devices

Figure 67. x272 Table with Eight Devices

Figure 68. 272-bit SEARCH for Device Number 0 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.

Figure 69. 272-bit SEARCH for Device Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.

Figure 70. 272-bit SEARCH for Device Number 7 (Last Device) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.

Table 44. Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 272-bit, Up to 8 Devices Table 45. Shift of SSF and SSV from SADR of eight devices is shown in Figure 72, page 102. LRAM = 1 and LDEV = 1 (Device 30 in this case). one device with the matching entry in each block.

The following is the sequence of operation for a single 272-bit SEARCH command (see COM- MAND CODES AND PARAMETERS, page 29). – Cycle A: The host ASIC drives the CMDV high and applies SEARCH command code ('10') on CMD[1:0] signals. CMD[5:3] signals must be driven with the index to the GMR pair used for bits [271:136] of the data being searched. DQ[67:0] must be driven with the 68-bit data ([271:204])to be compared to all locations “0” in the four 68-bit-word page. The CMD[2] signal must be driven to logic '1.' Note: CMD[2] = 1 signals that the search is a x272-bit search. CMD[8:7] is ignored in this cy- cle. – Cycle B: The host ASIC continues to drive the CMDV high and applies SEARCH command ('10') on CMD[1:0]. The DQ[67:0] is driven with the 68-bit data ([203:136]) to be compared to all locations '1' in the four 68-bits-word page. – Cycle C: The host ASIC drives the CMDV high and applies SEARCH command code ('10') on CMD[1:0] signals. CMD[5:3] signals must be driven with the index to the GMR pair used for the bits [135:0] of the data being searched. CMD[8:7] signals must be driven with the bits that will be driven by this device on SADR[21:20] if it has a hit. DQ[67:0] must be driven with the 68-bit data ([135:68]) to be com- pared to all locations “2” in the four 68-bit-word page. The CMD[2] signal must be driven to logic '0.' – Cycle D: The host ASIC continues to drive the CMDV high and continues to apply SEARCH command code ('10') on CMD[1:0]. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the Hit Flag (see SEARCH- Successful Registers (SSR[0:7]), page 23). The DQ[67:0] is driven with the 68-bit data ([67:0]) to be compared to all locations “3” in the four 68- bit-word page. CMD[5:2] is ignored because the LEARN Instruction is not supported for x272 ta- bles. Note: For 272-bit searches, the host ASIC must supply four distinct 68-bit data words on DQ[67:0] during Cycles A, B, C, and D. The GMR Index in Cycle A selects a pair of GMRs in each of the 31 devices that apply to DQ data in Cycles A and B. The GMR Index in Cycle C se- lects a pair of GMRs in each of the 31 devices that apply to DQ data in Cycles C and D. The logical 272-bit SEARCH operation is as shown in Figure 73, page 103. The entire table of 272-bit entries is compared to a 272-bit word K that is presented on the DQ Bus in Cycles A, B, C, and D of the command using the GMR and local mask bits. The GMR is the 272-bit word specified by the two pairs of GMRs selected by the GMR In- dexes in the command’s Cycles A and C in each of the 31 devices. The 272-bit word K that is pre- sented on the DQ Bus in Cycles A, B, C, and D of the command is compared to each entry in the ta- ble starting at location “0.” The first matching en- try’s location address, “L,” is the winning address that is driven as part of the SRAM address on the SADR[21:0] lines (see SRAM ADDRESSING, page 126). Note: The matching address is always going to be location “0” in a four-entry page for 272-bit search (two LSBs of the matching index will be '00'). The SEARCH command is a pipelined operation and executes a search at one-fourth the rate of the frequency of CLK2X for 272-bit searches in x272- configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 272-bit SEARCH command (measured in CLK cycles) from the CLK2X cycle that contains Cycles C and D shown in Table 47, page 115. The latency of a SEARCH from command to SRAM access cycle is 6 for only a single device in the table and TLSZ = 10. In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 48, page 115 The 272-bit SEARCH operation is pipelined and executes as follows: – Four cycles from the last cycle of the SEARCH command each of the devices knows the out- come internal to it for that operation. – In the fifth cycle from the SEARCH command, the devices in a block (which is less than or equal to eight devices resolving the winner with- in them using an LHI[6:0] and LHO[1:0] signal- ling mechanism) arbitrate for a winner. – In the sixth cycle after the SEARCH command, the blocks of devices resolve the winning block through a BHI[2:0] and BHO[2:0] signalling mechanism. The winning device within the win- ning block is the global winning device for the SEARCH operation.

Table 46. Hit/Miss Assumption Figure 71. Hardware Diagram for a Table with 31 Devices

Figure 72. Hardware Diagram for a Block of Up to Eight Devices

Figure 73. x272 Table with 31 Devices

Figure 74. Each Device in Block Number 0 (Miss on Each Device) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 75. Each Device Above the Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 76. Globally Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 77. Devices Below the Winning Device in Block Number 1 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 78. Devices Above the Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 79. Globally Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 80. Devices Below the Winning Device in Block Number 2 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 81. Devices Above the Winning Device in Block Number 3 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 82. Globally Winning Device in Block Number 3 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 83. Devices Below the Winning Device in Block Number 3 (not Device 30 - Last Device) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 84. Last Device in Block Number 3 (Device 30 in the Table) Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0].

1. Each bit in LHO[1:0] is the same logical signal.
2. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0].
3. Each bit in BHO[2:0] is the same logical signal.

Figure 85. Timing Diagram for Mixed SEARCH for One Device

Figure 86. Multi-Width Configurations Example the device with the LDEV Bit set.

Bit [0] of each 68-bit data location specifies wheth- er an entry in the database is occupied. If all the entries in a device are occupied, the device as- serts FULO signal to inform the downstream de- vices that it is full. The result of this communication between depth- cascaded devices determines the global FULL signal for the entire table. The FULL signal in the last device determines the fullness of the depth- cascaded table. In a depth-cascaded table, only a single device will learn the entry through the application of a LEARN Instruction. The determination of which device is going to learn is based on the FULI and FULO sig- nalling between the devices. The first non-full de- vice learns the entry by storing the contents of the specified comparand registers to the location(s) pointed to by NFA. In a x68-configured table the LEARN command writes a single 68-bit location. In a x136-config- ured table the LEARN command writes the next even and odd 68-bit locations. In 136-bit mode, Bit[0] of the even and odd 68-bit locations is '0,' which indicates they are cascaded empty, or '1,' which indicates they are occupied. The global FULL signal indicates to the Table Con- troller (the host ASIC) that all entries within a block are occupied and that no more entries can be learned. The M7020R updates the signal after each WRITE or LEARN command to a data array. The LEARN command generates a WRITE cycle to the external SRAM, also using the NFA register as part of the SRAM address (see SRAM AD- DRESSING, page 126). The LEARN command is supported on a single block containing up to eight devices if the table is configured either as a x68 or a x136. The LEARN command is not supported for x272-configured ta- bles. LEARN is a pipelined operation and lasts for two CLK cycles, as shown in Figure 87, page 119 where TLSZ = 00, and Figure 88, page 120 and Figure 89, page 121 where TLSZ = 01 (which as- sume the device performing the LEARN operation is not the last device in the table and has its LRAM Bit set to '0.' Note: The OE_L for the device with the LRAM Bit set goes high for two cycles for each LEARN (one during the SRAM WRITE cycle, and one the cycle before). The latency of the SRAM WRITE cycle from the second cycle of the Instruction is shown in Table 49, page 121. The sequence of operation is as follows: – Cycle 1A: The host ASIC applies the LEARN In- struction on the CMD[1:0], using CMDV = 1. The CMD[5:2] field specifies the index of the comparand register pair that will be written in the data array in the 136-bit-configured table. For a LEARN in a 68-bit-configured table, the even-numbered comparands specified by this index will be written. CMD[8:7] carries the bits that will be driven on SADR[21:20] in the SRAM WRITE cycle. – Cycle 1B: The host ASIC continues to drive CMDV to '1,' CMD[1:0] to '11,' and CMD[5:2] with the comparand pair index. CMD[6] must be set to '0' if the LEARN is being performed on a 68-bit-configured table, and to '1' if the LEARN is being performed on a 136-bit-configured ta- ble. – Cycle 2: The host ASIC drives the CMDV to '0.' At the end of Cycle 2, a new instruction can be- gin. The latency of the SRAM WRITE is the same as the search to the SRAM READ Cycle. It is measured from the second cycle of the LEARN Instruction.

Figure 87. Timing Diagram of LEARN: TLSZ = 00

Figure 88. Timing Diagram of LEARN: TLSZ = 01 (Except on the Last Device)

Figure 89. Timing Diagram of LEARN on Device 7: TLSZ = 01 Table 49. Latency of SRAM WRITE Cycle from Second Cycle of LEARN Instruction

Figure 90. Depth-Cascading to Form a Single Block

Figure 91. Depth-Cascading Four Blocks

Figure 92. “FULL” Generation in a Cascaded Table

Table 50, page 127 describes the commands used to generate addresses on the SRAM Address Bus. The index [14:0] field contains the address of a 68- bit entry that results in a hit in 68-bit-configured quadrant. It is the address of the 68-bit entry that lies at the 136-bit page, and the 272-bit page boundaries in 136-bit- and 272-bit-configured quadrants, respectively. REGISTERS, page 21 of this specification, de- scribes the NFA and SSR Registers. ADR[14:0] contains the address supplied on the DQ Bus dur- ing PIO access to the M7020R. Command Bits 8 and 7 {CMD[8:7]} are passed from the command to the SRAM Address Bus (see COMMAND CODES AND PARAMETERS, page 29 for more information). ID[4:0] is the ID of the device driving the SRAM Bus (see Figure 3, page 10 and Table 2, page 9 for more information). SRAM PIO Access SRAM READ enables READ access to off-chip SRAM that contains associative data. The latency from the issuance of the READ Instruction to the address appearing on the SRAM Bus is the same as the latency of the SEARCH Instruction and will depend on the TLSZ value parameter pro- grammed in the device Configuration Register. The latency of the ACK from the READ Instruction is the same as the latency of the SEARCH Instruc- tion to the SRAM address plus the HLAT pro- grammed in the Configuration Register. Note: SRAM READ is a blocking operation – no new instruction can begin until the ACK is returned by the selected device performing the access. SRAM WRITE enables WRITE access to the off- chip SRAM containing associative data. The laten- cy from the second cycle of the WRITE Instruction to the address appearing on the SRAM Bus is the same as the latency of the SEARCH Instruction and will depend on the TLSZ value parameter pro- grammed in the device Configuration Register. Note: SRAM WRITE is a pipelined operation – new instruction can begin right after the previous command has ended. SRAM READ with a Table of One Device SRAM READ enables READ access to the off- chip SRAM containing associative data. The laten- cy from the issuance of the READ Instruction to the address appearing on the SRAM Bus is the same as the latency of the SEARCH Instruction and will depend on the TLSZ value parameter pro- grammed in the device configuration register. The latency of the ACK from the READ Instruction is the same as the latency of the SEARCH Instruc- tion to the SRAM address plus the HLAT pro- grammed in the configuration register. The following explains the SRAM READ operation in a table with only one device that has the follow- ing parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and LDEV = 1. Figure 93, page 127 shows the associated timing diagram. For the following description, the selected device refers to the only device in the table because it is the only device to be accessed. The sequence of the operation is as follows: – Cycle 1A: The host ASIC applies the READ In- struction on the CMD[1:0], using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM ad- dress. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. During this cycle, the host ASIC also supplies SADR[21:20] on CMD[8:7] in this cycle. – Cycle 1B: The host ASIC continues to apply the READ Instruction on the CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. – Cycle 2: The host ASIC floats DQ[67:0] to a 3- state condition. – Cycle 3: The host ASIC keeps DQ[67:0] in a 3- state condition. – Cycle 4: The selected device starts to drive DQ[67:0] and drives ACK from High-Z to low. – Cycle 5: The selected device drives the READ address on SADR[21:0]; it also drives ACK high, CE_L low, and ALE_L low. – Cycle 6: The selected device drives CE_L high, ALE_L high, the SADR Bus, and the DQ Bus in a 3-state condition; it drives ACK low. At the end of Cycle 6, the selected device floats ACK in a 3-state condition, and a new command can begin.

Table 50. Generating an SRAM Bus Address Figure 93. SRAM READ Access for One Device

SRAM READ with a Table of Up to Eight Devices The following explains the SRAM READ operation completed through a table of up to eight devices using the following parameters: TLSZ = 01. Figure 94, page 129 diagrams a block of eight devices. The following assumes that SRAM access is suc- cessfully achieved through M7020R Device 0. Fig- ure 95, page 130 and Figure 96, page 131 show timing diagrams for Device 0 and Device 7, re- spectively. – Cycle 1A: The host ASIC applies the READ In- struction on the CMD[1:0] using CMDV = 1. The DQ Bus supplies the address, with DQ[20:19] set to '10' to select the SRAM address. The host ASIC selects the device for which ID[4:0] match- es the DQ[25:21] lines. During this cycle the host ASIC also supplies SADR[21:20] on CMD[8:7]. – Cycle 1B: The host ASIC continues to apply the READ Instruction on the CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. – Cycle 2: The host ASIC floats DQ[67:0] to a 3- state condition. – Cycle 3: The host ASIC keeps DQ[67:0] in a 3- state condition. – Cycle 4: The selected device starts to drive DQ[67:0]. – Cycle 5: The selected device continues to drive DQ[67:0] and drives ACK from high-Z to low – Cycle 6: The selected device drives the READ address on SADR[21:0]. It also drives ACK high, CE_L low, WE_L high, and ALE_L low. – Cycle 7: The selected device drives CE_L, ALE_L, WE_L, and the DQ Bus in a 3-state con- dition. It continues to drive ACK low. At the end of Cycle 7, the selected device floats ACK in 3-state condition and a new command can begin.

Figure 94. Table with Eight Devices

Figure 95. SRAM READ Through Device 0 in a Block of Eight Devices

Figure 96. SRAM READ Timing for Device 7 in a Block of Eight Devices

SRAM READ with a Table of Up to 31 Devices The following explains the SRAM READ operation accomplished through a table of up to 31 devices, using the following parameters: TLSZ = 10. The di- agram of such a table is shown in Figure 97, page 133. The following assumes that SRAM access is being accomplished through M7020R Device 0 and that Device 0 is the selected device. Figure 98, page 134 and Figure 99, page 135 show the timing dia- grams for Device 0 and Device 30, respectively. – Cycle 1A: The host ASIC applies the READ In- struction to CMD[1:0] using CMDV = 1. The DQ Bus supplies the address, with DQ[20:19] set to '10,' to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. During this cycle, the host ASIC also supplies SADR[21:20] on CMD[8:7]. – Cycle 1B: The host ASIC continues to apply the READ Instruction to CMD[1:0] using CMDV = 1. The DQ Bus supplies the address, with DQ[20:19] set to '10,' to select the SRAM ad- dress. – Cycle 2: The host ASIC floats DQ[67:0] to a 3- state condition. – Cycle 3: The host ASIC keeps DQ[67:0] in a 3- state condition. – Cycle 4: The selected device starts to drive DQ[67:0]. – Cycles 5 to 6: The selected device continues to drive DQ[67:0]. – Cycle 7: The selected device continues to drive DQ[67:0] and drives an SRAM READ cycle. – Cycle 8: The selected device drives ACL from Z to low. – Cycle 9: The selected device drives ACK to high. – Cycle 10: The selected device drives ACK from high to low. At the end of Cycle 10, the selected device floats ACL in a 3-state condition.

Figure 97. Table of 31 Devices Made of Four Blocks

Figure 98. SRAM READ Through Device 0 in a Bank of 31 Devices (Device 0 Timing)

Figure 99. SRAM READ Through Device 0 in a Bank of 31 Devices (Device 30 Timing)

SRAM WRITE with a Table of One Device SRAM WRITE enables WRITE access to the off- chip SRAM that contains associative data. The la- tency from the second cycle of the WRITE Instruc- tion to the address appearing on the SRAM Bus is the same as the latency of the SEARCH Instruc- tion, and will depend on the TLSZ value parameter programmed in the device configuration register. The following explains the SRAM WRITE opera- tion accomplished with a table of only one device of the following parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and LDEV = 1. Figure 100, page 137 shows the timing diagram. For the following description the selected device refers to the only device in the table as it is the only device that will be accessed. – Cycle 1A: The host ASIC applies the WRITE In- struction on CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also sup- plies SADR[21:20] on CMD[8:7] in this cycle. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. – Cycle 1B: The host ASIC continues to apply the WRITE Instruction on CMD[1:0], using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. – Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the M7020R device. – Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the M7020R device. At the end of Cycle 3, a new command can begin. The WRITE is a pipelined operation. The WRITE Cycle appears at the SRAM Bus, however, with the same latency as that of a SEARCH Instruction, as measured from the second cycle of the WRITE command.

Figure 100. SRAM WRITE Access for One Device

SRAM WRITE with a Table of Up to Eight Devices The following explains the SRAM WRITE opera- tion done through a table(s) of up to eight devices with the following parameters (TLSZ = 01). The di- agram of such a table is shown in Figure 101, page 139. The following assumes that SRAM access is done through M7020R Device 0. Figure 102, page 140 and Figure 103, page 141 show the timing dia- gram for Device 0 and Device 7, respectively. – Cycle 1A: The host ASIC applies the WRITE In- struction on CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also sup- plies SADR[23:21] on CMD[8:6] in this cycle. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. – Cycle 1B: The host ASIC continues to apply the WRITE Instruction on CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM ad- dress. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. – Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the M7020R device. – Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the M7020R device. At the end of cycle 3, a new command can begin. The WRITE is a pipelined operation. The WRITE Cycle appears at the SRAM Bus, however, with the same latency as that of a SEARCH Instruction, as measured from the second cycle of the WRITE command.

Figure 101. Table with Eight Devices

Figure 102. SRAM WRITE Through Device 0 in a Block of Eight Devices

Figure 103. SRAM WRITE Timing for Device 7 in a Block of Eight Devices

SRAM WRITE with Table(s) of Up to 31 Devices The following explains the SRAM WRITE opera- tion done through a table(s) of up to 31 devices with the following parameters (TLSZ = 10). The di- agram of such table(s) is shown in Figure 104, page 143. The following assumes that SRAM ac- cess is done through M7020R Device 0 – Device 0 is the selected device. Figure 105, page 144 and Figure 106, page 145 show the timing diagram for Device 0 and Device 30, respectively. – Cycle 1A: The host ASIC applies the WRITE In- struction on CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also sup- plies SADR[21:20] on CMD[8:7] in this cycle. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. – Cycle 1B: The host ASIC continues to apply the WRITE Instruction on CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM ad- dress. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. – Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the M7020R device. – Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the M7020R device. At the end of Cycle 3, a new command can begin. The WRITE is a pipelined operation. The WRITE Cycle appears at the SRAM Bus, however, with the same latency as that of a SEARCH Instruction, as measured from the second cycle of the WRITE command

Figure 104. Table of 31 Devices (Four Blocks)

Figure 105. SRAM WRITE Through Device 0 in a Bank of 31 Devices (Device 0 Timing)

Figure 106. SRAM WRITE Through Device 0 in a Bank of 31 Devices (Device 30 Timing)

definitions: TCK, TMS, TDI, TDO, and TRST_L. scribes the TAP Device ID Register. Table 51. Supported Operations Table 52. TAP Device ID Register the normal functional operation. test connectivity external to the device. using the boundary scan register to provide the I/O values. Revision Number. This is the current device revision number. Part # [27:12] 0000 0000 0000 0001 This is the part number for this device.

Table 53. Ordering Information Scheme please contact the ST Sales Office nearest to you.

Figure 107. PBGA-Z00 – 272-ball Plastic Ball Grid Array Package Outline Note: Drawing is not to scale. Table 54. PBGA-Z00 – 272-ball Plastic Ball Grid Array Package Mechanical Data

1. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink, or metallized markings, or other feature

of package body or integral heatslug.

1. A distinguished feature is allowable on the bottom surface of the package to identify the terminal A1 corner.
2. Exact shape of each corner is optional.

REVISION HISTORY

Table 55. Document Revision History

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