M7010R STMICROELECTRONICS | Alldatasheet

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Figure 1. 272-ball PBGA Package

272 PBGA

Mixed-sized Searches on Tables Configured with Different Width Using an M7010R Device46

Four Blocks (31 Devices Cascaded) SEARCH, 68-bit Configured with LDEV = 1 (Figure 39.)...5 4

Table 2. Signal Names

  1. ACK and EOT Signals require a pull-down resistor of 47 ohms.

Figure 3. Connections Note: This diagram is TOP VIEW perspective (view through package).

Figure 4. M7010R Block Diagram

Table 3. Absolute Maximum Ratings Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

tions when using the quoted parameters. Table 4. DC and AC Measurement Conditions Note: 1. Maximum allowable applies to overshoot only (VDDQ is 3.3V supply).

  1. Minimum allowable applies to undershoot only.

Table 5. Capacitance Note: Effective capacitance measured with power supply. Sampled only, not 100% tested. Table 6. DC Characteristics Note: 1. Valid for Ambient Operating Temperature: TA =0t o7 0°C; VDD =1 . 8 V .

Figure 11. AC Timing Waveforms with CLK2X

Table 7. AC Timing Parameters with CLK2X Note: 1. Valid for Ambient Operating Temperature: TA =0t o7 0°C; VDD =1 . 8 V .

  1. Values are based on 50% signal levels.
  2. Unless otherwise noted, all values are based on AC load of CL = 50pF (see Figure 5, page 12 and Figure 8, page 12).
  3. These parameters are sampled and not 100% tested.

CMD[8:0] carries the command and its associated parameter. DQ[67:0] is used for data transfer to, and from the data base entries. The database en- tries are comprised of a data field and a mask field which are organized as a data array and a mask array. The DQ Bus carries the SEARCH data dur- ing the SEARCH command as well as the address and data during Pipelined I/O (PIO) READ/WRITE operations, of the data array, mask array, and in- ternal registers. The DQ Bus also can carry the ad- dress information for the PIO accesses to the SRAM. Database Entry (Data Array and Mask Array) Each database entry comprises a data field and a mask field. The resultant value of the entry is a log- ical AND of the corresponding data and mask bits and can take logical values of '1,' '0' and 'X' (don’t care), depending on the value in the mask bit. The on-chip priority encoder selects the first matching entry in the database which is nearest to location Arbitration Logic When multiple (Silicon) Search Engines are cas- caded to create large databases, the data being searched is presented to all Search processors si- multaneously in the cascaded system. When more than one device has duplicate entries, the arbitra- tion logic on the Search Engine with the matching entry which is closest to address 0 of the cascaded database, will be selected to drive the SRAM Bus. Pipeline and SRAM Control Pipeline latency is added to give enough time to the arbitration logic in a cascaded system to deter- mine the index with the highest priority. The pipe- line logic adds latency to the SRAM access cycles and the SSF and SSV signals to align them to the host ASIC receiving the associated data. Refer to Table 27, page 36 for details. Full Logic Bit[0] in each of the 68-bit entries has a special purpose for the LEARN command (0 = empty, 1 = full). When all the data entries have Bit[0] set to '1,' the database asserts the FULL flag, indicating that all the Search Engines in the depth-cascaded ar- ray are full. Connections Descriptions Master Clock (CLK2X).The M7010R samples all of the control and data signals on the positive edge of CLK2X when PHS_L is low. Phase (PHS_L). This signal runs at half the fre- quency of CLK2X and generates an internal clock from CLK2X (see Figure 12, page 18). Reset (RST_L).Driving RST low initializes the device to a known state. Command Bus (CMD[8:0]. [1:0] specifies the command; [8:2] contains the command parame- ters. The descriptions of individual commands ex- plains the details of the parameters. The encoding of commands based on the [1:0] field are: – 00: PIO READ – 01: PIO WRITE – 10: SEARCH – 11: LEARN Command Valid ( CMDV) . Qualifies the CMD bus as follows: – 0: No Command – 1: Command Address/Data Bus (DQ[67:0]). Carries the READ and WRITE address as well as the data during register, data, and mask array operations. It car- ries the compare data during SEARCH opera- tions. It also carries the SRAM address during SRAM PIO accesses. READ Acknowledge (ACK). Indicates that valid data is available on the DQ Bus during register, data, and mask array READ operations, or the data is available on the SRAM data bus during SRAM READ operations. Note:ACK Signals require a pull-down resistor of 47Ω . End of Transfer (EOT).Indicates the end of burst transfer during READ or WRITE burst oper- ations. Note:EOT Signals require a pull-down resistor of 47 ohms. SEARCH Successful Flag (SSF).When assert- ed, this signal indicates that the device is the glo- bal winner in a SEARCH operation. SEARCH Successful Flag Valid (SSV).When asserted, this signal qualifies the SSF signal. SRAM Address (SADR[21:0]). This bus con- tains address lines to access off-chip SRAMs that contain associative data. See Table 35, page 61 for the details of the generated SRAM address. SRAM Chip Enable (CE_L). This is Chip Enable control for external SRAMs. When more than one device is cascaded, CE_L of all devices must be connected. SRAM WRITE Enable (WE_L). This is WRITE Enable control for external SRAMs. When more than one device is cascaded, WE_L of all devices must be connected. SRAM Output Enable (OE_L). This is Output Enable control for external SRAMs. Only the last device drives this signal (with the LRAM Bit set).

Address Latch Enable (ALE_L).When this sig- nal is low, the addresses on the SRAM address bus have been validated. When more than one de- vice is cascaded, the ALE_L of all devices must be connected. Local Hit In (LHI[6:0]).These pins depth-cas- cade the device to form a larger table size. One signal of this bus is connected to the LHO[1] or LHO[0] of each of the upstream devices in a block. Connect all unused LHI pins to a logic '0.' (For more information, see DEPTH-CASCADING, page 52.) Local Hit Out (LHO[1:0]).LHO[1] and LHO[0] are the same logical signal. LHO[1] or LHO[0] is connected to one input of the LHI bus of up to four downstream devices (in a block that contains up to eight devices; for more information, see DEPTH- CASCADING, page 52.) Block Hit In (BHI[2:0]).Inputs from the previous BHO[2:0] are tied to the BHI[2:0] of the current de- vice (see DEPTH-CASCADING, page 52). In a four-block system, the last block can contain only seven devices because the ID code 11111 is used for broadcast access. Block Hit Out (BHO[2:0]).Outputs from the cur- rent device are connected to the BHI[2:0] of the next device (see DEPTH-CASCADING, page 52). Full In (FULI[6:0]).Each signal in this bus is con- nected to FULO[0] or FULO[1] of an upstream de- vice to generate the FULL flag for the depth- cascaded block. For more information, see DEPTH-CASCADING, page 52 to Generate Full for a Block Section. Full Out (FULO[1:0]).FULO[1] and FULO[0] are the same logical signal. One of these two signals must be connected to the FULI of up to four down- stream devices in a depth-cascaded table. Bit [0] in the data array indicates if the entry is full (1) or empty (0).This signal is asserted if all of the bits in the data array are '1s.' Refer to Depth-Cascading to Generate a“FULL ”State for a Block, page 52. Full Flag (FULL).When asserted, this signal in- dicates that the table consisting of many depth- cascaded devices is full. Device Identification (ID[4:0]).The binary-en- coded device ID for a depth-cascaded system starts at 00000 and goes up to 11110. 11111 is re- served for a special broadcast address that se- lects all cascaded (silicon) Search Engines in the system. On a broadcast read-only, the device with the LDEV Bit set to '1' responds. Test Data In (TDI).This is the Test Access Port’s Test Data In. Test Clock (TCK).This is the Test Access Port’s Test Clock. Test Data Out (TDO).This is the Test Access Port’s Test Data Out. Test Mode Select (TMS).This is the Test Ac- cess Port’s Test Mode Select. Test Reset (TRST_L).This is the Test Access

and CLK signals are used for internal operations. shown in Figure 13, page 19. operations, also shown in Figure 14. Figure 12. Clocks

  1. “CLK ”is an internal signal. The period for this clock is specified in Table 7, page 15.

Table 8. Register Overview 32–47 MASKS RW 16 Global Mask Registers Array. 48–55 SSR0 –7 R 8 SEARCH Successful Index Registers. 56 COMMAND RW Command Register. 57 INFO R Information Register. 58 RBURREG RW Burst READ Register. 59 WBURREG RW Burst WRITE Register. 60 NFA R Next Free Address Register.

Table 10. Command Register Field Descriptions cycles. This bit automatically resets to a '0' during the reset cycle. is no bus contention when the devices power-up in the system. SRAM (SADR[21:0], CE_L, OE_L, WE_L, ALE_L, SSV, SSF, and ACK). Once programmed, the SEARCH latency stays constant. depth-cascaded table and is the default driver for the SSF and SSV signals. OE_L is always driven by the device for which this bit is set.

CFG [16:9] 0000 0000 Database Configuration.The device is internally divided into four quadrants of 8K x 68, each of which can be configured as 4K x 68, 2K x 136, or 1K x 272 as follows: 00: 4K x 68 01: 2K x 136 10: 1K x 272 11: Reserved Bits [10:9] apply to configuring the 1st quadrant in the address space. Bits [12:11] apply to configuring the 2nd quadrant in the address space. Bits [14:13] apply to configuring the 3rd quadrant in the address space. Bits [16:15] apply to configuring the 4th quadrant in the address space. [67:17] 0 Reserved. Field Range Initial Value Description

Table 11. Information Register Field Descriptions programmed before burst READ (see Table 12). Table 12. READ Burst Register Description Table 13. WRITE Burst Register Description from one and increment by one for each revision of the device. tation [6:4] 000 This is the M7010R implementation number. Device ID [15:8] 00000001 This is the Device Identification Number. up to 511 locations in a single burst. The BLEN decrements automatically. up to 511 locations in a single burst. The BLEN decrements automatically.

dicate full/empty status for a 136-bit entry. '1' (e.g., '10' or '01' settings are invalid). Table 14. NFA Register ue of CFG bits in the COMMAND register. 68-bit entries in quadrants configured as 272 bits. drive the SRAM bus, SSF, and SSV signals. a sample configuration of different widths.

60 Reserved Index

Figure 17. M7010R Database Configuration Table 15. Bit Position Match Figure 18. Multi-width Configuration Example

8 K 4 K

Figure 19. M7010R Data and Mask Array Addressing

tions describe the functions of the commands. instructions with the CLK2X signal. Table 16. Command Codes Table 17. Command Parameters Note: The SRAM Address Bit SADR [19] in the command bit C6 will not be passed to the SRAM (see Table 28).

  1. The 272-bit configuration does not support the LEARN Instruction.

00 READ Reads one of the following: data array, mask array, device registers, or external

01 WRITE Writes one of the following: data array, mask array, device registers, or external

10 SEARCH Searches the data array for a desired pattern using the specified register from the

global mask register array and local mask associated with each data cell.

11 LEARN

the NFA register) using the LEARN Instruction.

T h eR E A Dc a nb eas i n g l er e a do fad a t aa r r a y ,a mask array, an SRAM, or a register location (CMD[2] = 0). It can be a burst READ (CMD[2] = 1) using an internal auto-incrementing address regis- ter (RBURADR) of the data or mask array loca- tions (see Table 18, page 30 and Table 19, page 30 for formats). A single-location READ operation takes six cycles, as shown in Figure 20, page 29. The burst READ adds two cycles for each successive read. The SADR[21:19] bits supplied in the READ Instruction Cycle A drives SADR[21:19] signals during the PIO READ of an SRAM location. The single READ operation takes six CLK cycles, in the following sequence: – Cycle 1:The host ASIC applies the READ In- struction on the CMD[1:0] (CMD[2] = 0), using CMDV = 1, and the DQ Bus supplies the ad- dress, as shown in Table 19, page 30 and Table 20, page 30. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21] lines. If DQ[25:21] = 11111, the host ASIC selects the M7010R with the LDEV Bit set. The host ASIC also supplies SADR[21:19] on CMD[8:6] in Cy- cle A of the READ Instruction if the READ is di- rected to the external SRAM. – Cycle 2:The host ASIC releases the DQ[67:0] bus to a tri-state condition. – Cycle 3:The host ASIC keeps DQ[67:0] bus in a tri-state condition. – Cycle 4:The selected device starts to drive the DQ[67:0] bus and drives the ACK signal from Z to low. – Cycle 5:The selected device drives the READ data from the addressed location on the DQ[67:0] bus and drives the ACK signal high. – Cycle 6: The selected device floats the DQ[67:0] bus and drives the ACK signal low. At the termination of Cycle 6, the selected device releases the ACK line to a tri-state condition. The READ Instruction is complete, and a new opera- tion can begin. The burst READ operation lasts 4 + 2n CLK-cycles (where “n” stands for the number of accesses in the burst specified by the BLEN field of the RBUR- REG) in the sequence shown in Figure 21, page 29. This operation assumes that the host ASIC has programmed the RBURREG with the starting address (ADDR) and the length of transfer (BLEN) before initiating the burst READ command. – Cycle 1:The host ASIC applies the READ In- struction on the CMD[1:0] (CMD[2] = 1), using CMDV=1 and the address supplied on the DQ Bus, as shown in Table 21, page 31. The host ASIC selects the device for which ID[4:0] match- es the DQ[25:21] lines. If DQ[25:21] = 11111, the host ASIC selects the M7010R with the LDEV Bit set. – Cycle 2:The host ASIC floats DQ[67:0] to a tri- state condition. – Cycle 3:The host ASIC keeps DQ[67:0] bus in a tri-state condition. – Cycle 4:The selected device starts to drive the DQ[67:0] bus and drives ACK, and EOT from Z to low. – Cycle 5:The selected device drives the READ data from the addressed location on the DQ[67:0] bus and drives the ACK signal high. Note:Cycles four and five repeat for each addi- tional access until all the accesses specified in the burst length (BLEN) field of RBURREG are complete. On the last transfer, the M7010R drives the EOT signal high. – Cycle (4 + 2n):The selected device drives the DQ[67:0] to 3-state condition and drives the ACK and the EOT signals low. At the termination of Cycle 4 + 2n, the selected de- vice floats the ACK line to 3-state condition. The burst READ Instruction is complete, and a new op- eration can begin (see Table 21, page 31 for burst READ address formats).

Figure 20. Single Location READ Cycle Timing Figure 21. Burst READ of the Data and Mask Arrays (BLEN = 4)

1 Cycle

3 Cycle

11 Cycle

Table 18. READ Command Parameters Table 19. Data and Mask Array, SRAM READ Address Format Note: 1.“|”stands for logical OR operation, and“{}”stands for concatenation operator. Table 20. READ Address Format for Internal Registers

0 Single Read Reads a single location of the data array, mask array, external SRAM,

or device registers. All access information is applied on the DQ Bus.

1 Burst Read

auto-increments the address for each access. All other access information is applied on the DQ Bus. address of data array location. address of mask array location.

Table 21. READ Address Format for Data and Mask Arrays cle, another operation can begin. WBURREG register (see Figure 23, page 32). array locations in CMD[5:3]. REG register) of the selected device. the BLEN field of the WBURREG). a new instruction can begin.

Table 22. (Single) WRITE Address Format for Data and Mask Arrays or SRAM Note: 1.“|”stands for logical OR operation, and“{}”stands for concatenation operator. Table 23. WRITE Address Format for Internal Registers Table 24. WRITE Address Format for Data and Mask Array (Burst WRITE) address of the data array location. address of the mask array location. address of the data SRAM location. increments with each access. increments with each access.

Figure 25. 68-Bit Configuration SEARCH Timing Diagram (One Device)

2 Cycle

4 Cycle

Table 25. Right-Shift of 68-bit Signals for TLSZ Table 26. Shift of SSF and SSV from SADR (for Table 27. Latency of SEARCH from Instruction to SRAM Access Cycle (68-bit Mode)

Figure 28. 136-Bit Configuration SEARCH Timing Diagram (One Device)

Table 28. Right-Shift of 136-bit Signals for Table 29. Shift of SSF and SSV from SADR (for Table 30. Latency of SEARCH from Instruction to SRAM Access Cycle (136-bit Mode)

parand Register Index in the command’s Cycle B. Figure 29. x136 Table with One Device

Figure 31. 272-Bit Configuration SEARCH Timing Diagram (One Device)

Table 31. Right-Shift of 272-bit Signals for Table 32. Shift of SSF and SSV from SADR (for Table 33. Latency of SEARCH from Instruction to SRAM Access Cycle (272-bit Mode)

Figure 34. Timing Diagram for Mixed SEARCH (One Device)

When search engines are cascaded using multiple M7010R devices, the SADR, CE_L, and WE_L (tri-state signals) are all tied together. To eliminate external pull-up and pull-downs, one device in a bank is designated as the default driver. For non- SEARCH or non-LEARN cycles (see LEARN COMMAND, page 48) or SEARCH cycles with a global miss, the SADR, CE_L, and WE_L signals are driven by the device with the LRAM Bit set. It is important that only one device in a bank of cas- caded search engines have this bit set. Failure to do so will cause contention on SADR, CE_L, and WE_L, and can potentially cause damage to the device(s). Similarly, when search engines using multiple M7010R devices are cascaded, SSF and SSV (al- so tri-state signals) are tied together. To eliminate external pull-up and pull-downs, one device in a bank is designated as the default driver. For non- SEARCH or SEARCH cycles with a global miss, the SSF and SSV signals are driven by the device with the LRAM Bit set. It is important that only one device in a bank of cascaded search engines have this bit set. Failure to do so will cause contention on SSF and SSV, and can potentially cause dam- age to the device(s). LEARN COMMAND Bit [0] of each 68-bit data location specifies wheth- er an entry in the database is occupied. If all the entries in a device are occupied, the device as- serts FULO signal to inform the downstream de- vices that it is full. The result of this communication between depth- cascaded devices determines the global FULL signal for the entire table. On a miss by the SEARCH (signalled to the ASIC through the SSV and SSF signals [SSV = 1, SSF = 0]), the host ASIC can apply the LEARN command to learn the entry from a comparand register to the next-free location (see The NFA Register, page 24). The NFA updates to the next-free location following each WRITE or LEARN command. In a depth-cascaded table, only a single device will learn the entry through the application of a LEARN Instruction. The determination of the LEARN de- vice is based on the FULI and FULO signalling be- tween the devices. The first non-full device learns the entry by storing the contents of the specified comparand registers to the location(s) pointed to by the NFA. In a x68-configured table, the LEARN command writes a single 68-bit location. In a 136-bit-config- ured table, the LEARN command writes the next even and odd 68-bit locations. In 136-bit mode, Bit[0] of the even and odd 68-bit locations is '0,' in- dicating that they are cascaded empty, or '1,' which indicates that they are occupied. The global FULL signal indicates to the table con- troller (the host ASIC) that all entries within a block are occupied and that no more entries can be learned. The M7010R device updates the signal to a data array after each WRITE or LEARN com- mand. Also using the NFA Register as part of the SRAM address, the LEARN command generates a WRITE cycle to the external SRAM. The LEARN command is supported on a single block containing up to eight devices if the table is configured as either a x68 or a x136. The LEARN command is not supported for x272-configured ta- bles. The LEARN operation lasts two CLK cycles. The sequence of this operation is as follows: – Cycle 1A: The host ASIC applies the LEARN I n s t r u c t i o no nC M D [ 1 : 0 ]u s i n gC M D V=1 .T h e CMD[5:2] field specifies the index of the com- parand register pair that will be written to the data array in the 136-bit-configured table. For a LEARN in a 68-bit-configured table, the even- numbered comparand specified by this index will be written. CMD[8:6] carries the bits that will be driven on SADR[21:19] in the SRAM WRITE cycle. – Cycle 1B: The host ASIC continues to drive CMDV to '1,' CMD[1:0] to '11,' and CMD[5:2] with the comparand pair index. CMD[6] must be set to '0' if the LEARN is being performed on a 68-bit-configured table, and to '1' if the LEARN is being performed on a 136-bit-configured ta- ble. – Cycle 2:The host ASIC drives CMDV to '0.' At the end of Cycle 2, a new instruction can begin. SRAM WRITE latency is the same as the SEARCH to the SRAM READ cycle measured from the second cycle of the LEARN Instruction.

tion is shown in Table 34, page 51. Figure 35. LEARN Command Timing Diagram (TLSZ = 00)

Figure 36. LEARN Timing Diagram (TLSZ = 1, except on Last Device)

Figure 37. LEARN Timing Diagram on Device Number 7 (TLSZ = 01) Table 34. SRAM WRITE Cycle Latency from Second Cycle of LEARN Instruction

Figure 38. Depth-Cascading to Form a Single Block (8 Devices)

Figure 39. Four Blocks (31 Devices Cascaded) SEARCH, 68-bit Configured with LDEV = 1

Figure 40. “FULL” State Generation in a Cascaded Table

Figure 42. Timing for Arbitration for Two or More Blocks for the Last Device

Table 35, page 61 lists and describes the com- mands used to generate addresses on the SRAM address bus. The Index[13:0] field contains the ad- dress of a 68-bit entry that results in a hit in 68-bit configured quadrant. It is the address of the 68-bit entry that lies at the 136-bit page and 272-bit page boundaries in 136-bit and 272-bit configured quadrants, respectively. The register section of this specification describes the NFA and SSR registers. Adr[13:0] contains the address supplied on the DQ Bus during PIO ac- cess to the M7010R. Command Bits 8 and 7, CMD[8:6] are passed from the command to the SRAM address bus. See COMMAND CODES AND PARAMETERS, page 27 for more informa- tion. SRAM PIO Access SRAM READ. Enables READ access to the off- chip SRAM that contains associative data. The la- tency from the issuance of the READ Instruction to the address appearing on the SRAM bus is the same as the latency of the SEARCH Instruction, and will depend on the value programmed for the TLSZ parameter in the device configuration regis- ter. The latency of the ACK from the READ In- struction is the same as the latency of the SEARCH Instruction to the SRAM address plus the HLAT programmed into the configuration reg- ister. Note: SRAM READ is a blocking operation - no new instruction can begin until the ACK is returned by the selected device performing the access. The following explains the SRAM READ operation in a table with only one device and having the fol- lowing parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and LDEV = 1. Figure 43, page 59 shows the associated timing diagram. For the fol- lowing description, the selected device refers only to the device in the table because it is the only de- vice to be accessed. – Cycle 1A:The host ASIC applies the READ In- struction on CMD[1:0] using CMDV = 1. The DQ Bus supplies the address, with DQ[20:19] set to “10,” to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. During this cycle, the host ASIC also supplies SADR[21:19] on CMD[8:6]. – Cycle 1B:The host ASIC continues to apply the READ Instruction on CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to“10” to select the SRAM ad- dress. – Cycle 2:The host ASIC floats DQ[67:0] to a tri- state condition. – Cycle 3:The host ASIC keeps DQ[67:0] in a tri- state condition. – Cycle 4: T h es e l e c t e dd e v i c es t a r t st od r i v e DQ[67:0] and drives ACK from High-Z to LOW. – Cycle 5:The selected device drives the READ address on SADR[21:0]; it also drives ACK HIGH, CE_L LOW, and ALE_L LOW. – Cycle 6: The selected device drives CE_L HIGH, ALE_L HIGH, the SADR Bus and DQ Bus in a tri-state condition, and ACK LOW. At the end of Cycle 6, the selected device floats ACK in a tri-state condition, and a new command can begin. Table 36, page 62 shows by how many cycles SRAM signals shift to the right for various TLSZ values. Table 37, page 62 shows by how many cycles SRAM signals shift to the right for various HLAT values.

Figure 43. SRAM READ Access for One M7010R Device

SRAM WRITE. Enables WRITE access to the off- chip SRAM containing associative data. The laten- cy from the second cycle of the WRITE Instruction to the address appearing on the SRAM bus is the same as the latency of the SEARCH Instruction, and will depend on the TLSZ value parameter pro- grammed into the device configuration register. Note: SRAM WRITE is a pipelined operation - new instruction can begin right after the previous com- mand has ended. The following explains the SRAM WRITE operation accomplished through a table of only one device with the following param- eters: TLSZ = 00, HLAT = 000, LRAM = 1, and LDEV = 1. Figure 44, page 61 shows the timing di- agram. For the following description, the selected device refers to the only device in the table as this is the only device that will be accessed. – Cycle 1A:The host ASIC applies the WRITE In- struction on CMD[1:0] using CMDV = 1. The DQ Bus supplies the address, with DQ[20:19] set to “10,” to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also supplies SADR[21:19] on CMD[8:6] in this cycle. Note: CMD[2] must be set to '0' for SRAM WRITE, because burst WRITES into the SRAM are not supported. – Cycle 1B:The host ASIC continues to apply the W R I T EI n s t r u c t i o no nC M D [ 1 : 0 ]u s i n gC M D V= 1. The DQ Bus supplies the address with DQ[20:19] set to“10” to select the SRAM ad- dress. Note: CMD[2] must be set to '0' for SRAM WRITE, because burst WRITES into the SRAM are not supported. – Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the M7010R. – Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the M7010R. At the end of Cycle 3, a new command can begin. The WRITE is a pipelined operation; however, the WRITE cycle appears at the SRAM bus with the same latency as the SEARCH Instruction (as mea- sured from the second cycle of the WRITE com- mand).

Figure 44. SRAM WRITE Access for One M7010R Device Table 35. SRAM Bus Address Generation

Table 36. Right-Shift of SRAM Signals for TLSZ Table 37. Right-Shift of SRAM Signals for tions that the test access port controller supports. Table 39 shows the TAP Device ID Register. Table 38. Test Access Port Controller Instructions Table 39. TAP Device ID Register normal functional operation. connectivity external to the device. using the boundary scan register to provide the I/O values. Revision Number.This is the current device revision number. Part # [27:12] 0000 0000 0000 0001 This is the part number for this device.

used having values of 0.01uF and 0.1uF. the 3.3V VDDQ source supply. specified with the bypass capacitors. pentiumiii/xeon/applnots/245095.htm). Figure 45. Network Search Engine Power Distribution

Table 40. Ordering Information Scheme please contact the ST Sales Office nearest to you.

Figure 46. PBGA-Z00 – 272-ball Plastic Ball Grid Array Package Outline Note: Drawing is not to scale. Table 41. PBGA-Z00 – 272-ball Plastic Ball Grid Array Package Mechanical Data

  1. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink, or metallized markings, or other feature

of package body or integral heatslug.

  1. A distinguished feature is allowable on the bottom surface of the package to identify the terminal A1 corner.
  2. Exact shape of each corner is optional.

REVISION HISTORY

Table 42. Document Revision History

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