M69AW048B STMICROELECTRONICS | Alldatasheet
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32 Mbit (2M x16) 3V Asynchronous PSRAM
Figure 1. Package
standard Asynchronous SRAM Interface. Figure 2. Logic Diagram Table 1. Signal Names
Figure 3. TFBGA Connections (Top view through package)
See Figure 2., Logic Diagram, and Table 1., Signal Names, for a brief overview of the sig- nals connected to this device. Address Inputs (A0-A20).The Address Inputs select the cells in the memory array to access dur- ing Read and Write operations. Data Inputs/Outputs (DQ8-DQ15).The Upper Byte Data Inputs/Outputs carry the data to or from the upper part of the selected address during a Write or Read operation, when Upper Byte Enable (UB) is driven Low. Data Inputs/Outputs (DQ0-DQ7).The Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the selected address during a Write or Read operation, when Lower Byte Enable (LB) is driven Low. Chip Enable (E1).When asserted (Low), the Chip Enable, E1, activates the memory state ma- chine, address buffers and decoders, allowing Read and Write operations to be performed. When de-asserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode. Chip Enable (E2).The Chip Enable, E2, puts the device in Power-down mode (Deep Power-Down, PAR and Standby) when it is driven Low. One of these, Deep Power-Down mode, is the lowest power mode. Output Enable (G ).The Output Enable, G, pro- vides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. Write Enable (W ).The Write Enable, W, controls the Bus Write operation of the memory’s Com- mand Interface. Upper Byte Enable (UB).The Upper Byte En- able, UB, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-DQ15) to or from the upper part of the selected address during a Write or Read operation. Lower Byte Enable (LB).The Lower Byte En- able, LB, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7) to or from the lower part of the selected address during a Write or Read operation. VCC Supply Voltage.The V CC Supply Voltage supplies the power for all operations (Read, Write, etc.) and for driving the refresh logic, even when the device is not being accessed. VSS Ground. The VSS Ground is the reference for all voltage measurements.
Figure 4. Block Diagram
(E1 is Low, and E2 is High). was the last to reach the appropriate level. details of when the outputs become valid. and Lower Byte Enable (LB) is Low. to become true (tAVWL or tAVEL or tAVBL ). high impedance within tWHDZ of its rising edge. when the outputs become valid. when the outputs become valid. Refresh (see Table 4. and Figure 22.). be lost once E2 is brought Low for Power-down. Power-Down mode after Power-up. rent consumption is of major importance. eration the device must be in Standby mode. Table 4. shows the sequence. In the first cycle, the Byte at the highest memory address (MSB) is read.
Table 2. Operating Modes
- Should not be kept in this logic condition for a period longer than 1µs.
- Power-Down mode can be entered from Standby state and all DQ pins are in High-Z state. The Power-Down current and data re-
tention depend on the selection of Power-Down programming.
- G can be VIL during the Write operation if the following conditions are satisfied:
b. G stays VIL during the entire Write cycle. Table 3. Power-Down Modes
Table 4. Power-Down Program Sequence Note: 1. PDC Power-Down Configuration. Table 5. Power-Down Configuration Data Table 6. Power-Down Configuration Addresses
Table 7. Absolute Maximum Ratings
Table 8. Operating and AC Measurement Conditions Note: 1. All voltages are referenced to VSS .
- The Input Transition Time used in AC measurements is 5ns. For other input transition times, see Table 8.
Figure 5. AC Measurement I/O Waveform Figure 6. AC Measurement Load Circuit
Table 9. Capacitance Table 10. DC Characteristics Note: 1. Maximum DC voltage on input and I/O pins is VCC +0 . 2 V . During voltage transitions, input may positive overshoot to VCC + 1.0V for a period of up to 5ns.
- Minimum DC voltage on input or I/O pins is –0.3V.
During voltage transitions, input may positive overshoot to VSS + 1.0V for a period of up to 5ns.
Table 11. Read Mode AC Characteristics contact your local ST representative for relaxation of the 1000ns limitation.
- Address should not be changed within minimum Read Cycle Time.
- The output load 50pF with 50Ω termination to V
- The output load 5pF without any other load.
- Applicable to A3 to A20 when E1
- Applicable only to A0, A1 and A2 when E1 is kept Low for the page address access.
- In case Page Read Cycle is continued with keeping E1 stays Low, E1 must be brought to High within 4µs. In other words, Page
Read Cycle must be closed within 4µs.
- Applicable when at least two of address inputs among applicable are switched from previous state.
- Minimum Read Cycle TIme and minimum Page Read Cycle Time must be satisfied.
Figure 11. Random and Page Address Controlled, Read Mode AC Waveforms
Table 12. Write Mode AC Characteristics local ST representative for relaxation of the 1000ns limitation.
- Minimum value must be equal to or greater than the sum of write pulse (tELEH , tWLBH or tBLBH ) and write recovery time (tEHAX ,
- Write pulse is defined from the falling edge of E1, W, or LB/UB, whichever occurs last.
- Write recovery is defined from Write pulse is defined from the rising edge of E1, W, or LB/UB, whichever occurs first.
- Applicable to any address change when E1 stays Low.
- If G is Low after minimum tGHEL , the read cycle is initiated. In other words, G must be brought High within 5ns after E1 is brought
Low. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time is met.
- If G is Low after new address input, the read cycle is initiated. In other words, G must be brought High at the same time or before
new address valid. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time is met.
Table 13. Standby/Power-Down Mode AC Characteristics Note: 1. Applicable also to Power-up.
- Applicable when 4Mb, 8Mb and 16Mb PAR mode is programmed
- Some data might be written into any address location if t
EHWL (min) is not satisfied.
- The Input Transition Time (tτ) at AC testing is 5ns as shown below. If actual tτ is longer than 5ns, it may violate AC specification of
Figure 22. Power Down Program AC Waveforms
- All address inputs must be High from Cycle 1 to Cycle 5.
- PDCADD stands for Power-Down Configuration Address. It must be compliant with the format specified in Table 6 otherwise the
data programmed during the Power-Down Program sequence may be incorrect.
- PDCDAT stands for Power-Down Configuration Data. It must be compliant with the format specified in Table 5 otherwise the data
programmed during the Power-Down Program sequence may be incorrect. EHEL after the end of Cycle 6, the Power Down Program is completed and the device returns to normal operation.
Figure 26. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View Note: Drawing is not to scale. Table 14. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data
Table 15. Ordering Information Scheme croelectronics Sales Office.
REVISION HISTORY
Table 16. Document Revision History Configuration Address respectively. Sleep mode renamed Deep Power-Down mode. ICCS removed and IPD renamed ICCPD in Table 10., DC Characteristics. Partial mode renamed Partial Array Refresh. Table 12. Write Mode AC Characteristics: tGHDZ added and Note 2 updated. tGHQZ changed to tGHDZ in Figure 13.Write Enable Controlled, Write AC Waveforms. AC Waveforms converted to ST standard. 15-Nov-2004 5.0 VOH value updated in Table 10., DC Characteristics.
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