M69AR048B STMICROELECTRONICS | Alldatasheet
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Technical content
1T/1C (one transistor per cell) memory family. can be implemented in a given area. standard Asynchronous SRAM Interface. the PSRAM array that contains essential data. than the maximum period for refresh. Figure 2. Logic Diagram Table 1. Signal Names
Figure 3. TFBGA Connections (Top view through package)
See Figure 2, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A20).The Address Inputs select the cells in the memory array to access dur- ing Read and Write operations. Data Inputs/Outputs (DQ8-DQ15).The Upper Byte Data Inputs/Outputs carry the data to or from the upper part of the selected address during a Write or Read operation, when Upper Byte Enable (UB ) is driven Low. Data Inputs/Outputs (DQ0-DQ7).The Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the selected address during a Write or Read operation, when Lower Byte Enable (LB ) is driven Low. Chip Enable (E1).When asserted (Low), the Chip Enable, E1, activates the memory state ma- chine, address buffers and decoders, allowing Read and Write operations to be performed. When de-asserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode. Chip Enable (E2).The Chip Enable, E2, puts the device in Power-down mode (Deep Power-Down or a Partial Power-Down mode ) when it is driven Low. Deep Power-down mode is the lowest power mode. Output Enable (G ).The Output Enable, G, pro- vides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. Write Enable (W ).The Write Enable, W, controls the Bus Write operation of the device. Upper Byte Enable (UB).The Upper Byte En- able, UB, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-DQ15) to or from the upper part of the selected address during a Write or Read operation. Lower Byte Enable (LB ).The Lower Byte En- able, LB, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7) to or from the lower part of the selected address during a Write or Read operation. V CC Supply Voltage.The V CC Supply Voltage supplies the power for all operations (Read, Write, etc.) and for driving the refresh logic, even when the device is not being accessed. V SS Ground. The VSS Ground is the reference for all voltage measurements.
Figure 4. Block Diagram
Operational modes are determined by device con- trol inputs W, E1, E2, LB and UB as summarized in the Operating Modes table (see Table 2). Power Up Sequence Because the internal control logic of the M69AR048B needs to be initialized, the following power-up procedure must be followed before the memory is used (see Figure 25., Power-Up Mode AC Waveforms): – Apply power and wait for V CC to stabilize – Wait 300µs while driving both Chip Enable signals (E1 and E2) High Read Mode The device is in Read mode when: – Write Enable (W) is High and – Output Enable (G) is Low and – the two Chip Enable signals are asserted (E1 is Low, and E2 is High). The time taken to enter Read mode (tELQV , tGLQV or tBLQV ) depends on which of the above signals was the last to reach the appropriate level. Data out (DQ15-DQ0) may be indeterminate during tELQX , tGLQX and tBLQX , but data will always be valid during tAVQV . See Figures 8, 9, 10, 11 and 12 and Table 11., Read Mode AC Characteristics, for details of when the outputs become valid. Write Mode The device is in Write mode when – Write Enable (W ) is Low and – at least one of Upper Byte Enable (UB) and Lower Byte Enable (LB) is Low – the two Chip Enable signals are asserted (E1 is Low, and E2 is High). The Write cycle begins just after the event (the fall- ing edge) that causes the last of these conditions to become true (t AVWL or tAVEL or tAVBL ). The Write cycle is terminated by the rising edge of Write Enable (W) or Chip Enable (E1), whichever occurs first. If the device is in Write mode (Chip Enable (E1) is Low, Output Enable (G) is Low, Upper Byte En- able (UB) and/or Lower Byte Enable (LB) is Low), then Write Enable (W) will return the outputs to high impedance within tWHDZ of its rising edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for t VWH before the rising edge of Write Enable (W), or for tDVEH before the rising edge of Chip Enable (E1), whichever occurs first, and remain valid for tWHDZ , tBHDZ or tEHDZ . See Figures 13, 14, 15, 16, 17 and 18, and Table 12., Write Mode AC Characteristics, for details of the timing requirements. Figures 19, 20, 21 and 22 show Read and Write mode AC waveforms. Standby Mode The device is in Standby mode when: – Chip Enable (E1) is High and – Chip Enable (E2) is High The input/output buffers and the decoding/control logic are switched off, but the dynamic array con- tinues to be refreshed. In this mode, the memory current consumption, I SB , is reduced, and the data remains valid. See Figure 26., Standby Mode Entry AC Wave- forms, After Read and Table 13., Standby Mode AC Characteristics for details. Power-Down Modes Description.The M69AR048B has four Power- down modes, Deep Power-down, 4Mbit Partial Power-Down, 8Mbit Partial Power-Down, and 16Mbit Partial Power-Down (see Table 3). These can be entered using a series of read and write operations. Each mode has the following fea- tures. The default state is Deep Power-Down and it is the lowest power consumption but all data will be lost once E2 is brought Low for Power-down. No sequence is required to put the device in Deep Power-down mode after Power-up. The device is in one of the Power-Down modes when: – Chip Enable (E2) is Low All the device logic is switched off and all internal operations are suspended. This gives the lowest power consumption. In this operating mode, no re- fresh is performed, and data is lost if the duration is longer than 10ns. This mode is useful for those applications where the data contents are no longer needed, and can be lost, but where reduced cur- rent consumption is of major importance. See Figure 24., Power-Down Mode AC Wave- forms and Table 13., Standby Mode AC Charac- teristics for details. Power-Down Program Sequence. The Power- Down Program sequence is used to program the Power-Down Configuration. It requires a total of six read and write operations, with specific addresses and data. Between each read or write operation the device must be in Standby mode. Table 4 and Figure 23. show the sequence. In the first cycle, the Byte at the highest memory address (MSB) is read. In the second and third cycles, the data (RDa) read by first cycle are written back. If the third cycle is written into a different address, the sequence is aborted, and the data written by the third cycle is valid as in a normal write operation. In the fourth and fifth cycles, the Power-Down Config-
Table 2. Operating Modes
- Should not be kept in this logic condition for a period longer than 1µs.
- Power-Down mode can be entered from Standby state and all DQ pins are in High-Z state. The Power-Down current and data re-
tention depend on the selection of the Power-Down programming.
- G can be VIL during the Write operation if the following conditions are satisfied:
b. G stays VIL during the entire Write cycle. Table 3. Power-Down Modes
Table 4. Power-Down Program Sequence Note: 1. PDC Power-Down Configuration. Table 5. Power-Down Configuration Data Table 6. Power-Down Configuration Addresses
Table 7. Absolute Maximum Ratings
Table 8. Operating and AC Measurement Conditions Note: 1. All voltages are referenced to VSS .
- The Input Transition Time used in AC measurements is 5ns. For other input transition times, see Table 8.
Figure 5. AC Measurement Load Circuit 1 F igure 6. AC Measurement Load Circuit 2 Table 9. Capacitance
Figure 7. AC Measurement I/O Waveform Table 10. DC Characteristics Note: 1. Maximum DC voltage on input and I/O pins is VCC +0 . 2 V . During voltage transitions, input may overshoot to VCC + 1.0V for a period of up to 5ns.
- Minimum DC voltage on input or I/O pins is –0.3V.
During voltage transitions, input may undershoot to VSS −1.0V for a period of up to 5ns.
- Partial stands for Partial Power-Down.
Table 11. Read Mode AC Characteristics contact your local ST representative for relaxation of the 1000ns limitation.
- Address should not be changed within minimum Read Cycle Time.
- The output load 5pF without any other load.
- Applicable to A3 to A20 when E1
- Applicable only to A0, A1 and A2 when E1 is kept Low for the page address access.
- In case Page Read Cycle is continued with keeping E1 stays Low, E1 must be brought to High within 4µs. In other words, Page
Read Cycle must be closed within 4µs.
- Applicable when at least two of address inputs among applicable are switched from previous state.
- Minimum Read Cycle TIme and minimum Page Read Cycle Time must be satisfied.
- Values obtained with AC Measurement Load Circuit 1 (see Figure 5). If the test conditions correspond to AC Measurement Load
Circuit 2 (see Figure 6), 10ns must be added to the times given in the above table.
Figure 12. Random and Page Address Controlled, Read Mode AC Waveforms
Table 12. Write Mode AC Characteristics local ST representative for relaxation of the 1000ns limitation.
- Minimum value must be equal to or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWRC, tWR or
- Write pulse is defined from the falling edge of E1, W, or LB/UB, whichever occurs last.
- Write recovery is defined from Write pulse is defined from the rising edge of E1, W, or LB/UB, whichever occurs first.
- Applicable to any address change when E1 stays Low.
- If G is Low after minimum tGHEL, the read cycle is initiated. In other words, G must be brought High within 5ns after E1 is brought
Low. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time is met.
- If G is Low after new address input, the read cycle is initiated. In other words, G must be brought High at the same time or before
new address valid. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time is met.
Table 13. Standby Mode AC Characteristics Note: 1. Applicable also to Power-up.
- Applicable when 4M, 8M or 16M Partial Power-Down mode is programmed
- Some data might be written into any address location if tEHWL (min) is not satisfied.
- The Input Transition Time (tτ) at AC testing is 5ns as shown below. If actual tτ is longer than 5ns, it may violate AC specification
Figure 23. Power-Down Programming AC Waveforms
- All address inputs must be High from Cycle 1 to Cycle 5.
- PDCADD stands for Power-Down Configuration Address. It must be compliant with the format specified in Table 6 otherwise the
data programmed during the Power-Down Program sequence may be incorrect.
- PDCDAT stands for Power-Down Configuration Data. It must be compliant with the format specified in Table 5 otherwise the data
programmed during the Power-Down Program sequence may be incorrect.
- tEHEL after the end of Cycle 6, the Power-Down Program is completed and the device returns to normal operation.
Figure 27. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View Note: Drawing is not to scale. Table 14. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data
Table 15. Ordering Information Scheme croelectronics Sales Office.
REVISION HISTORY
Table 16. Document Revision History 12-Mar-2003 3.0 Document completely revised. Speed class changed to 80ns. Timing diagrams changed. Voltage levels for operating modes changed. 07-Jul-2003 3.5 Entries for tAVEL and tEHAX corrected to -5ns. Document status set to Preliminary Data. Input capacitance added to Figure 5., and title changed to AC Measurement Load Circuit 1. Figure 6., AC Measurement Load Circuit 2. Note 2 to Figure 10., UB/LB Controlled, Read Mode AC Waveforms, modified. 5-Oct-2005 5.0 Datasheet status updated to Full Datasheet. Note 3 removed from in tBHQZ , tEHQZ and tGHQZ Table 11., Read Mode AC Characteristics.
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