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This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. Addendum to M68000 User Manual M68000 Ó 1997 Motorola, Inc. All Rights Reserved. Communications and Advanced Consumer Technologies Group SEMICONDUCTOR PRODUCT INFORMATION August 7, 1997 This addendum to the M68000UM/AD User’s Manual , Revision 8, provides corrections to the original text as well as additional information. This document and other information on this product is maintained on the World Wide Web at http://www.motorola.com/68000. OVERVIEW This manual includes hardware details and programming information for the MC68HC000, the MC68HC001, the MC68EC000, and the MC68SEC000. For ease of reading, the name M68000 MPUs will be used when referring to all processors. Refer to M68000PM/AD, M68000 Programmer's Reference Manual , for detailed information on the MC68000 instruction set. The four microprocessors are very similar to each other and all contain the following features:

• Sixteen 32-Bit Data and Address Registers
• 16-Mbyte Direct Addressing Range
• Program Counter
• 6 Instruction Types
• Operations on Five Main Data Types
• Memory-Mapped Input/Output (I/O)
• 14 Addressing Modes The following processors contain additional features:
• MC68HC001/MC68EC000/MC68SEC000 — Statically selectable 8- or 16-bit data bus
• MC68HC000/MC68EC000/MC68HC001/MC68SEC000 — Low power

M68000 USER’S MANUAL ADDENDUM MOTOROLA The primary features of the MC68SEC000 embedded processor include the following:

• Direct Replacement for the MC68EC000 — Pin-for-pin compatibility with the MC68EC000 in the plastic QFP and TQFP packages — Vast selection of existing third-party development tools for the MC68EC000 support the MC68SEC000 — Software written for the MC68EC000 will run unchanged on the MC68SEC000
• Power Management — Low-power HCMOS technology — Static design allows for stopping the processor clock — 3.3V or 5V operation — Typical 0.5 m A current consumption at 3.3V in sleep mode
• Software Strength — Fully upward object-code compatible with other M68000 Family products — M68000 architecture allows effective assembly code with a C compiler
• Upgrade — Fully upward code-compatible with higher performance 680x0 and 68300 Family members — ColdFire code-compatible with minor modifications 1. MC68HC000 The primary benefit of the MC68HC000 is reduced power consumption. The device dissipates less power (by an order of magnitude) than the NMOS MC68000. The MC68HC000 is an implementation of the M68000 16/-32 bit microprocessor architecture. The MC68HC000 has a 16-bit data bus implementation of the MC68000 and is upward code-compatible with the MC68010 and the MC68020 32-bit implementation of the architecture.

1.1 MC68HC001

The MC68HC001 provides a functional extension to the MC68HC000 HCMOS 16-/32-bit microprocessor with the addition of statically selectable 8- or 16-bit data bus operation. The MC68HC001 is object-code compatible with the MC68HC000. You can migrate code written for the MC68HC001 without modification to any member of the M68000 Family.

1.2 MC68EC000

The MC68EC000 is an economical high-performance embedded controller designed to suit the needs of the cost-sensitive embedded-controller market. The HCMOS MC68EC000 has an internal 32-bit architecture that is supported by a statically selectable 8- or 16-bit data bus. This architecture provides a fast and efficient processing device that can satisfy the requirements of sophisticated applications based on high-level languages. The MC68EC000 is fully object-code compatible with the MC68000. You can migrate code written for the MC68EC000 without modification to any member of the M68000 Family. The MC68EC000 brings the performance level of the M68000 Family to cost levels previously associated with 8-bit microprocessors. The MC68EC000 benefits from the rich M68000 instruction set and its related high code density with low memory bandwidth requirements.

M68000 USER’S MANUAL ADDENDUM

1.3 MC68SEC000

The MC68SEC000 is a cost-effective static embedded processor engineered for low-power applications. In addition to providing the substantial cost and performance benefits of the MC68EC000, the low-power mode of the MC68SEC000 provides significant advantages in power consumption and power management. The typical current consumption of the MC68SEC000 is only 0.5 m A in static standby mode and 15.0mA in normal consumption, small footprint packages, and static implementation are combined in the MC68SEC000 for low- power applications such as portable measuring equipment, electronic games, and battery-operated hand-held consumer products. The HCMOS MC68SEC000’s static architecture is a direct replacement for the MC68EC000, which offers the lowest cost entry point to 32-bit processing. The internal 32-bit architecture provides fast and efficient processing that satisfies the requirements of sophisticated applications based on high-level languages. All of the existing third-party developer tools widely available for the MC68EC000 will directly support the MC68SEC000. You can find detailed descriptions of these tools in the High Performance Embedded Systems Source Catalog

2.0 SIGNAL DESCRIPTION

Change Figure 3-3 on Page 3-2. Figure 1. Input and Output Signals (MC68EC000 and MC68SEC000)

2.1 Data Bus (D15-D0)

2.2 Bus Arbitration Control

2.3 System Control

2.4 MC68SEC000 Low-Power Mode

Add the following to Sections 4 and 5, Bus Operation.

processor clock is disabled, it is often necessary to disable the clock to other sections of your circuit. MC68SEC000. A timing diagram is shown in Figure 4. Figure 4. MC68SEC000 Clock Stop Timing for 16-Bit Data Bus pull-up or pull-down resistor.

1. This step is optional depending on whether your applications require the MC68SEC000 signals with

5.2 Bus Arbitration

for the STOP instruction. A timing diagram with the bus arbitration sequence is shown in Figure 5. Figure 5. MC68SEC000 Clock Stop Timing with Bus Arbitration for 16-Bit Data Bus

1. Restart the system clock if it was stopped.
2. Wait for the system clock to become stable.

the system clock. Figure 6 shows the timing for bringing the processor out of the low-power mode. the Electrical Characteristics section of this addendum. Figure 6. MC68SEC000 Clock Start Timing

1. If the MC68SEC000 was placed in a three-state condition, the BR

processor can begin executing instructions.

M68000 USER’S MANUAL ADDENDUM MOTOROLA An example trap routine is as follows: TRAP_x MOVE.B #0,$low_power_address /* Write that causes ADDRESS_MATCH to assert */ STOP #$2000 /* STOP instruction with desired interrupt mask */ RTE /* Return from the exception */ The first instruction (MOVE.B #0,$low_power_address) writes a byte to the low-power address that will cause the external circuitry to begin the sequence that will stop the processor’s clock. The second instruction (STOP #$2000) loads the SR with the immediate data. This lets you set the interrupt that will cause the processor to come out of the low-power mode. The final instruction (RTE) tells the processor to return from the exception and resume normal processing.

3.0 MC68SEC000 ELECTRICAL SPECIFICATIONS

Add to the following table to Section 10.1.

3.1 MC68SEC000 MAXIMUM RATINGS

3.2 CMOS CONSIDERATIONS

The following change should be made to Section 10.4, CMOS Considerations. “Although the MC68HC000 and MC68EC000 is implemented with input protection diodes, care should be exercised to ensure that the maximum input voltage specification is not exceeded.” should read “Although the MC68HC000, MC68EC000, and MC68SEC000 are implemented with input protection diodes, be careful not to exceed the maximum input voltage specification.” RATING SYMBOL VALUE UNIT Supply Voltage V CC –0.3 to 6.5 V Input Voltage V in –0.5 to 6.5 V Maximum Operating Temperature Range Commercial Extended "C" Grade T A T L to T H 0 to 70 –40 to 85 C Storage Temperature Tstg –55 to 150 C

4.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS

Replace Figure 10-2 on page 10-6 with Figure 7. Figure 7. Drive Levels and Test Points for AC Specifications - applies to all parts

1. This output timing is applicable to all parameters specified relative to the rising edge of the clock.
2. This output timing is applicable to all parameters specified relative to the falling edge of the clock.
3. This input timing is applicable to all parameters specified relative to the rising edge of the clock.
4. This input timing is applicable to all parameters specified relative to the falling edge of the clock.
5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal.

A. Maximum output delay specification. B. Minimum output hold time. C. Minimum input setup time specification. D. Minimum input hold time specification. E. Signal valid to signal valid specification (maximum or minimum). F. Signal valid to signal invalid specification (maximum or minimum).

M68000 USER’S MANUAL ADDENDUM MOTOROLA

5.0 MC68SEC000 DC ELECTRICAL SPECIFICATIONS

Add the following table to Section 10.13 on page 10-23. CC = 5.0 Vdc 5%, 3.3 Vdc 10%,; GND = 0 Vdc; T A = T L to T H *During normal operation, instantaneous Vcc current requirements may be as high as 1.5A. Currents listed are with no loading. **Capacitance is periodically sampled rather than 100% tested. 3.3 V 5.0 V CHARACTERISTIC SYMBOL MIN MAX MIN MAX UNIT Input High Voltage V IH 2.0 V CC 2.0 V CC V Input Low Voltage V IL GND 0.8 GND – 0.5 0.8 V Input Leakage Current BERR, BR, DTACK, CLK, I PL2-IPL0, AVEC MODE, HALT, RESET Iin — 2.5 — 2.5 uA Three-State (Off State) Input Current I TSI — 2.5 — 2.5 uA Output High Voltage V OH 2.4 — V CC –0.75 — V Output Low Voltage (IOL = 1.6 mA) HALT (IOL = 3.2 mA) A23–A0, BG, FC2–FC0 (IOL = 5.0 mA) RESET (IOL = 5.3 mA) AS, D15–D0, LDS, R/W, UDS V OL 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 V Current Dissipation* f = 0 Hz I D — 0.7 — 1.0 mA f=10MHz — 10 — 15 mA f=16 MHz — 15 — 25 mA f= 20 MHz — 20 — 30 mA Capacitance (Vin = 0 V, T A = 25 C, Frequency = 1 MHz)** Cin — 20.0 — 20.0 pF Load Capacitance HALT All Others CL — 70 130 —7 0 130 pF

6.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS — CLOCK

Add the following table and Figure 8 to Section 10.9 on page 10-9. Figure 8. MC68SEC000 Clock Input Timing Diagram

1 Cycle time tcyc 100 — 60 — 50 — ns

fall will be linear between 0.8 V and 2.0 V.

M68000 USER’S MANUAL ADDENDUM MOTOROLA

7.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS — READ AND

Add the following table and Figures 9 and 10 to Section 10.16. Applies to 3.3V and 5V. (GND = 0 V; T A = T L to T H ; see Figures 3 and 4) NUM CHARACTERISTIC 10MHz 16MHz 20MHz UNITMIN MAX MIN MAX MIN MAX

6 Clock Low to Address Valid — 35 — 30 — 25 ns

6A Clock High to FC Valid 0 35 0 30 0 25 ns

7 Clock High to Address, Data Bus High Impedance (Maximum)

(Write) —5 5—5 0—4 2n s

8 Clock High to Address, FC Invalid (Minimum) 0—0—0— n s

Clock High to AS, LDS, UDS Asserted 3 35 3 30 3 25 ns Address Valid to AS, LDS, UDS Asserted (Read)/ AS Asserted (Write) 2 0—1 5—1 0—n s 11A FC Valid to AS, LDS, UDS Asserted (Read)/ AS Asserted (Write) 45 — 45 — 40 — ns Clock Low to AS, LDS, UDS Negated 3 35 3 30 3 25 ns AS , LDS, UDS Negated to Address, FC Invalid 15 — 15 — 10 — ns AS (and LDS, UDS Read) Width Asserted 195 — 120 — 100 — ns 14A LDS , UDS Width Asserted (Write) 95 — 60 — 50 — ns AS , LDS, UDS Width Negated 105 — 60 — 50 — ns

16 Clock High to Control Bus High Impedance — 55 — 50 — 42 ns

AS , LDS, UDS Negated to R/W Invalid 15 — 15 — 10 — ns Clock High to R/W High (Read) 0 35 0 30 0 25 ns Clock High to R/W Low (Write) 0 35 0 30 0 25 ns 20A 2,6 AS Asserted to R/W Low (Write) — 10 — 10 — 10 ns Address Valid to R/W Low (Write) 0—0—0— n s 21A FC Valid to R/W Low (Write) 50 — 30 — 25 — ns R/W Low to DS Asserted (Write) 50 — 30 — 25 — ns

23 Clock Low to Data-Out Valid (Write) — 35 — 30 — 25 ns

AS , LDS, UDS Negated to Data-Out Invalid (Write) 30 — 15 — 10 — ns Data-Out Valid to LDS, UDS Asserted (Write) 30 — 15 — 10 — ns Data-In Valid to Clock Low (Setup Time on Read) 5—5—5— n s AS , LDS, UDS Negated to DTACK Negated (Asynchronous Hold) 0 110 0 110 0 95 ns 28A Clock High to DTACK Negated 0 110 0 110 0 95 ns

M68000 USER’S MANUAL ADDENDUM MOTOROLA AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (Continued) Applies to 3.3V and 5V. NOTES: 1. For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum columns. 2. Actual value depends on clock period. 3. If #47 is satisfied for both DT ACK and BERR, #48 may be ignored. In the absence of DTACK , BERR is an asynchronous input using the asynchronous input setup time (#47). 4. For power-up, the MC68SEC000 must be held in the reset state for 100 ms to allow stabilization of on-chip circuitry. After the system is powered up, #56 refers to the minimum pulse width required to reset the controller. 5. If the asynchronous input setup time (#47) requirement is satisfied for DTACK , the DTACK asserted to data setup time (#31) requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle. 6. When AS and R/W are equally loaded ( 20%), subtract 5 ns from the values given in these columns. 7. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted. NUM CHARACTERISTIC 10MHz 16MHz 20MHz UNITMIN MAX MIN MAX MIN MAX

29 AS , LDS, UDS Negated to Data-In Invalid (Hold Time on Read)0—0—0— n s

29A AS , LDS, UDS Negated to Data-In High Impedance (Read) — 150 — 90 — 75 ns

30 AS , LDS, UDS Negated to BERR Negated 0—0—0— n s

2,5 DTACK Asserted to Data-In Valid (Setup Time on Read) — 65 — 50 — 42 ns

32 HALT and RESET Input Transition Time 0 150 0 150 0 150 ns

33 Clock High to BG Asserted — 35 — 30 — 25 ns

34 Clock High to BG Negated — 35 — 30 — 25 ns

38 BG Asserted to Control, Address, Data Bus High Impedance (AS

Negated) —5 5—5 0—4 2n s 39 BG Width Negated 1.5 — 1.5 — 1.5 — Clks

44 AS , LDS, UDS Negated to AVEC Negated 0 55 0 50 0 42 ns

Asynchronous Input Setup Time 5—5—5— n s 2,3 BERR Asserted to DTACK Asserted 20 — 10 — 10 — ns

52 Data-In Hold from Clock High 0—0—0— n s

53 Data-Out Hold from Clock High (Write) 0—0—0— n s

55 R/W Asserted to Data Bus Impedance Change (Write) 20 — 10 — 0 — ns

HALT , RESET Pulse Width 10 — 10 — 10 — Clks BR Negated to AS, LDS, UDS, R/W Driven 1.5 — 1.5 — 1.5 — Clks 58A BR Negated to FC Driven 1—1—1— Clks

Figure 9. MC68SEC000 Read Cycle Timing Diagram

1. Setup time for the asynchronous inputs IPL2–IPL0 and AVEC (#47) guarantees their recognition at the

next falling edge of the clock.

1. BR need fall at this time only to insure being recognized at the end of the bus cycle.
2. Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V,

range such that the rise or fall is linear between 0.8 V and 2.0 V.

Figure 10. MC68SEC000 Write Cycle Timing Diagram

1. Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V,

range such that the rise or fall is linear between 0.8 V and 2.0 V.

1. Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge

M68000 USER’S MANUAL ADDENDUM MOTOROLA

8.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS — BUS

Add the following table and Figure 11 to Section 10.17. (GND = 0 Vdc; T A = T L to T H ; refer to Figure 13) Applies to 3.3V and 5V. 1. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted. NUM CHARACTERISTICp 10MHz 16MHz 20MHz UNITMIN MAX MIN MAX MIN MAX

7 Clock High to Address, Data Bus High Impedance (Maximum) — 55 — 50 — 42 ns

33 Clock High to BG

Asserted 0 35 0 30 0 25 ns

34 Clock High to BG Negated 0 35 0 30 0 25 ns

Negated) —5 5—5 0—4 2n s 39 BG Width Negated 1.5 — 1.5 — 1.5 — Clks

47 Asynchronous Input Setup Time 5—5—5— n s

BR Negated to AS, LDS, UDS, R/W Driven 1.5 — 1.5 — 1.5 — Clks 58A BR Negated to FC Driven 1—1—1— Clks

Figure 13. Bus Arbitration Timing—Idle Bus Case NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V. This diagram also applies to the 68EC000.

Figure 14. Bus Arbitration Timing - Active Bus Case NOTE: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V. This diagram also applies to the 68EC000.

Figure 15. Bus Arbitration - Multiple Bus Request NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V. This diagram also applies to the 68EC000.

9.0 MECHANICAL DATA

9.1 PIN ASSIGNMENTS

Add Figure 12 to Section 11.1. Figure 16. 64-Lead Quad Flat Pack and 64-Lead Thin Quad Flat Pack

22 M68000 USER’S MANUAL ADDENDUM MOTOROLA

10.0 PACKAGE DIMENSIONS - FU SUFFIX

This diagram replaces the one on Page 11-16

64 Lead Quad Flat Pack Case 840B-01

A 16.95 17.45 0.667 0.687 B 13.90 14.10 0.547 0.555 C 16.95 17.45 0.667 0.687 D 13.90 14.10 0.547 0.555 G 0.30 0.45 0.012 0.018 H 0.80 BSC 0.031 BSC K 2.15 2.45 0.085 0.096 L 0.13 0.23 0.005 0.009 M 2.00 2.40 0.79 0.094 R 12.00 REF 0.472 REF S 12.00 REF 0.472 REF G R D C H M K L B SA

MOTOROLA M68000 USER’S MANUAL ADDENDUM 23

11.0 PACKAGE DIMENSIONS - PB SUFFIX

Add the following to Section 11.2.

64 Lead Thin Quad Flat Pack Case 840F-02

A 12.00 BSC 0.472 BSC A1 6.00 BSC 0.236 BSC B 10.00 BSC 0.394 BSC B1 5.00 BSC 0.197 BSC C 12.00 BSC 0.472 BSC C1 6.00 BSC 0.236 BSC D 10.00 BSC 0.394 BSC D1 5.00 BSC 0.197 BSC G 0.17 0.27 0.007 0.011 H 0.50 BSC 0.020 BSC L 0.09 0.20 0.004 0.008 M 1.35 1.45 0.053 0.057 G D C H M K L B B1A1 A

24 M68000 USER’S MANUAL ADDENDUM MOTOROLA

12.0 PACKAGE/FREQUENCY AVAILABILITY

Replaces Section 11.1 The following tables identify the packages and operating frequencies available for the MC68HC000, MC68HC001, MC68EC000, and the MC68SEC000. NOTE : ** not recommended for new designs MC68SEC000 PACKAGE FREQUENCY VOLTAGE

3.3 V 5 V

Quad Flat Pack (FU) Thin Quad Flat Pack (PB)

10 MHz

16 MHz

Plastic Quad Pack (PLCC) Plastic Quad (Gull Wing) Pin Grid Array, Solder Lead Finish Pin Grid Array, Gold Lead Finish 8,10,12,16,20 MHz 3 8,10,12,16,20 MHz 3 8,10,12,16,20 MHz 3 8,10,12,16,20 MHz 3 Plastic Quad Pack (PLCC) 8,10,12,16,20 MHz 3 MC68HC001 PACKAGE FREQUENCY VOLTAGE Plastic Quad Pack (PLCC) Plastic Quad (Gull Wing) Pin Grid Array, Gold Lead Finish 8,10,12,16 MHz 8,10,12,16 MHz 3 8,10,12,16 MHz 3 8,10,12,16 MHz 3 MC68EC000 PACKAGE FREQUENCY VOLTAGE Plastic Quad Pack (PLCC) Plastic Quad Flat Pack

8 MHz 3

10 MHz 3

12 MHz 3

16 MHz 3

20 MHz 3

MOTOROLA M68000 USER’S MANUAL ADDENDUM 25

ORDERING INFORMATION

Add the following to Section 11. The following tables contains the ordering information for the MC68SEC000. DOCUMENTATION Add to Section 11. The documents listed in the following table contain detailed information that pertain to the MC68SEC000 processor. You can obtain these documents from the Literature Distribution Centers listed on the last page of this document. PACKAGE BODY SIZE LEAD SPACING SPEED (IN MH Z) VOLTAGE SUFFIX TEMPERATURE RANGE QFP 14.0 mm X 14.0mm 0.8mm 10/16/20 MHz 3.3V or 5.0V FU 0C to +70C CFU -40C to +85C TQFP 10.0mm x 10.0mm 0.5mm PB 0C to +70C CPB -40C to +85C PACKAGE BODY SIZE LEAD SPACING SPEED (IN MHZ) VOLTAGE SUFFIX TEMPERATURE RANGE DIP 81.91mm X 20.57mm 2.54mm 8, 10, 12, 16 5.0V P 0C to +70C PLCC 25.57mm X 25.27mm 1.27mm 8, 10, 12, 16, 20 FN 0C to +70C 8, 10, 12, 16 CFN -40C to +85C PACKAGE BODY SIZE LEAD SPACING SPEED (IN MHZ) VOLTAGE SUFFIX TEMPERATURE RANGE PLCC 25.57mm X 25.27mm 1.27mm 8, 10,12, 16, 20 5.0V FN 0C to +70C PQFP 14.1mm X 14.1mm 0.8mm 8, 10,12, 16, 20 FU MC68SEC000 Documentation MC68SEC000 DOCUMENTATION DOCUMENT NUMBER M68000 Family Programmer’s Reference Manual M68000PM/AD M68000 User’s Manual M68000UM/AD High Performance Embedded Systems Source Catalog‘‘ BR729/D MC68EC000 Product Brief MC68EC000/D MC68SEC000 Product Brief MC68SEC000/D

SEMICONDUCTOR PRODUCT INFORMATION Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P .O. Box 20912, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.