M66280FP RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 14
Technical content
Features
- Memory configuration: 5120 words × 8 bits (dynamic memory)
- High speed cycle: 25 ns (Min)
- High speed access: 18 ns (Max)
- Output hold: 3 ns (Min)
- Reading and writing operations can be completely carried out independently and asynchronously
- Variable length delay bit
- Input/output: TTL direct connection allowable
- Output: 3 states Application Digital copying machine, laser beam printer, high speed facsimile, etc. Block Diagram 718 Read address counter Write address counter Read control circuit Write control circuit Input buffer Memory array 5120 × 8 bits 13 14 15 16 21 22 2423 1 2 3 4 9 10 11 12 REB RRESB RCK Read enable input Read reset input Read clock input Write enable input Data inputs D0 to D7 Data outputs Q0 to Q7 Write reset input Write clock input GND WEB WRESB WCK VCC Output buffer
REJ03F0253-0200 Rev.2.00 Sep 14, 2007 Page 2 of 13 Pin Arrangement WEB WRESB V CC WCK REB RRESB GND RCK Data inputData output Data output Data input M66280FP (Top view) Outline: PRSP0024GA-A (24P2Q-A) Write enable input Write reset input Write clock input Read enable input Read reset input Read clock input
REJ03F0253-0200 Rev.2.00 Sep 14, 2007 Page 3 of 13 Absolute Maximum Ratings (Ta = 0 to 70°C, unless otherwise noted) Item Symbol Ratings Unit Conditions Supply voltage V CC −0.3 to +4.6 V Input voltage V I −0.3 to VCC + 0.3 V Output voltage V O −0.3 to VCC + 0.3 V Value based on the GND pin Power dissipation Pd 300 mW Ta = 25°C Storage temperature Tstg −55 to 150 °C Recommended Operating Conditions Item Symbol Min Typ Max Unit Supply voltage V CC 2.7 3.15 3.6 V Supply voltage GND 0 V Operating temperature Topr 0 70 °C
Electrical Characteristics
(Ta = 0 to 70°C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted) Item Symbol Min Typ Max Unit Test Conditions High-level input voltage V IH 2.0 V Low-level input voltage V IL 0.8 V High-level output voltage V OH V CC − 0.8 V I OH = −4 mA Low-level output voltage V OL 0.55 V I OL = 4 mA High-level input current I IH 1.0 µA V I = VCC WEB, WRESB, WCK, REB, RRESB, RCK, D0 to D7 Low-level input current I IL −1.0 µA V I = GND WEB, WRESB, WCK, REB, RRESB, RCK, D0 to D7 Off-state high-level output current I OZH 5.0 µA V O = VCC Off-state low-level output current I OZL −5.0 µA V O = GND Average supply current during operation I CC 70 mA V I = VCC, GND, Output open tWCK, tRCK = 25 ns Input capacitance C I 10 pF f = 1 MHz Off-time output capacitance C O 15 pF f = 1 MHz Function When write enable input WEB is set to "L", the contents of data inputs D0 to D7 are read in synchronization with a rising edge of write clock input WCK to perform writing operation. When this is the case, the write address counter is also incremented simultaneously. When WEB is set to "H", the writing operation is inhibited and the write address counter stops. When write reset input WRESB is set to "L", the write address counter is initialized. When read enable input REB is set to "L", the contents of memory are output to data outputs Q0 to Q7 in synchronization with a rising edge of read clock input RCK to perform reading operation. When this is the case, the read address counter is incremented simultaneously. When REB is set to "H", the reading operation is inhibited and the read address counter stops. The outputs are placed in a high impedance state. When read reset input RRESB is set to "L", the read address counter is initialized.
REJ03F0253-0200 Rev.2.00 Sep 14, 2007 Page 4 of 13 Switching Characteristics (Ta = 0 to 70°C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted) Item Symbol Min Typ Max Unit Access time t AC 18 ns Output hold time t OH 3 ns Output enable time t OEN 3 18 ns Output disable time t ODIS 3 18 ns Timing Requirements (Ta = 0 to 70°C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted) Item Symbol Min Typ Max Unit Write clock (WCK) cycle t WCK 25 ns Write clock (WCK) "H" pulse width t WCKH 11 ns Write clock (WCK) "L" pulse width t WCKL 11 ns Read clock (RCK) cycle t RCK 25 ns Read clock (RCK) "H" pulse width t RCKH 11 ns Read clock (RCK) "L" pulse width t RCKL 11 ns Input data setup time for WCK t DS 7 ns Input data hold time for WCK t DH 3 ns Reset setup time for WCK/RCK t RESS 7 ns Reset hold time for WCK/RCK t RESH 3 ns Reset non-selection setup time for WCK/RCK t NRESS 7 ns Reset non-selection hold time for WCK/RCK t NRESH 3 ns WEB setup time for WCK t WES 7 ns WEB hold time for WCK t WEH 3 ns WEB non-selection setup time for WCK t NWES 7 ns WEB non-selection hold time for WCK t NWEH 3 ns REB setup time for RCK t RES 7 ns REB hold time for RCK t REH 3 ns REB non-selection setup time for RCK t NRES 7 ns REB non-selection hold time for RCK t NREH 3 ns Input pulse up/down time tr, tf 20 ns Data hold time* tH 20 ms Notes: Perform reset operation after turning on power supply. * For 1 line access, the following conditions must be satisfied: WEB high-level period ≤ 20 ms − 5120 • tWCK − WRESB low-level period REB high-level period ≤ 20 ms − 5120 • tRCK − RRESB low-level period
REJ03F0253-0200 Rev.2.00 Sep 14, 2007 Page 5 of 13 Switching Characteristics Measurement Circuit CL = 30 pF: tAC, tOH Qn CL = 5 pF: tOEN, tODIS SW1 SW2 RL = 1 kΩ RL = 1 kΩ VCC Qn Input pulse level: 0 to 3 V Input pulse up/down time: 3 ns Judging voltage Input: 1.3 V Output: 1.3 V (However, t ODIS (LZ) is judged with 10% of the output amplitude, while tODIS (HZ) is judged with 90% of the output amplitude) Load capacitance C L includes the floating capacity of connected lines and input capacitance of probe. Item SW1 SW2 tODIS (LZ) Close Open tODIS (HZ) Open Close tOEN (ZL) Close Open tOEN (ZH) Open Close tODIS and tOEN Measurement Condition RCK REB Qn Qn VOL VOH GND 3 V GND 3 V 1.3 V 1.3 V 1.3 V tOEN (ZH) tOEN (ZL) 1.3 V 90% 10% tODIS (HZ) tODIS (LZ)
REJ03F0253-0200 Rev.2.00 Sep 14, 2007 Page 6 of 13 Operation Timing Write Cycle WCK WEB Dn tWCK n cycle n + 1 cycle n + 2 cycle WRESB = "H" (n + 4) n + 3 cycle n + 4 cycleDisable cycle tWCKH tWEH tNWES tNWEH tWEStWCKL tDS tDH Write Reset Cycle WCK WRESB Dn tWCK n − 1 cycle n cycle WEB = "L" (2) 1 cycle0 cycle 2 cycleReset cycle tNRESH tRESH tNRESStRESS tDS tDH
REJ03F0253-0200 Rev.2.00 Sep 14, 2007 Page 7 of 13 Matters that Needs Attention when WCK Stops WCK WEB Dn tWCK Period for writing data (n) into memory Period for writing data (n) into memory tNWES n cycle n cycle Disable cyclen + 1 cycle (n) (n) WRESB = "H" tDS tDH tDS tDH Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of n + 1 cycle. The writing operation is complete at the falling edge after n + 1 cycle. To stop reading write data at n cycle, enter WCK before the rising edge after n + 1 cycle. When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
REJ03F0253-0200 Rev.2.00 Sep 14, 2007 Page 8 of 13 Read Cycle RCK REB Qn tRCK n cycle n + 1 cycle n + 2 cycle RRESB = "H" (n + 4) n + 3 cycle n + 4 cycleDisable cycle HIGH-Z tRCKH tREH tNRES tNREH tRES tAC tRCKL tODIS tOEN tOH Read Reset Cycle RCK RRESB Qn tRCK n − 1 cycle n cycle REB = "L" (2) 1 cycle0 cycle 2 cycleReset cycle tNRESH tRESH tNRESS tAC tOH tRESS
REJ03F0253-0200 Rev.2.00 Sep 14, 2007 Page 9 of 13 Variable Length Delay Bit
1 Line (5120 Bits) Delay
Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK before read cycle to easily make 1 line delay. WCK RCK Dn Qn WRESB RRESB WEB, REB = "L" tRESHtRESS tDHtDS tDH tOHtAC5120 cycle tDS 1 cycle0 cycle 5118 cycle 5119 cycle 5120 cycle (0') 5121 cycle (1') 5122 cycle (2')2 cycle (0) (1) (2) (3) n-bit Delay Bit (Reset at cycles according to the delay length) WCK RCK Dn Qn WRESB RRESB WEB, REB = "L" m ≥ 3 tRESHtRESS tDHtDS tDH tOHtACm cycle tDS tRESHtRESS 1 cycle0 cycle n − 2 cycle n − 1 cycle n cycle (0') n + 1 cycle (1') n + 2 cycle (2') n + 3 cycle (3')2 cycle (0) (1) (2) (3)
REJ03F0253-0200 Rev.2.00 Sep 14, 2007 Page 10 of 13 n-bit Delay 2 (Slides input timings of WRESB and RRESB at cycles according to the delay length) WCK RCK Dn Qn WRESB WEB, REB = "L" m ≥ 3 tRESHtRESS tDHtDS tDH tOHtACm cycle tDS 1 cycle0 cycle n − 1 cycle n cycle n + 1 cycle n + 2 cycle n + 3 cycle2 cycle n − 2 cycle (0) (1) (2) (3) RRESB tRESHtRESS n-bit Delay 3 (Slides address by disabling REB in the period according to the delay length) WCK RCK Dn Qn WRESB RRESB WEB = "L" m ≥ 3 tRESHtRESS tDHtDS tDH tOHtACm cycle HIGH-Z tDS 1 cycle0 cycle n − 1 cycle n cycle n + 1 cycle n + 2 cycle n + 3 cycle2 cycle (0) (1) (2) (3) REB tREStNREH
REJ03F0253-0200 Rev.2.00 Sep 14, 2007 Page 11 of 13 Reading Shortest n-cycle Write Data "n" (Reading side n − 1 cycle starts after the end of writing side n − 1 cycle) When the reading side n − 1 cycle starts before the end of the writing side n + 1 cycle, output Qn of n cycle is made invalid. In the following diagram, reading operation of n − 1 cycle is invalid. (n) (n +2) (n +3) n cycle n + 1 cycle n − 2 cycle n − 1 cycle n cycle (n)Invalid n + 2 cycle n + 3 cycle WCK Dn Qn RCK (n +1) Reading Longest n-cycle Write Data "n": 1 Line Delay (When writing side n-cycle <2>* starts, reading side n cycle <1>* then starts) Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each other. n cycle <1>* WCK Dn Qn RCK n cycle <0>* 0 cycle <2>* 0 cycle <1>* n cycle <2>* n cycle <1>* Note: <0>*, <1>* and <2>* indicate value of lines.
REJ03F0253-0200 Rev.2.00 Sep 14, 2007 Page 12 of 13 Application Example Sub Scan Resolution Compensation Circuit with Laplacian Filter M66280 × 2 Compensated image data (n − 1) line K: Laplacian coefficient A N B n line (n + 1) line × K 1 line delay to to M66280 A (n − 1) line image data B (n + 1) line image data Adder A + B Subtractor 2N − (A + B) Adder N n line image data 1 line delay to to Main scan direction Sub scan direction
REJ03F0253-0200 Rev.2.00 Sep 14, 2007 Page 13 of 13 Package Dimensions F 1 12 1324 Index mark y E HE e bp D A c Detail F A1A2 L INCLUDE TRIM OFFSET. DIMENSION "*3" DOES NOT NOTE) DO NOT INCLUDE MOLD FLASH. A1 0 0.1 0.2 Previous CodeJEITA Package Code RENESAS Code PRSP0024GA-A 24P2Q-A MASS[Typ.] 0.2gP-SSOP24-5.3x10.1-0.80 0.250.20.18 0.450.350.3 MaxNomMin Dimension in Millimeters Symbol Reference 10.210.110.0D 5.45.35.2E 1.8A2 8.17.87.5 2.1A 0.80.60.4L 8°0° c 0.8e 0.10y HE bp 0.65 0.95
Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 RENESAS SALES OFFICES © 2007. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .7.0