M66271FP RENESAS | Alldatasheet

Document overview

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Technical content

Features

  • Displayable LCD  Monochrome STN dot matrix type LCD of up to 76800 dots (equivalent to 320 × 240 dots)  Maximum display duty: 1/240 (set to 240 line) : 1/255 (Max)
  • Display memory  Built-in 9600-byte (76800-bit) VRAM (equivalent to one screen of 320 × 240 dots LCD)  All addresses of built-in VRAM are externally opened.
  • Interface with MPU  Capability of switching 8-bit type MPU/16-bit type MPU  With WAIT output pin (Accessing register from MPU without WAIT output. Accessing VRAM from MPU with WAIT output.)  Capability of controlling BHE or LWR/HWR at the interface with a 16-bit MPU.
  • Interface with LCD  LCD display data are 4-bit parallel output  4 kinds of control signals: CP, LP, FLM and M
  • Display functions  Graphic display only (characters drawn graphically)  Binary display only (without tone display function)  Vertical scrolling is allowed within memory range (small size LCD only)
  • Additional function for LCD module built-in system  15 kinds of interface with MPU: A <4:1>, D <7:0>, IOCS, LWR, RD  Accessing VRAM from MPU through I/O register  Capability of interfacing with 8-bit type MPU only
  • 5 V single power supply
  • 80-pin QFP Application
  • PPC/FAX operation panel, display/operation panel of other OA equipment
  • Multi-function/public telephones
  • PDA/electronic notebook/information terminal
  • Other applications using LCD of 76800 dots or less

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 2 of 27 Block Diagram 1 MPU I/F control circuit Address buffer Data buffer (Basic timing control) Clock control Bus arbiter timing control (Cycle steal control) Control register LCD display timing control circuit LCD display data control circuit Oscillator output Oscillator input Wait MPU clock Bus high enable Reset 8/16 MPU select Read strobe Low write strobe High write strobe VRAM chip select Control register chip select MPU address bus A <13:0> D <15:0>MPU data bus IOCS MCS HWR LWR RD RESET BHE WAIT MPUSEL MPUCLK OSC1 OSC2 VRAM 9600-byte

61 LCDENB

M 1 806564514110 13 24 25 35 40 32 76757433 36 37 38 39 73 8 23 34 42 52 53 77 VSS VDD N.C UD <3:0> LCD display data bus LCD control signal Display data transfer clock Display data latch pulse First line marker signal LCD alternating signal Block Diagram 2 (In case of LCD module built-In system) 3 6 7 9 11 12 14 15 MPU I/F control circuit 20 22_ 26 31_ 53 60_ Address buffer Data buffer (Basic timing control) Clock control Bus arbiter timing control Control register LCD display timing control circuit LCD display data control circuit Oscillator output Oscillator input Read strobe Low write strobe Control register chip select MPU address bus A <4:1> D <7:0>MPU data bus IOCS LWR RD OSC1 OSC2 VRAM 9600-byte M 1 806564514110 13 24 25 35 40 32 76757433 36 37 38 39 73 8 23 34 42 52 63 77 VSS VDD N.C UD <3:0> LCD display data bus LCD control signal Display data transfer clock Display data latch pulse First line marker signal LCD alternating signal No use pins VRAM address index register Data port register

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 3 of 27 Pin Arrangement (Top view) VSS VSS VSS VSS VDD VDD VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VSS VDD N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C A <13> D <15> UD <0> UD <1> UD <2> UD <3> D <14> D <13> D <12> D <11> D <10> D <9> D <8> A <12> A <11> A <10> A <9> A <8> A <0> A <1> A <2> A <3> A <4> A <5> A <6> A <7> D <7> D <6> D <5> D <4> D <3> D <2> D <1> D <0> M LCDENB LCD control signal LCD alternating signal MPU data bus MPU data bus CP LP FLM OSC1 OSC2 Display data transfer clock Display data latch pulse First line marker LCD display data bus Oscillator input Oscillator output Control register chip select High write strobe Low write strobe Read strobe VRAM chip select Wait MPU clock Reset Bus high enable MPU address bus 8/16 MPU select IOCS HWR LWR RD MCS WAIT RESET BHE MPUSEL MPUCLK MPU address bus M66271FP N.C: No connection Outline: PRQP0080GB-A (80P6N-A)

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 5 of 27 Absolute Maximum Ratings (Ta = 0 to +70°C unless otherwise noted) Item Symbol Ratings Unit Supply voltage V DD –0.3 to +6.5 V Input voltage V I –0.3 to V DD + 0.3 V Output voltage V O –0.3 to V DD + 0.3 V Output current I O 10 mA Power dissipation Pd 600 mW Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions (Ta = 0 to +70°C unless otherwise noted) Item Symbol Min Typ Max Unit Supply voltage V DD 4.5 5.0 5.5 V Supply voltage V SS — 0 — V Input voltage V I 0 — V DD V Output voltage V O 0 — V DD V Operating temperature Topr 0 +25 +70 °C

Electrical Characteristics

(VDD = 5 V ± 10%, Ta = 0 to +70°C unless otherwise noted) Item Symbol Min Typ Max Unit Test Conditions High-level input voltage V IH 2.2 — — V V DD = 5.5 V Low-level input voltage All inputs except for OSC1, RESET and MPUSEL VIL — — 0.8 V V DD = 4.5 V High-level input voltage V IH 3.5 — — V V DD = 5.5 V Low-level input voltage OSC1 VIL — — 1.0 V V DD = 4.5 V Positive-going threshold voltage VT+ 2.3 — 3.7 V V DD = 5.0 V Negative-going threshold voltage MPUSEL, RESET V T– 1.25 — 2.3 V V DD = 5.0 V High-level output voltage V OH 4.1 — — V I OH = –4 mA Low-level output voltage All outputs except for OSC2 and outputs of D <15:0> VOL — — 0.4 V VDD = 4.5 V IOL = 4 mA High-level output voltage V OH 4.1 — — V I OH = –50 µA Low-level output voltage OSC2 VOL — — 0.4 V VDD = 4.5 V IOL = 50 µA High-level input current I IH — — 10 A V DD = 5.5 V, VI = VDD Low-level input current IIL — — –10 A V DD = 5.5 V, VI = VSS Off-state high-level output current I OZH — — 10 A V DD = 5.5 V, VO = VDD Off-state low-level output current D <15:0> I OZL — — –10 A V DD = 5.5 V, VO = VSS Operating supply current (Average) I DD (A) — — 40 mA V DD = 5.5 V, VI = VDD or VSS fosc = 10 MHz, Output = open Stand-by supply current I DD (S) — — 500 A V DD = 5.5 V, IOCS, MCS = VDD Other's VI = VDD or VSS (valid)

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 6 of 27 Switching Characteristics (VDD = 5 V ± 10%, Ta = 0 to +70°C, CL = 50 pF) Item Symbol Min Typ Max Unit IOCS data access time MCS data access time RD data access time ta (IOCS-D) ta (MCS-D) ta (RD-D) — — 70 ns Output disable time after IOCS Output disable time after MCS Output disable time after RD t dis (IOCS-D) tdis (MCS-D) tdis (RD-D) — — 20 ns WAIT output propagation time after MCS WAIT output propagation time after WR WAIT output propagation time after RD t pHL (MCS-WAIT) tpHL (WR-WAIT) tpHL (RD-WAIT) — — 40 ns WAIT output propagation time after MPUCLK t pLH (CLK-WAIT) — — 20 ns CP output propagation time after OSC t pd (OSC-CP) — — 40 ns LP output propagation time after OSC t pLH (OSC-LP) tpHL (OSC-LP) — — 40 ns UD access time t a (UD) — — 40 ns FLM output propagation time after OSC t pLH (OSC-FLM) tpHL (OSC-FLM) — — 40 ns M output propagation time after OSC t pd (OSC-M) — — 40 ns LCDENB output propagation time after OSC t pLH (OSC-LE) tpHL (OSC-LE) — — 40 ns Data definite time before canceling WAIT t pd (D-WAIT) 0 — — ns Timing Requirements (VDD = 5 V ± 10%, Ta = 0 to +70°C) (1) Accessing to Control Register Item Symbol Min Typ Max Unit IOCS pulse width LWR pulse width t W (IOCS) tW (LWR) 70 — — ns Data set up time before falling edge of IOCS Data set up time before falling edge of LWR t su (D-IOCS) tsu (D-LWR) 0 — — ns Data hold time after rising edge of IOCS Date hold time after rising edge of LWR th (IOCS-D) th (LWR-D) 15 — — ns Address set up time before falling edge of IOCS Address set up time before falling edge of LWR Address set up time before falling edge of RD t su (A-IOCS) tsu (A-LWR) tsu (A-RD) 15 — — ns Address hold time after rising edge of IOCS Address hold time after rising edge of LWR Address hold time after rising edge of RD th (IOCS-A) th (LWR-A) th (RD-A) 15 — — ns

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 7 of 27 (2) Accessing to VRAM Item Symbol Min Typ Max Unit MCS pulse width WR pulse width tW (MCS) tW (WR) 70 — — ns Data set up time before falling edge of MCS Data set up time before falling edge of WR t su (D-MCS) tsu (D-WR) 0 — — ns Data hold time after rising edge of MCS Data hold time after rising edge of WR th (MCS-D) th (WR-D) 15 — — ns Address set up time before falling edge of MCS Address set up time before falling edge of WR Address set up time before falling edge of RD t su (A-MCS) tsu (A-WR) tsu (A-RD) 15 — — ns Address hold time after rising edge of MCS Address hold time after rising edge of WR Address hold time after rising edge of RD th (MCS-A) th (WR-A) th (RD-A) 15 — — ns (3) Clock and Accessing to LCD Display Item Symbol Min Typ Max Unit MPUCLK cycle time t C (CLK) 50 — — ns MPUCLK "H" pulse width t WH (CLK) MPUCLK "L" pulse width t WL (CLK) — tC (CLK) 2 — ns OSC cycle time t C (OSC) 50 * — — ns OSC "H'' pulse width t WH (OSC) OSC "L" pulse width t WL (OSC) — tC (OSC) 2 — ns CP cycle time t C (CP) — tC (OSC) (1/n) — ns CP "H" pulse width t WH (CP) CP "L" pulse width t WL (CP) — tC (OSC) 2 • (1/n) — ns FLM pulse width t W (FLM) — 2 • tC (OSC) • LPW (1/n) — ns Note: Clock frequency of OSC1 input is less than fmax = 20 MHz. Limit of OSC clock for the internal operation is fmax = 10 MHz. When OSC1 is more than 10 MHz from external input, set OSC clock up to 10 MHz by using division of OSCC register. Division is set with rising edge of OSC1 input. 1/n = Division of OSC1 LPW = Setting value of LPW register Test Circuit Item SW1 SW2 tdis (LZ) Closed Open tdis (HZ) Open Closed ta (ZL) Closed Open ta (ZH) Open Closed P.G DUT Input V DD VDD VSS Outputs except for D <15:0> D <15:0> SW1 SW2 RL = 1 k RL = 1 k CL CL (1) Input pulse level: 0 to 3 V Input pulse rise/fall time: tr, tf = 3 ns Input decision voltage: 1.5 V Output decision voltage: V DD/2 (However, tdis (LZ) is 10% of output amplitude and tdis (HZ) is 90% of that for decision.) (2) Load capacity C L include float capacity of connection and input capacity of probe.

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 8 of 27 Outline M66271FP is graphic display only controller for displaying a dot matrix type LCD. This IC has a built-in display data memory (VRAM) which is equivalent to 320 × 240 dots LCD.

  • Control register When access the control register from MPU side, use IOCS, LWR, RD, A <4:0> and D <7:0>. Refer to table 1, when set control type inputs. Control registers are R1 to R8 for the normal mode function and R9 to R11 for the exclusive register for the LCD module built-in system.
  • VRAM When access VRAM from MPU side, use MCS, HWR, LWR, RD, BHE, A <13:0> and D <15:0>. And enable to correspond to both 8-bit and 16-bit MPU by using MPUSEL input. Refer to figure 1 and table 2 to 6 for a form of VRAM and input setting for 8/16-bit MPU.
  • Cycle steal system Cycle steal is interact method of transferring display data for LCD from VRAM and accessing VRAM from MPU on the basic cycle of OSC. Basic timing is two clocks of OSC, and assign first clock to the access from MPU to VRAM and second clock to the transfer of display data from VRAM to LCD. In accessing VRAM from MPU, output WAIT. Change WAIT to "L" at the timing of the falling edge of overlapping with MCS and (RD or LWR/HWR). And return to "H" at synchronizing with rising edge of MPUCLK after internal processing. Cycle steal system can transfer data with more efficient. This function access with the cycle steal method as taking WAIT for MPU during the display term with necessity for the display data transfer from built-in VRAM to LCD. On other side, don't output WAIT for keeping throughput of MPU during horizontal synchronous term with no necessity for the display data transfer from VRAM to LCD side. Refer to the following description of cycle steal.
  • Output to LCD side LCD display data UD <3:0> output synchronized with the rising edge of CP output per 4 bits. LP output synchronized with the falling edge of OSC when finish the transfer of display data for a line. Enable to adjust the fittest value of the frame frequency requested by the LCD PANEL side with adjusting pulse width by LPW register. FLM output, when finish the transfer of display data of 1st line. M output is the LCD alternating signal which is signal for driving LCD by alternating current. M-cycle enable to set variably by M-cycle variable register in line unit, and enable to utilize for preventing LCD from being inferior.

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 9 of 27 Difference in VRAM between 8-bit and 16-bit MPU A <13:0> A <13:1> DI <7:0> DO <7:0> CEC WEC CEC WEC A <13:1> DI <15:8> DO <15:8> CEC WEC VRAM 9600-byte DI <7:0> DO <7:0> A <13:0> MCS MCSMCS LWRLWR BHE RD HWR RD LWR RD D <7:0> A <0>A <0> D <7:0> D <15:8> D <7:0> DI <7:0> DO <7:0> D <15:8> VRAM 4800-byte (Lower byte) VRAM 4800-byte (Upper byte) VRAM 4800-byte (Lower byte) VRAM 4800-byte (Upper byte) CEC WEC A <13:1> A <0> DI <15:8> DO <15:8> CEC WEC (1) When accessing built-in VRAM by 8-bit MPU (MPUSEL = "L", BHE = "H", HWR = "H": set) (2) When accessing built-in VRAM by 16-bit MPU (2-1) In case MPU use A <0> and BHE for byte access (MPUSEL = "H", HWR = "H": set) (2-2) In case MPU use LWR and HWR for byte access (MPUSEL = "H", BHE = "H", A <0> = "H": set) Figure 1 Difference in VRAM between 8-bit and 16-bit MPU

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 10 of 27 Combination of Control Input Pins for MPU Interface Table 1 to 6 show conditions of input setting when access the control register and VRAM from MPU. (1) Access control register (Use address = A <4:0>, Data = D <7:0>) Table 1 IOCS LWR RD Operation L L H Write to control register L H L Read from control register H X X Invalid (2) Writing to VRAM (2-1) When use 8-bit MPU (MPUSEL = "L", BHE = HWR = "H": set) Table 2 MPU SEL MCS BHE A <0> HWR LWR Odd Address Even Address Valid Data Bus Width of MPU L Invalid Write H L Write Invalid 8-bit L X H L H H X H X Invalid Invalid (2-2) When use 16-bit MPU (In MPU controls byte access with A <0> and BHE, MPUSEL = HWR = "H": set) Table 3 MPU SEL MCS BHE A <0> HWR LWR Upper Byte Lower Byte Valid Data Bus Width of MPU L Write Write 16-bit L H Invalid Invalid L Write Invalid Upper 8-bit L H H Invalid Invalid L Invalid Write Lower 8-bit L H Invalid Invalid L Invalid Write Lower 8-bit L H H H H H X X H X Invalid Invalid ← Even if A <0> = "H", enable to write (2-3) When use 16-bit MPU (In MPU controls byte access with LWR and HWR, MPUSEL = BHE = A <0> = "H": set) Table 4 MPU SEL MCS BHE A <0> HWR LWR Upper Byte Lower Byte Valid Data Bus Width of MPU L Write Write 16-bit L H Write Invalid Upper 8-bit L Invalid Write Lower 8-bit L H H H H H H X X Invalid Invalid

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 11 of 27 (3) Reading from VRAM (3-1) When use 8-bit MPU (MPUSEL = "L", BHE = "H": set) Table 5 MPU SEL MCS BHE A <0> RD Odd Address Even Address Valid Data Bus Width of MPU L Invalid Read H L Read Invalid 8-bit L H L H H X X Invalid Invalid (3-2) When use 16-bit MPU (MPUSEL = ''H": set) Table 6 MPU SEL MCS BHE A <0> RD Upper Byte Lower Byte Valid Data Bus Width of MPU L Read Read 16-bit L H H H X X X Invalid Invalid Note: Avoid setting combination except above, as cause of error action. X = "L" or "H''

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 13 of 27 Function of Cycle Steal Control M66271FP has a function for processing data of a line with more efficient. This function access with the cycle steal method as taking WAIT for MPU during the display term with necessity for the display data transfer from built-in VRAM to LCD. On other side, don't output WAIT for keeping throughput of MPU during the horizontal synchronous term with no necessity for the display data transfer from VRAM to LCD side. But certainly set a term of accessing with the cycle steal method by CSW register, for controlling an error action near the end of horizontal synchronous term. Ex.) Assuming 320 × 240 dots LCD LP CP UD <3:0> CSE (Internal signal) Setting by CR register Displaying term (Cycle steal method) (Necessity for data transfer from VRAM to LCD side) Horizontal synchronous term (No necessity for data transfer from VRAM to LCD side) Setting by LPW register Start WAIT for MPU according to cycle steal access Access with bus timing of MPU without WAIT for MPU. Start WAIT for MPU in timing of CSE "H" according to bus timing of MPU 4-bit transfer Output every transfer of a display data Output when finish transfe r of display data with a line

1 Line

Figure 4 Function of Cycle Steal Control Handling of Oscillator Pin Crystal oscillator Rf C2 Rd OSC2 OSC1 Open OSC2 OSC1Clock generator Note: As far as possible, connect C, R and the crystal oscillator at near the pin. <1> Crystal oscillator <2> Input from external clock directly M66271FP M66271FP Figure 5 Oscillator Pin

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 14 of 27 Additional Function for LCD Module Built-in System As all of the VRAM address in M66271FP are externally opened for addressing VRAM from MPU directly. When consider the LCD module built-in system, connect pins are increased. But M66271FP has an additional function for the LCD module built-in system by lessening connect pins. Outline of the additional function for the LCD module built-in system.

  • Interface pins with MPU 15 kinds of interface with MPU: A <4:1>, D <7:0>, IOCS, LWR, RD
  • Method of accessing the internal VRAM Access the internal VRAM through the VRAM address index register (IDXL, IDXH) and the data port register (DP) which are used for I/O register. The following show the process of accessing VRAM. Setting to MPUSEL, BHE = "L" Select VRAM address index register (IDXL, IDXH), and write access address (14-bit) as data. Select Data port register (DP). Reading/Writing data for appointed VRAM address. VRAM address is increased of +1. No use pins set the following. HWR = "H", MCS = "H", WAIT = open, MPUCLK = "L", MPUSEL = "L", RESET = Power on reset or soft ware reset. (In case of soft ware reset RESET = "H": set) Enable to change IDXL and IDXH, even if either. Access the DP after writing the mode register (DISP (R1 − D2)) = "0". Always enable to access (CSES register = "0"), because the display signal fix "H" or "L" in DISP = "0" and a term is no wait access. Access DP without WAIT function. VRAM address is automatically increased of +1, when finished access to DP. When access to continuous address, it doesn't need to set IDXL and IDXH. Application MPU side A <4:1> D <7:0> IOCS LWR RD Crystal Oscillator LCD side Common driver Graphic LCD PANEL Segment driver Note: LCD module of small size for only graphics M66271FP

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 15 of 27 Control Register M66271FP has 9 kinds of control register. To set mode from MPU to control register, use IOCS, LWR, RD, A <4:0> and D <7:0>. (1) Kind of control register Control Register Table Kind of Register Address Data No. Name A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Functions of Register R/W R1 Mode register 0 0 0 0 0 CSES RESET ←– OSCC –→ DISP REV LCDE D6 to D0 set the basic mode. D7 is the status register of cycle steal state. R/W D7 = Only "R" R2 Horizontal display character number register Set the number of horizontal display characters per line. W R3 Horizontal synchronous pulse width register Set the pulse width of LP per line. W R4 Cycle steal enable width register Set the term of cycle steal enable access during horizontal synchronous term. W R5 Vertical line number register Set the number of display line of vertical direction. W Display start address register Set the display start address of VRAM. Set lower 8-bit to SAL and upper 6-bit to SAH. Max = 257F H R/W R8 M cycle variable register Set the cycle of LCD alternating signal from M. W R9 Data port Data port register for accessing VRAM through the register. R/W R10 R11 VRAM address index register Set the address for accessing VRAM. Set lower 8-bit to IDXL and upper 6-bit to IDXH. Max = 257F H And automatically increase in continuous address. R/W Note: Data port register (DP) and VRAM address index register (IDXL, IDXH) are exclusive register, when using this IC for the LCD module built-in system. When RESET, each register is initialize the setting which is assumed LCD size of 320 × 240 dots. Then, even if each register has not setting, output the signal to LCD side, it is possible to be alternation of LCD.

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 16 of 27 (2) Description of register (2-1) Mode register [R1] Address R/W Function Reset D7 CSES

0 No wait access

1 Cycle steal access

  • Status register for identifying active or inactive in cycle steal function.
  • Set "1" during active with cycle steal function.
  • CSES is for only reading, not for writing. D6 RESET

0 Reset OFF

1 Reset ON

  • Software reset.
  • Surely return to reset off after reset on. OSCC D5 D4 D3 Division of OSC1 0 0 0 1 0 0 1 1/2 Division 0 1 0 1/4 Division 0 1 1 1/8 Division 1 0 0 1/16 Division
  • Set the division of OSC clock for internal operation from OSC1 input pin.
  • When reset, OSCC = 000, OSC1 clock doesn't divide.
  • Don't set except left table. 000 D2 DISP

0 Display OFF

1 Display ON

  • Control the displaying ON/OFF of LCD.
  • When reset, DISP = 0, set display OFF.
  • REV (D1) set "1", and when DISP = "0" display data UD <3:0> output "1" in reversal mode. D1 REV

0 Normal display

1 Reversal display

  • Control normal/reversal of LCD display.
  • When reset, REV = 0, set normal display.
  • In using LCD of permeation method, REV = "1" has effect.

00000 R/W

D7 = Only "R" D0 LCDE

0 LCDENB = "0" output

1 LCDENB = "1" output

  • Set the output data from LCDENB output pin.
  • When reset, LCDE = 0, LCDENB output "0" (Vss potential).
  • This function is prepared for controlling the voltage of LCD. When the power supply is ON after finish each register setting, LCDE = "1", supply voltage of LCD. Conversely for setting power supply OFF, first LCDE = "0", the voltage of LCD is OFF. Therefore enable to prevent LCD from being unusual voltage as DC. This function use for satisfy the need of LCD.

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 17 of 27 (2-2) Horizontal display characters number register [R2] Address R/W Function Reset CR D7 D6 D5 D4 D3 D2 D1 D0 Character Number Display Dot Number 0 0 0 0 0 0 — — 0 0 0 0 0 1 1 8 0 0 0 0 1 0 2 16 ↓ ↓ ↓ 1 1 1 1 1 1 63 504 00010 W

  • The number of horizontal display characters per line can set to the extent of Max = 504 dots (= 63 characters)
  • When reset, CR = "28H" (= 40 characters = 320 dots) 28H Note: Definition of the number of display characters. The number of display characters means data which is corresponding with 1 byte of VRAM. In case of binary, 1 bit of VRAM corresponds to 1 dot of display, then 1 character means 8 dots of display. (2-3) Horizontal synchronous pulse width register [R3] Address R/W Function Reset 00100 W LPW D7 D6 D5 D4 D3 D2 D1 D0 Character Number 0 0 0 0 0 0 0 0 — 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 2 ↓ ↓ 1 1 1 1 1 1 1 1 255
  • Set the length of horizontal synchronous pulse width which appeared per line in character unit. Horizontal synchronous pulse output from LP output pin, and use for changing serial/parallel of displaying data. Adjusting this pulse width is possible to set frame frequency the fittest value. And the actual LP output pulse is (LPW setting value – 1CP) in consideration of timing with CP output.
  • When reset, LPW = "01H" (= 1 character) 01H

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 18 of 27 (2-4) Cycle steal enable width register [R4] Address R/W Function Reset 00110 W CSW D7 D6 D5 D4 D3 D2 D1 D0 Character Number 0 0 0 0 0 0 0 0 — 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 2 ↓ ↓ 1 1 1 1 1 1 1 1 255

  • During the horizontal synchronous term, set term of access by cycle steal method in character number unit. Setting value of CSW sets below LPW value.
  • When reset, CSW = "00H" Note: Be careful with first and second byte of display data UD <3:0> output indefinite data when setting value of CSW is still reset (00H). Surely CSW set over 01H. (When select 8-bit MPU, 1 byte is indefinite. When 16-bit and SAL: D <0> = 0, 2 byte are indefinite. When 16-bit and SAL: D <0> = 1, 1 byte is indefinite.) 00H (2-5) Vertical line number register [R5] Address R/W Function Reset 01000 W SLT D7 D6 D5 D4 D3 D2 D1 D0 Vertical Line Number 0 0 0 0 0 0 0 0 — 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 2 ↓ ↓ 1 1 1 1 1 1 1 1 255
  • SLT combine the setting of display driving duty of LCD.
  • Setting of SLT is sure to adjust to the number of display line of LCD.
  • When reset, SLT = "F0H" (= 240 lines). F0H

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 19 of 27 (2-6) Display start addr ess register [R6, R7] Address R/W Function Reset 01010 SAL 01100 SAH R/W SAH SAL D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Display Start Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 H 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0001 H 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0002 H ↓ ↓ ↓ 1 0 0 1 0 1 0 1 1 1 1 1 1 1 257F H

  • D6 and D7 output "0" when read SAH.
  • It is possible to set display start address to the extent of 257FH (= 9600 address).
  • Don't set over 2580H.
  • When reset, SAL and SAH = "0000H"
  • Display start address is established by the writing data to SAH register. Even if only change SAL, surely set SAH after SAL.
  • When select 8-bit MPU, start address set in SAL <D7 to D0> + SAH <D5 to D0>. When select 16-bit MPU, start address set in SAL <D7 to D1>+ SAH <D5 to D0>.
  • Even it selecting 16-bit MPU, enable to set display start address in character unit. In case the display reading data from VRAM start at D <15:12>, set SAL <D0> = "0", and if start at D <7:4>, set SAL <D0> = "1". (Refer to figure 8) 0000H (2-7) M cycle variable register [R8] Address R/W Function Reset 01110 W MT D7 D6 D5 D4 D3 D2 D1 D0 Cycle of M 0 0 0 0 0 0 0 0 Toggle change at every 1 frame. 0 0 0 0 0 0 0 1 Toggle change at every 1 line (1LP). 0 0 0 0 0 0 1 0 Toggle change at every 2 lines. ↓ ↓ 1 1 1 1 1 1 1 1 Toggle change at every 255 lines.
  • Set the cycle of M. In case of MT = 01H, M repeat reversal (toggle) at every 1 line (at every 1 count of LP).
  • When reset, MT = "00H", toggle M signal at every 1 frame.
  • We recommend this register set suitable value for user's LCD. 00H (2-8) Data port register [R9] Address R/W Function Reset

10000 R/W

D7 D6 D5 D4 D3 D2 D1 D0 Data Port (8-bit)

  • Exclusive data port register for the LCD module built-in system. Reading or writing 8-bit data between MPU and VRAM through this register.
  • VRAM address index register (IDXL, IDXH) is increased of +1, when finished access to DP.
  • Output indefinite data when reset. XXH (indefinite)

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 20 of 27 (2-9) VRAM address index register [R10, R11] Address R/W Function Reset 10010 IDXL 10100 IDXH R/W IDXH IDXL D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Accessing VRAM Address 00 0 0 0000000000 0000H 00 0 0 0000000001 0001H 00 0 0 0000000010 0002H ↓ ↓ ↓ 10 0 1 0101111111 257FH

  • Exclusive VRAM address index register for the LCD module built-in system.
  • It is possible to change the register only one side, because IDXH and IDXL are independent each other.
  • It is possible to set VRAM access address to the extent of 257FH (= 9600 address).
  • Don't set address over 2580H.
  • D6 and D7 output "0" when read IDXH
  • When reset, IDXL and IDXH = "0000H". 0000H Description of LCD Display Relation between Setting of Control Register and LCD Displaying 1 horizontal line LPWCR CR CSW SLT OSC Character number of horizontal display

1 Character number = 8 dots display

12 3 n − 2 n − 1 n Horizontal synchronous pulse width LPW Data is indefinite × Vertical line number SLT Condition of control register (CR × 8) × SLT ≤ 76800 dots CP UD <3:0> LP 1 2 1 horizontal line (1) Time for processing a horizontal line (TH) (2) Time for processing a frame (TFR) TH = fosc 2 × (CR + LPW) TFR = TH × SLT CR, LPW, CSW: Unit of character number SLT: Unit of line number fosc: Internal OSC clock frequency after dividing OSC1 input By adjusting LPW, it is possible to set a frame frequency which is requested from LCD PANEL the fittest value. Expectant LCD PANEL Figure 6 Relation between Setting of Control Register and LCD Displaying

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 22 of 27 Output Signal of LCD Side LCDENB LCDENB OSC1 OSC1 OSC1 OSC1 (3) LCDENB output signal (2) Output signal per frame (1) Output signal per line LP LP LP LP FLM FLM FLM FLM M M M M LP CP CP CP CP OSC1 UD <3:0> 239 240 1 239 240 1 1 2 79 80 1 280 (6) 240th line of 1st frame-1st line of 2nd frame (5) 1st line-2nd line (4) Reset-1st line of 1st frame RESET 76 77 78 79 80 76 77 78 79 80 123 4 5 67 8 1 2345 6 12345 6 Division of OSC1 = 1 Output every display data transfer 4-bit parallel output Output when finish the transfer of one line of display data. Output at finishing the transfer of first line display data. Cycle of reversing output of M is able to be set by MT register. "L" "L" 1st line of 1st frame 2nd line1st line 240th line of 1st frame 1st line of 2nd frame Ex.) Assuming 320 × 240 dots LCD (In setting of CR = 40 characters, LPW = 2 characters, SLT = 240 lines, OSCC = 1 division, MT = 1 toggle per line)

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 23 of 27 Timing Diagram (1) Write to Control Register (RD = "H") IOCS LWR WAIT D <7:0> A <4:0> Address is established th (LWR-A) tw (LWR) th (IOCS-A) tw (IOCS) th (IOCS-D) "H" tsu (D-IOCS) tsu (A-IOCS) tsu (A-LWR) Without WAIT tsu (D-LWR) th (LWR-D) Data input is established (2) Read from Control Register (LWR = "H") IOCS RD WAIT D <7:0> A <4:0> Address is established th (RD-A) th (IOCS-A) tdis (IOCS-D) "H" ta (IOCS-D) tsu (A-IOCS) ta (RD-D) tsu (A-RD) Without WAIT tdis (RD-D) Data output is established Note: 1. Writing/Reading operation for the control register is performed during overlapping IOCS and (LWR or RD). Limits of IOCS, LWR and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first change to "H" in ending access.

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 24 of 27 (3) Write to VRAM (RD = "H") MCS LWR (+HWR) WAIT D <7:0> (D <15:0>) A <13:0> (+BHE) Address is established th (WR-A) tw (WR) th (MCS-A) tw (MCS) th (MCS-D) "H" tsu (D-MCS) tsu (A-MCS) tsu (A-WR) Term of non cycle steal access tsu (D-WR) th (WR-D) Data input is established (4) Read from VRAM (LWR, HWR = "H") MCS RD WAIT D <7:0> (D <15:0>) A <13:0> Address is established th (RD-A) th (MCS-A) tdis (MCS-D) "H" ta (MCS-D) tsu (A-MCS) ta (RD-D) tsu (A-RD) Term of non cycle steal access tdis (RD-D) Data output is established Note: 2. Writing/Reading operation for VRAM during non cycle steal access is performed during overlapping MCS and [LWR (+HWR) or RD]. Limits of MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first change to "H" in ending access.

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 25 of 27 (5) Write to VRAM (RD = "H") MCS LWR (+HWR) WAIT D <7:0> (D <15:0>) A <13:0> (+BHE) Address is established th (WR-A) tpHL (WR-WAIT) th (MCS-A) th (MCS-D)tsu (D-MCS) tsu (A-MCS) tsu (A-WR) MPUCLK tC (CLK) tw (MCS) tw (WR) tpLH (CLK-WAIT) Term of cycle steal access tWH (CLK) tWL (CLK) tpHL (MCS-WAIT) tsu (D-WR) th (WR-D) Data input is established (6) Read from VRAM (LWR, HWR = "H") MCS RD WAIT D <7:0> (D <15:0>) A <13:0> Address is established th (RD-A) tpd (D-WAIT) th (MCS-A) tpHL (RD-WAIT) tdis (MCS-D) tsu (A-MCS) ta (MCS-D) ta (RD-D) tsu (A-RD) MPUCLK tC (CLK) tpLH (CLK-WAIT) Term of cycle steal access tWH (CLK) tWL (CLK) tpHL (MCS-WAIT) tdis (RD-D) Data output is established Notes: 3. Reading/writing operation for VRAM during cycle steal needs 1 tc (Internal) in best case or 3 tc (Internal) in worst case, according to the condition of the internal cycle steal at starting access requested from MPU. tc (Internal) = Clock cycle time after setting division of OSC1. Data output D in reading is established before changing WAIT to "H". 4. Limits of MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first change to "H" in ending access. 5. Always once return MCS, LWR (+HWR) or RD to "H" after canceling WAIT output. In case of latching "L", as don't output next WAIT, this is cause of error action.

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 26 of 27 (7) Interface Timing with LCD (OSCC = 1 division: set) (When OSCC = 1 division, OSC clock for internal operation = OSC1 input.) 1. Transfer of LCD display data OSC1 CP LP UD <3:0> tC (OSC) tWL (OSC)tWH (OSC) tpHL (OSC-LP)tpLH (OSC-LP) Data is indefinite tpd (OSC-CP) tWH (CP) tC (CP) ta (UD) tWL (CP) 2. LCD control signal OSC1 CP LP FLM M LCDENB tW (FLM) tpLH (OSC-FLM) tpHL (OSC-LE)tpLH (OSC-LE) tpd (OSC-M) tpHL (OSC-FLM) Note: 6. Output signal to LCD side is synchronized with OSC clock for internal operation. When division is set to 1/2 to 1/16 by OSCC register, switching characteristics is defined by rising edge of OSC1.

REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 27 of 27 Package Dimensions y F 1 24 4164 Index mark c bp D E HE A e ZD ZE HD Detail F L A1 A2 INCLUDE TRIM OFFSET. DIMENSION "*3" DOES NOT NOTE) DO NOT INCLUDE MOLD FLASH. Previous CodeJEITA Package Code RENESAS Code PRQP0080GB-A 80P6N-A MASS[Typ.] 1.6gP-QFP80-14x20-0.80 0.20.150.13 0.450.350.3 MaxNomMin Dimension in Millimeters Symbol Reference 20.220.019.8D 14.214.013.8E 2.8A2 23.122.822.5 17.116.816.5 3.05A 0.20.10 0.80.60.4L 10°0° c 0.8e 0.10y HD HE bp ZD ZE 0.65 0.95 0.8 1.0

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