M66258FP RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 14
Technical content
Features
- Memory configuration: 8192 words × 8 bits configuration
- High speed cycle: 20 ns (Min)
- High speed access: 16 ns (Max)
- Output hold: 3 ns (Min)
- Reading and writing operations can be completely carried out independently and asynchronously
- Variable length delay bit
- Input/output: TTL direct connection allowable
- Output: 3 states Application Digital copying machine, laser beam printer, high speed facsimile, etc. Block Diagram 718 Read address counter Write address counter Read control circuit Write control circuit Input buffer Memory array 8192 × 8 bits 13 14 15 16 21 22 2423 1 2 3 4 9 10 11 12 RE RRES RCK Read enable input Read reset input Read clock input Write enable input Data inputs D0 to D7 Data outputs Q0 to Q7 Write reset input Write clock input GND WE WRES WCK VCC Output buffer
REJ03F0252-0200 Rev.2.00 Sep 14, 2007 Page 2 of 13 Pin Arrangement WE WRES V CC WCK RE RRES GND RCK Data inputData output Data output Data input M66258FP (Top view) Outline: 24P2U-A Write enable input Write reset input Write clock input Read enable input Read reset input Read clock input
REJ03F0252-0200 Rev.2.00 Sep 14, 2007 Page 3 of 13 Absolute Maximum Ratings (Ta = 0 to 70°C, unless otherwise noted) Item Symbol Ratings Unit Conditions Supply voltage V CC −0.5 to +6.0 V Input voltage V I −0.5 to VCC + 0.5 V Output voltage V O −0.5 to VCC + 0.5 V Value based on the GND pin Power dissipation Pd 825 mW Ta = 25 °C Storage temperature Tstg −65 to 150 °C Recommended Operating Conditions Item Symbol Min Typ Max Unit Supply voltage V CC 4.5 5.0 5.5 V Supply voltage GND 0 V Operating temperature Topr 0 to 70 °C
Electrical Characteristics
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted) Item Symbol Min Typ Max Unit Test Conditions High-level input voltage V IH 2.0 V Low-level input voltage V IL 0.8 V High-level output voltage V OH V CC − 0.8 V I OH = −4 mA Low-level output voltage V OL 0.55 V I OL = 4 mA High-level input current I IH 1.0 µA V I = VCC WE, WRES, WCK, RE, RRES, RCK, D0 to D7 Low-level input current I IL −1.0 µA V I = GND WE, WRES, WCK, RE, RRES, RCK, D0 to D7 Off-state high-level output current I OZH 5.0 µA V O = VCC Off-state low-level output current I OZL −5.0 µA V O = GND Average supply current during operation I CC 150 mA V I = VCC, GND, Output open tWCK, tRCK = 20 ns Input capacitance C I 10 pF f = 1 MHz Off-time output capacitance C O 15 pF f = 1 MHz Function When write enable input WE is set to "L", the contents of data inputs D0 to D7 are read in synchronization with a rising edge of write clock input WCK to perform writing operation. When this is the case, the write address counter is also incremented simultaneously. When WE is set to "H", the writing operation is inhibited and the write address counter stops. When write reset input WRES is set to "L", the write address counter is initialized. When read enable input RE is set to "L", the contents of memory are output to data outputs Q0 to Q7 in synchronization with a rising edge of read clock input RCK to perform reading operation. When this is the case, the read address counter is incremented simultaneously. When RE is set to "H", the reading operation is inhibited and the read address counter stops. The outputs are placed in a high impedance state. When read reset input RRES is set to "L", the read address counter is initialized.
REJ03F0252-0200 Rev.2.00 Sep 14, 2007 Page 4 of 13 Switching Characteristics (Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted) Item Symbol Min Typ Max Unit Access time t AC 16 ns Output hold time t OH 3 ns Output enable time t OEN 3 16 ns Output disable time t ODIS 3 16 ns Timing Requirements (Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted) Item Symbol Min Typ Max Unit Write clock (WCK) cycle t WCK 20 ns Write clock (WCK) "H" pulse width t WCKH 8 ns Write clock (WCK) "L" pulse width t WCKL 8 ns Read clock (RCK) cycle t RCK 20 ns Read clock (RCK) "H" pulse width t RCKH 8 ns Read clock (RCK) "L" pulse width t RCKL 8 ns Input data setup time for WCK t DS 4 ns Input data hold time for WCK t DH 3 ns Reset setup time for WCK/RCK t RESS 4 ns Reset hold time for WCK/RCK t RESH 3 ns Reset non-selection setup time for WCK/RCK t NRESS 4 ns Reset non-selection hold time for WCK/RCK t NRESH 3 ns WE setup time for WCK t WES 4 ns WE hold time for WCK t WEH 3 ns WE non-selection setup time for WCK t NWES 4 ns WE non-selection hold time for WCK t NWEH 3 ns RE setup time for RCK t RES 4 ns RE hold time for RCK t REH 3 ns RE non-selection setup time for RCK t NRES 4 ns RE non-selection hold time for RCK t NREH 3 ns Input pulse up/down time tr, tf 20 ns Data hold time* tH 20 ms Notes: Perform reset operation after turning on power supply. * For 1 line access, the following conditions must be satisfied: WE high-level period ≤ 20 ms − 8192 • tWCK − WRES low-level period RE high-level period ≤ 20 ms − 8192 • tRCK − RRES low-level period
REJ03F0252-0200 Rev.2.00 Sep 14, 2007 Page 5 of 13 Switching Characteristics Measurement Circuit CL = 30 pF: tAC, tOH Qn CL = 5 pF: tOEN, tODIS SW1 SW2 RL = 1 kΩ RL = 1 kΩ VCC Qn Input pulse level: 0 to 3 V Input pulse up/down time: 3 ns Judging voltage Input: 1.3 V Output: 1.3 V (However, t ODIS (LZ) is judged with 10% of the output amplitude, while tODIS (HZ) is judged with 90% of the output amplitude) Load capacitance C L includes the floating capacity of connected lines and input capacitance of probe. Item SW1 SW2 tODIS (LZ) Close Open tODIS (HZ) Open Close tOEN (ZL) Close Open tOEN (ZH) Open Close tODIS and tOEN Measurement Condition RCK RE Qn Qn VOL VOH GND 3 V GND 3 V 1.3 V 1.3 V 1.3 V tOEN (ZH) tOEN (ZL) 1.3 V 90% 10% tODIS (HZ) tODIS (LZ)
REJ03F0252-0200 Rev.2.00 Sep 14, 2007 Page 6 of 13 Operation Timing Write Cycle WCK WE Dn tWCK n cycle n + 1 cycle n + 2 cycle WRES = "H" (n + 4) n + 3 cycle n + 4 cycle Disable cycle tWCKH tWEH tNWES tNWEH tWEStWCKL tDS tDH Write Reset Cycle WCK WRES Dn tWCK n − 1 cycle n cycle (n) (0) (1) WE = "L" (2) 1 cycle0 cycle 2 cycleReset cycle tNRESH tRESH tNRESStRESS tDS tDH (n − 1)
REJ03F0252-0200 Rev.2.00 Sep 14, 2007 Page 7 of 13 Matters that Needs Attention when WCK Stops WCK WE Dn tWCK Period for writing data (n) into memory Period for writing data (n) into memory tNWES n cycle n cycle Disable cyclen + 1 cycle (n) (n) WRES = "H" tDS tDH tDS tDH Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of n + 1 cycle. The writing operation is complete at the falling edge after n + 1 cycle. To stop reading write data at n cycle, enter WCK before the rising edge after n + 1 cycle. When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
REJ03F0252-0200 Rev.2.00 Sep 14, 2007 Page 8 of 13 Read Cycle RCK RE Qn tRCK n cycle n + 1 cycle n + 2 cycle RRES = "H" (n + 4) n + 3 cycle n + 4 cycleDisable cycle HIGH-Z tRCKH tREH tNRES tNREH tRES tAC tRCKL tODIS tOEN tOH Read Reset Cycle RCK RRES Qn tRCK n − 1 cycle n cycle RE = "L" (2) 1 cycle0 cycle 2 cycleReset cycle tNRESH tRESH tNRESS tAC tOH tRESS
REJ03F0252-0200 Rev.2.00 Sep 14, 2007 Page 9 of 13 Variable Length Delay Bit
1 Line (8192 Bits) Delay
Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK before read cycle to easily make 1 line delay. WCK RCK Dn Qn WRES RRES WE, RE = "L" tRESHtRESS tDHtDS tDH tOHtAC8192 cycle tDS 1 cycle0 cycle 8190 cycle 8191 cycle 8192 cycle (0') 8193 cycle (1') 8194 cycle (2')2 cycle (0) (1) (2) (3) n-bit Delay Bit (Reset at cycles according to the delay length) WCK RCK Dn Qn WRES RRES WE, RE = "L" m ≥ 3 tRESHtRESS tDHtDS tDH tOHtACm cycle tDS tRESHtRESS 1 cycle 0 cycle n − 2 cycle n − 1 cycle n cycle (0') n + 1 cycle (1') n + 2 cycle (2') n + 3 cycle (3')2 cycle (0) (1) (2) (3)
REJ03F0252-0200 Rev.2.00 Sep 14, 2007 Page 10 of 13 n-bit Delay 2 (Slides input timings of WRES and RRES at cycles according to the delay length) WCK RCK Dn Qn WRES WE, RE = "L" tRESHtRESS tDHtDS tDH tOHtACm cycle tDS 1 cycle0 cycle n − 1 cycle n cycle n + 1 cycle n + 2 cycle n + 3 cycle2 cycle n − 2 cycle (0) (1) (2) (3) RRES tRESHtRESS n-bit Delay 3 (Slides address by disabling RE in the period according to the delay length) WCK RCK Dn Qn WRES RRES WE, RE = "L" m ≥ 3 tRESHtRESS tDHtDS tDH tOHtACm cycle HIGH-Z tDS 1 cycle0 cycle n − 1 cycle n cycle n + 1 cycle n + 2 cycle n + 3 cycle2 cycle (0) (1) (2) (3) RE tREStNREH
REJ03F0252-0200 Rev.2.00 Sep 14, 2007 Page 11 of 13 Reading Shortest n-cycle Write Data "n" (Reading side n − 1 cycle starts after the end of writing side n − 1 cycle) When the reading side n − 1 cycle starts before the end of the writing side n + 1 cycle, output Qn of n cycle is made invalid. In the following diagram, reading operation of n − 1 cycle is invalid. (n) (n +2) (n +3) n cycle n + 1 cycle n − 2 cycle n − 1 cycle n cycle (n)Invalid n + 2 cycle n + 3 cycle WCK Dn Qn RCK (n +1) Reading Longest n-cycle Write Data "n": 1 Line Delay (When writing side n-cycle <2>* starts, reading side n cycle <1>* then starts) Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each other. n cycle <1>* WCK Dn Qn RCK n cycle <0>* 0 cycle <2>* 0 cycle <1>* n cycle <2>* n cycle <1>* Note: <0>*, <1>* and <2>* indicate value of lines.
REJ03F0252-0200 Rev.2.00 Sep 14, 2007 Page 12 of 13 Application Example Sub Scan Resolution Compensation Circuit with Laplacian Filter M66258 × 2 Compensated image data Main scan direction (n − 1) line K: Laplacian coefficient A X B n line (n + 1) line × K 1 line delay to to M66258 A (n + 1) line image data B (n + 1) line image data Adder A + B Subtractor 2N − (A + B) Adder N n line image data 1 line delay to to Sub scan direction
REJ03F0252-0200 Rev.2.00 Sep 14, 2007 Page 13 of 13 Package Dimensions SSOP24-P-375-0.80 — JEDEC Code 0.4 24P2U-A Plastic 24pin 375mil SSOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters HE 0.3 0.1 0.23 10.2 7.4 10.0 0.5 1.27 0.2 .32 0.35 0.25 10.3 7.5 0.8 10.3 0.7 1.4 9.53 0.3 2.65 0.45 0.3 10.4 7.6 10.6 0.9 0.1 b 2 0.5 0° 8° e 24 13 121 HE E D e y F A A2 A1 L c e b2 Recommended Mount Pad Detail F z Z1 Detail G 0.75 0.9 z b G Cu Alloy
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