M66257FP RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 13
Technical content
Features
- Memory configuration: 5120 words × 8 bits × 2 (dynamic memory)
- High-speed cycle: 25 ns (Min)
- High-speed access: 18 ns (Max)
- Output hold: 3 ns (Min)
- Fully independent, asynchronous write and read operations
- Output: 3 states
- Q00 to Q07: 1-line delay
- Q10 to Q17: 2-line delay Application Digital photocopiers, high-speed facsimile, laser beam printers. Block Diagram Read address counter Write address counter Read control circuit Write control circuit Input buffer 27 26 25 24 23 22 2021 10 11 12 13 14 15 16 17 RE RRES RCK Read enable input Read reset input Read clock input Write enable input Data input D0 to D7 Data output Q00 to Q07 Write reset input Write clock input GND GND GND WE WRES WCK V CC VCC VCC Data output Q10 to Q17 Memory array of 5120-word × 8-bit × 2 configuration 1-line delay data only memory/ 2-line delay data only memory( ) 2 3 4 5 6 7 8 9 Output buffer
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 2 of 12 Pin Arrangement VCC RE RRES RCK WE WRES WCK GND V CC GND GND Q00 Q01 Q02 Q03 Q04 Q05 Q06 Q07 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 VCC Data output Data input M66257FP (Top view) Outline: PRSP0036GA-A (36P2R-A) Read enable input Read reset input Read clock input Write enable input Write reset input Write clock input
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 3 of 12 Absolute Maximum Ratings (Ta = 0 to 70°C, unless otherwise noted) Item Symbol Ratings Unit Conditions Supply voltage V CC −0.5 to +7.0 V Input voltage V I −0.5 to VCC + 0.5 V Output voltage V O −0.5 to VCC + 0.5 V A value based on GND pin Power dissipation Pd 660 mW Ta = 25 °C Storage temperature Tstg −65 to 150 °C Recommended Operating Conditions Item Symbol Min Typ Max Unit Supply voltage V CC 4.5 5 5.5 V Supply voltage GND 0 V Operating ambient temperature Topr 0 70 °C
Electrical Characteristics
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted) Item Symbol Min Typ Max Unit Test Conditions "H" input voltage V IH 2.0 V "L" input voltage V IL 0.8 V "H" output voltage V OH V CC − 0.8 V I OH = −4 mA "L" output voltage V OL 0.55 V I OL = 4 mA "H" input current I IH 1.0 µA V I = VCC WE, WRES, WCK, RE, RRES, RCK, D0 to D7 "L" input current I IL −1.0 µA V I = GND WE, WRES, WCK, RE, RRES, RCK, D0 to D7 Off state "H" output current I OZH 5.0 µA V O = VCC Off state "L" output current I OZL −5.0 µA V O = GND Operating mean current dissipation I CC 120 mA V I = VCC, GND, Output open tWCK, tRCK = 25 ns Input capacitance C I 10 pF f = 1 MHz Off state output capacitance C O 15 pF f = 1 MHz
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 4 of 12 Function When write enable input WE is "L", the contents of data inputs D0 to D7 are written into 1-line delay data only memory in synchronization with rise edge of write clock input WCK. At this time, the write address counter of 1-line delay data only memory is also incremented simultaneously. The write functions given below are also performed in synchronization with rise edge of WCK. When WE is "H", a write operation to 1-line delay data only memory is inhibited and the write address counter of 1-line delay data only memory is stopped. When write reset input WRES is "L", the write address counter of 1-line delay data only memory is initialized. When read enable input RE is "L", the contents of 1-line delay data only memory are output to data outputs Q 00 to Q07 and those of 2-line delay data only memory to data outputs Q10 to Q17 in synchronization with the rise of read clock input RCK. At this time, the read address counters of 1-line and 2-line delay data only memories is also incremented simultaneously. Moreover, data of Q 00 to Q07 are written into 2-line delay data only memory in synchronization with rise edge of RCK. At this time, the write address of 2-line delay data only memory is incremented. The read functions given below are also performed in synchronization with rise edge of RCK. When RE is "H", a read operation from both of 1-line delay data only memory and 2-line delay data only memory is inhibited and the read address counter of each memory is stopped. The outputs of Q 00 to Q07 and Q10 to Q17 are in the high impedance state. Moreover, a write operation to 2-line delay data only memory is inhibited and the write address counter of 2-line delay data only memory is stopped. When read reset input RRES is "L", the read address counter of 1-line delay data only memory, and the write address counter and read address counter of 2-line delay data only memory are initialized.
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 5 of 12 Switching Characteristics (Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted) Item Symbol Min Typ Max Unit Access time t AC 18 ns Output hold time t OH 3 ns Output enable time t OEN 3 18 ns Output disable time t ODIS 3 18 ns Timing Conditions (Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted) Item Symbol Min Typ Max Unit Write clock (WCK) cycle t WCK 25 ns Write clock (WCK) "H" pulse width t WCKH 11 ns Write clock (WCK) "L" pulse width t WCKL 11 ns Read clock (RCK) cycle t RCK 25 ns Read clock (RCK) "H" pulse width t RCKH 11 ns Read clock (RCK) "L" pulse width t RCKL 11 ns Input data setup time to WCK t DS 7 ns Input data hold time to WCK t DH 3 ns Reset setup time to WCK or RCK t RESS 7 ns Reset hold time to WCK or RCK t RESH 3 ns Reset nonselect setup time to WCK or RCK t NRESS 7 ns Reset nonselect hold time to WCK or RCK t NRESH 3 ns WE setup time to WCK t WES 7 ns WE hold time to WCK t WEH 3 ns WE nonselect setup time to WCK t NWES 7 ns WE nonselect hold time to WCK t NWEH 3 ns RE setup time to RCK t RES 7 ns RE hold time to RCK t REH 3 ns RE nonselect setup time to RCK t NRES 7 ns RE nonselect hold time to RCK t NREH 3 ns Input pulse rise/fall time tr, tf 20 ns Data hold time* t H 20 ms Notes: Reset the IC after power is turned on. * For 1-line access, the following should be satisfied: WE "H" level period < 20 ms − 5120 tWCK − WRES "L" level period RE "H" level period < 20 ms − 5120 tRCK − RRES "L" level period
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 6 of 12 Test Circuit CL = 30 pF: tAC, tOH Qn CL = 5 pF: tOEN, tODIS SW1 SW2 RL = 1 kΩ RL = 1 kΩ VCC Qn Input pulse level: 0 to 3 V Input pulse rise/fall time: 3 ns Decision voltage input: 1.3 V Decision voltage output: 1.3 V (However, t ODIS (LZ) is 10% of output amplitude and tODIS (HZ) is 90% of that for decision) The load capacitance C L includes the floating capacitance of connection and the input capacitance of probe. Parameter SW1 SW2 tODIS (LZ) Closed Open tODIS (HZ) Open Closed tOEN (ZL) Closed Open tOEN (ZH) Open Closed tODIS/tOEN Test Condition RCK RE Q0n Q1n Q0n Q1n VOL VOH GND 3 V GND 3 V 1.3 V 1.3 V 1.3 V 1.3 V 90% 10% tOEN (ZH) tOEN (ZL) tODIS (HZ) tODIS (LZ)
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 7 of 12 Operating Timing Write Cycle WCK WE Dn tDS tWCK Cycle n Cycle n + 1 Cycle n + 2 WRES = "H" (n + 4) Cycle n + 3 Cycle n + 4Disable cycle tWCKH tWEH tNWES tNWEH tWEStWCKL tDH tDS tDH Write Reset Cycle WCK WRES Dn tDS tWCK Cycle n − 1 Cycle n WE = "L" (2) Cycle 1Cycle 0 Cycle 2Reset cycle tNRESH tRESH tNRESStRESS tDH tDS tDH
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 8 of 12 Read Cycle RCK RE Q0n Q1n tRCK Cycle n Cycle n + 1 Cycle n + 2 RRES = "H" (n + 4) Cycle n + 3 Cycle n + 4Disable cycle HIGH-Z tRCKH tREH tNRES tNREH tRES tAC tRCKL tODIS tOEN tOH Read Reset Cycle RCK RRES Q0n Q1n tRCK Cycle n − 1 Cycle n RE = "L" (2) Cycle 1Cycle 0 Cycle 2Reset cycle tNRESH tRESH tNRESS tAC tON tRESS tONtON
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 9 of 12 Note at WCK Stop WCK WE Dn tWCK Period of writing data (n) into memory Period of writing data (n) into memory tNWES n cycle n cycle Disable cyclen + 1 cycle (n) (n) WRES = "H" tDS tDH tDS tDH Input data Dn of n cycle is read at the rising edge after WCK of n cycle. Writing operation starts in the "L" period of WCK of n + 1 cycle and ends at the rising edge after n + 1 cycle. To stop reading write data at n cycle, input WCK for up to the rising edge of n + 1 cycle. When the cycle next to n cycle is a disable cycle, input of WCK for a cycle is required after a disable cycle as well.
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 10 of 12 Shortest Read of Data "n" Written in Cycle n (Cycle n − 1 on read side should be started after end of cycle n + 1 on write side) When the start of cycle n − 1 on read side is earlier than the end of cycle n + 1 on write side, output Qn of cycle n becomes invalid. In the figure shown below, the read of cycle n − 1 is invalid. Cycle n Cycle n + 1 Cycle n − 2 Cycle n − 1 Cycle n (n)Invalid Cycle n + 2 Cycle n + 3 WCK Dn Qn RCK Longest Read of Data "n" Written in Cycle n: 1-line Delay (Cycle n <1>* on read side should be started when cycle n <2>* on write is started) Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each other. Cycle n <1>* (n) <1>* (n) <0>* (n) <2>* (n − 1) <1>* (n − 1) <0>* (n − 1) <2>* (n − 1) <1>* WCK Dn Qn RCK Cycle n <0>* Cycle 0 <2>* Cycle 0 <1>* Cycle n <2>* Cycle n <1>* (0) <2>* Note: <0>*, <1>* and <2>* indicates a line value.
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 11 of 12 Application Example Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction M66257 × 2 Corrected image data Primary scanning direction Line (n − 1) K: Laplacian coefficient A N B Line n Line (n + 1) × K 1-line delay 2-line delay to Q00 to Q07 Q10 to Q17 A Line (n − 1) image data B Line (n + 1) image data Adder A + B Subtractor 2N − (A + B) Adder N Line n image data Secondary scanning direction
REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page 12 of 12 Package Dimensions y Index mark1 18 1936 F E HE D e bp A c Detail F L INCLUDE TRIM OFFSET. DIMENSION "*3" DOES NOT NOTE) DO NOT INCLUDE MOLD FLASH. Previous CodeJEITA Package Code RENESAS Code PRSP0036GA-A 36P2R-A MASS[Typ.] 0.5gP-SSOP36-8.4x15-0.80 0.20.150.13 0.50.40.35 MaxNomMin Dimension in Millimeters Symbol Reference 15.215.014.8D 8.68.48.2E 2.0A2 12.2311.9311.63 2.4A 0.05 0.70.50.3L 10°0° c 0.8e 0.15y HE bp 0.65 0.95
Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 RENESAS SALES OFFICES © 2007. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .7.0