M66255FP RENESAS | Alldatasheet
Document overview
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- PDF pages: 14
Technical content
Features
- Memory configuration: 8192 words × 10 bits (dynamic memory)
- High-speed cycle: 30 ns (Min)
- High-speed access: 25 ns (Max)
- Output hold: 5 ns (Min)
- Fully independent, asynchronous write and read operations
- Variable length delay bit
- Output: 3 states Application Digital photocopiers, high-speed facsimile, laser beam printers. Block Diagram 821 15 16 17 18 19 24 2625 27 28 1 2 3 4 5 10 11 12 13 14 RE RRES RCK Read enable input Read reset input Read clock input Write enable input Data input D0 to D9 Data output Q0 to Q9 Write reset input Write clock input GND WE WRES WCK VCC Output buffer Read address counter Write address counter Read control circuit Write control circuit Input buffer Memory array of 8192-word × 10-bit configuration
REJ03F0249-0200 Rev.2.00 Sep 14, 2007 Page 2 of 13 Pin Arrangement WE WRES VCC WCK RE RRES GND RCK Data inputData output Data output Data input M66255FP (Top view) Outline: PRSP0028DB-B (28P2W-C) Write enable input Write reset input Write clock input Read enable input Read reset input Read clock input
REJ03F0249-0200 Rev.2.00 Sep 14, 2007 Page 3 of 13 Absolute Maximum Ratings (Ta = 0 to 70°C, unless otherwise noted) Item Symbol Ratings Unit Conditions Supply voltage V CC −0.5 to +7.0 V Input voltage V I −0.5 to VCC + 0.5 V Output voltage V O −0.5 to VCC + 0.5 V A value based on GND pin Power dissipation Pd 825 * mW Ta = 25 °C Storage temperature Tstg −65 to 150 °C Note: * Ta ≥ 40°C are derated at −9.7 mW / °C Recommended Operating Conditions Item Symbol Min Typ Max Unit Supply voltage V CC 4.5 5 5.5 V Supply voltage GND 0 V Operating ambient temperature Topr 0 70 °C
Electrical Characteristics
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V) Item Symbol Min Typ Max Unit Test Conditions "H" input voltage V IH 2.0 V "L" input voltage V IL 0.8 V "H" output voltage V OH V CC − 0.8 V I OH = −4 mA "L" output voltage V OL 0.55 V I OL = 4 mA "H" input current I IH 1.0 µA V I = VCC WE, WRES, WCK, RE, RRES, RCK, D0 to D9 "L" input current I IL −1.0 µA V I = GND WE, WRES, WCK, RE, RRES, RCK, D0 to D9 Off state "H" output current I OZH 5.0 µA V O = VCC Off state "L" output current I OZL −5.0 µA V O = GND Operating mean current dissipation ICC 150 mA V I = VCC, GND, Output open tWCK, tRCK = 30 ns Input capacitance C I 10 pF f = 1 MHz Off state output capacitance C O 15 pF f = 1 MHz Function When write enable input WE is "L", the contents of data inputs D0 to D9 are written into memory in synchronization with rise edge of write clock input WCK. At this time, the write address counter is also incremented simultaneously. The write functions given below are also performed in synchronization with rise edge of WCK. When WE is "H", a write operation to memory is inhibited and the write address counter is stopped. When write reset input WRES is "L", the write address counter is initialized. When read enable input RE is "L", the contents of memory are output to data outputs Q0 to Q9 in synchronization with rise edge of read clock input RCK. At this time, the read address counter is also incremented simultaneously. The read functions given below are also performed in synchronization with rise edge of RCK. When RE is "H", a read operation from memory is inhibited and the read address counter is stopped. The outputs are in the high impedance state. When read reset input RRES is "L", the read address counter is initialized.
REJ03F0249-0200 Rev.2.00 Sep 14, 2007 Page 4 of 13 Switching Characteristics (Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V) Item Symbol Min Typ Max Unit Access time t AC 25 ns Output hold time t OH 5 ns Output enable time t OEN 5 25 ns Output disable time t ODIS 5 25 ns Timing Conditions (Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted) Item Symbol Min Typ Max Unit Write clock (WCK) cycle t WCK 30 ns Write clock (WCK) "H" pulse width t WCKH 12 ns Write clock (WCK) "L" pulse width t WCKL 12 ns Read clock (RCK) cycle t RCK 30 ns Read clock (RCK) "H" pulse width t RCKH 12 ns Read clock (RCK) "L" pulse width t RCKL 12 ns Input data setup time to WCK t DS 5 ns Input data hold time to WCK t DH 5 ns Reset setup time to WCK or RCK t RESS 5 ns Reset hold time to WCK or RCK t RESH 5 ns Reset nonselect setup time to WCK or RCK t NRESS 5 ns Reset nonselect hold time to WCK or RCK t NRESH 5 ns WE setup time to WCK t WES 5 ns WE hold time to WCK t WEH 5 ns WE nonselect setup time to WCK t NWES 5 ns WE nonselect hold time to WCK t NWEH 5 ns RE setup time to RCK t RES 5 ns RE hold time to RCK t REH 5 ns RE nonselect setup time to RCK t NRES 5 ns RE nonselect hold time to RCK t NREH 5 ns Input pulse rise/fall time tr, tf 20 ns Data hold time* t H 20 ms Notes: Perform reset operation after turning on power supply. * For 1-line access, the following should be satisfied: WE "H" level period ≤ 20 ms − 8192 tWCK − WRES "L" level period RE "H" level period ≤ 20 ms − 8192 tRCK − RRES "L" level period
REJ03F0249-0200 Rev.2.00 Sep 14, 2007 Page 5 of 13 Test Circuit CL = 30 pF: tAC, tOH Qn CL = 5 pF: tOEN, tODIS SW1 SW2 RL = 1 kΩ RL = 1 kΩ VCC Qn Input pulse level: 0 to 3 V Input pulse rise/fall time: 3 ns Decision voltage input: 1.3 V Decision voltage output: 1.3 V (However, t ODIS (LZ) is 10% of output amplitude and tODIS (HZ) is 90% of that for decision) The load capacitance C L includes the floating capacitance of connection and the input capacitance of probe. Parameter SW1 SW2 tODIS (LZ) Closed Open tODIS (HZ) Open Closed tOEN (ZL) Closed Open tOEN (ZH) Open Closed tODIS/tOEN Test Condition RCK RE Qn Qn VOL VOH GND 3 V GND 3 V 1.3 V 1.3 V 1.3 V 1.3 V 90% 10% tOEN (ZH) tOEN (ZL) tODIS (HZ) tODIS (LZ)
REJ03F0249-0200 Rev.2.00 Sep 14, 2007 Page 6 of 13 Operating Timing Write Cycle WCK WE Dn tDS tWCK Cycle n Cycle n + 1 Cycle n + 2 WRES = "H" (n + 4) Cycle n + 3 Cycle n + 4Disable cycle tWCKH tWEH tNWES tNWEH tWEStWCKL tDH tDS tDH Write Reset Cycle WCK WRES Dn tDS tWCK Cycle n − 1 Cycle n WE = "L" (2) Cycle 1Cycle 0 Cycle 2Reset cycle tNRESH tRESH tNRESStRESS tDH tDS tDH
REJ03F0249-0200 Rev.2.00 Sep 14, 2007 Page 7 of 13 Matters that Needs Attention when WCK Stops WCK WE Dn tWCK Period for writing data (n) into memory Period for writing data (n) into memory tNWES n cycle n cycle Disable cyclen + 1 cycle (n) (n) WRES = "H" tDS tDH tDS tDH Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of n + 1 cycle. The writing operation is complete at the falling edge after n + 1 cycle. To stop reading write data at n cycle, enter WCK before the rising edge after n + 1 cycle. When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
REJ03F0249-0200 Rev.2.00 Sep 14, 2007 Page 8 of 13 Read Cycle RCK RE Qn tRCK Cycle n Cycle n + 1 Cycle n + 2 RRES = "H" (n + 4) Cycle n + 3 Cycle n + 4Disable cycle HIGH-Z tRCKH tREH tNRES tNREH tRES tAC tRCKL tODIS tOEN tOH Read Reset Cycle RCK RRES Qn tRCK Cycle n − 1 Cycle n RE = "L" (2) Cycle 1Cycle 0 Cycle 2Reset cycle tNRESH tRESH tNRESS tAC tOH tRESS
REJ03F0249-0200 Rev.2.00 Sep 14, 2007 Page 9 of 13 Variable Length Delay Bits 1-line (8192 Bits) Delay A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output from memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily. WCK RCK Dn Qn WRES RRES WE, RE = "L" tRESHtRESS tDHtDS tDH tOHtAC8192 cycles tDS Cycle 1Cycle 0 Cycle 8190 Cycle 8191 Cycle 8192 (0') Cycle 8193 (1') Cycle 8194 (2')Cycle 2 (0) (1) (2) (3) N-bit Delay Bit (Making a reset at a cycle corresponding to delay length) WCK RCK Dn Qn WRES RRES WE, RE = "L" m ≥ 3 tRESHtRESS tDHtDS tDH tOHtACm cycles tDS tRESHtRESS Cycle 1Cycle 0 Cycle n − 2 Cycle n − 1 Cycle n (0') Cycle n + 1 (1') Cycle n + 2 (2') Cycle n + 3 (3')Cycle 2 (0) (1) (2) (3)
REJ03F0249-0200 Rev.2.00 Sep 14, 2007 Page 10 of 13 N-bit Delay 2 (Sliding WRES and RRES at a cycle corresponding to delay length) WCK RCK Dn Qn WRES WE, RE = "L" m ≥ 3 tRESHtRESS tDHtDS tDH tOHtACm cycles tDS Cycle 1Cycle 0 Cycle n − 1 Cycle n Cycle n + 1 Cycle n + 2 Cycle n + 3Cycle 2 Cycle n − 2 (0) (1) (2) (3) RRES tRESHtRESS N-bit Delay 3 (Disabling RE at a cycle corresponding to delay length) WCK RCK Dn Qn WRES RRES WE, RE = "L" m ≥ 3 tRESHtRESS tDHtDS tDH tOHtACm cycles HIGH-Z tDS Cycle 1Cycle 0 Cycle n − 1 Cycle n Cycle n + 1 Cycle n + 2 Cycle n + 3Cycle 2 (0) (1) (2) (3) RE tREStNREH
REJ03F0249-0200 Rev.2.00 Sep 14, 2007 Page 11 of 13 Shortest Read of Data "n" Written in Cycle n (Cycle n − 1 on read side should be started after end of cycle n + 1 on write side) When the start of cycle n − 1 on read side is earlier than the end of cycle n + 1 on write side, output Qn of cycle n becomes invalid. In the figure shown below, the read of cycle n − 1 is invalid. Cycle n Cycle n + 1 Cycle n − 2 Cycle n − 1 Cycle n (n)Invalid Cycle n + 2 Cycle n + 3 WCK Dn Qn RCK Longest Read of Data "n" Written in Cycle n: 1-line Delay (Cycle n <1>* on read side should be started when cycle n <2>* on write is started) Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1>* and the start of writing side n cycle <2>* overlap each other. Cycle n <1>* (n) <1>* (n) <0>* (n) <2>* (n) <1>* (0) <2>* (0) <1>* (n − 1) <1>* (n − 1) <0>* (n − 1) <2>* (n − 1) <1>* WCK Dn Qn RCK Cycle n <0>* Cycle 0 <2>* Cycle 0 <1>* Cycle n <2>* Cycle n <1>* Note: <0>*, <1>* and <2>* indicates a line value.
REJ03F0249-0200 Rev.2.00 Sep 14, 2007 Page 12 of 13 Application Example Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction M66255 × 2 Corrected image data Primary scanning direction Line (n − 1) K: Laplacian coefficient A N B Line n Line (n + 1) × K 1-line delay to to M66255 A Line (n − 1) image data B Line (n + 1) image data Adder A + B Subtractor 2N − (A + B) Adder N Line n image data 1-line delay to to Secondary scanning direction
REJ03F0249-0200 Rev.2.00 Sep 14, 2007 Page 13 of 13 Package Dimensions bp HE y 0.15 e 1.27 c 0° 10° L 0.8 1.0 1.2 0.05 A 2.4 11.63 11.93 12.23 A2 2.0 E 8.2 8.4 8.6 D 17.3 17.5 17.7 Reference Symbol Dimension in Millimeters Min Nom Max 0.35 0.4 0.5 0.13 0.15 0.2 MASS[Typ.] 28P2W-CPRSP0028DB-B RENESAS CodeJEITA Package Code Previous Code 1.07 1.47 y Index mark 28 15 141 F E HE A D e bp c Detail F L A2 A1 INCLUDE TRIM OFFSET. DIMENSION "*3" DOES NOT NOTE) DO NOT INCLUDE MOLD FLASH.
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