M66252P

M66252P RENESAS | Alldatasheet

Document overview

• Manufacturer or author: pROVIDED bY alldatasheet.com(free datasheet download site)
• PDF pages: 12

Technical content

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 stENESAS Renesas Technology Corp.

MITSUBISHI (DIGITAL ASSP) 1152 x 8-BIT LINE MEMORY (FIFO)

DESCRIPTION

The M66252P/FP is a high-speed line memory with a FIFO. PIN CONFIGURATION (TOP VIEW) (First In First Out) structure of 1152-word x 8-bit configuration which uses high-performance silicon gate CMOS process technology. o@o-G] [24] Do It has separate clock, enable and reset signals for write and paar &: OF [23]— D+ ate BT read and is most suitable as a buffer memory between ? @-L] [22] D2 Pe devices with different data processing throughput Qa = Da Readenableinpt RE=[5] & [20<WE — Write enable input FEATURES Read rese ipa FRES=[6] 8 WES Write reset input * Memory construction GND 8 Voc . 1152words x 8bits (dynamic memory) Readclockinpt ACK—=[B] 5 FTA WCK wiite clock input * High-speed cycle = - 50ns (min.) aR} 7 j— Ds * High-speed access 40ns (max.) Data output ¢ + HY Hilde | . * Output hold 5ns (min ) at OUP Qo < fi] [Ds eine + Fully independent, asynchronous write and read opera- ae |—D7 tions * Variable-length delay bit ine 24P4Y Outil * Output _ : ose S-8tate uuin® “24P2W-A APPLICATION Digital photocopiers, high-speed facsimiles, laser beam print- ers. BLOCK DIAGRAM Data input Data output Do Di D2 Da'Da Ds De D7 Qo Qi Q2 Qa 4 Q5 Qe Q7 | | Write WE a 5 > = Weim EB] 5] | 2 EB) | g Ore BB ioe 8 5 FI 8 ' 8 8 8 8 ' Write WAES g 3 Memory array g zg eed Tosat input WRES 9 = » g » (4152 x8 bits) Ko S Ki 5 ©) PRES feet input 8 3 3 8 ' 3 ® & 5 ' Wiite 4 2 g é Read Glock input WK G}-—>} = é is (8) ACK Sek input ' \\ Veo 4 GND 2tENESAS ;

MITSUBISHI (DIGITAL ASSP) M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) FUNCTION When read enable input RE is “L,” data on memory are out- When the status of write enable input WE is “L,” data on Do put to Qo thru Q7 synchronously with read clock input RCK thru D7 are written on the memory synchronously with write rise edges. At this time, read address counter executes clock input WCK rise edges. At this time, write address counting. counter executes counting The following read-related operations are also performed The following write-related operations are also performed _ synchronously with RCK rise edges synchronously with WCK rise edges. When RE is ‘H,” reading from memory is inhibited, and read When WE is “H,” writing on memory is inhibited, and write ad- address counter stops counting. The status of Qo thru Q7 be- dress counter stops counting. comes high-impedance. When write reset input WRES is ‘L,” write address counter is When read reset input RRES is “L,” read address counter is initialized initialized ABSOLUTE MAXIMUM RATINGS (Ta = ~20 ~ 70°C unless otherwise noted) Reterenoe pin GND [ex Powerdisspaton —_———SSS—*d TSC NT [Tax | Stee tonperatre i Note 1: Ta = 62°C are derated at -8. 8mW/°C (24P4Y) Taz 51° ate derated at -7. 5mW/"C (24P2W) RECOMMENDED OPERATIONAL CONDITIONS [eno —[Swpyvotage PP [ie Anbientieneniue mY ELECTRICAL CHARACTERISTICS (ta = -20.~70°C, Vcc = 5V#10%, GND = OV) ee es ec [vor ouput votegs _[ews—awa———SCSC~s | [va wuputvotage ]iueama SCY Cr pe fittest mee ||| iH “H" input current Vi= Voc | RRES, RCK 1.0 HA Do~D7 a eee es Me “L’ input current Vi= GND] RRES, RCK 10 pA Do~D7 [fom [Fauna curentunderatcondtin [Vosves SS | | [lon [eat urentunder“afeondtin —[Vo=GND| |) 6] a] = ontatrmtomonee|icaareme = | [| [| [o_inputcapacitance [time Tt Te [oo [ov caparenestnaeraF cenonen [fanz] or ; 2tENESAS

MITSUBISHI (DIGITAL ASSP) M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) SWITCHING CHARACTERISTICS (Ta =-20 ~ 70°C, Vcc = 5V+10%, GND = OV) [uc Accesstime rs | [tox | Outputholdtme ts Jtoen | Outoutenabletime ts | Loos Outputdisabletime aos TIMING CHARACTERISTICS (Ta = -20 ~ 70°C, Voc = 5V#10%, GND = OV), [ex | Witeiooe WOK) eyemtme SSS oP [nici [Wnt oto WOK) =H pulse wih | a P| | [wc [Wnt doa WOK) L"pulsewiety | a P| [rex [eas clock (ROK eyaetme sn | | [1c [Rea clock (ROKI"W" pues witha) | [iron | Reasolook (ROK) "pulse wah pes P| [10s | Iput ata setup me in eaponse WOM) SS) ts P| | [ror put ate nod ne (in eaponse to WOK) | sf) [1eess [Reset setup rie (in response to WOK end ROM) | as) || [1eesH [Resor nod ine (response WOK anaRcK) ss ]| [1whess [Reset non-slect satup tre in response io WicKanaRoK). | 4s || | na] [wrest [Reset non-selecthols tm n response taWoKanaicw) | __s || | rs] [wes | WE setup tne response ow) as | [wen | WEnnela me (response WOK] P| [wwes | WE nen-slect soup ame (n eaponsawWoK) iY as) | | [wwe | WErnen-slecthois ime (nreapense oWox) | s ||} ns_| [ies | REsetp me (nreaponse too) as P| | [reer | Eno ne (nvesponse toRCK) | [wees | RE-ner-esect setup tm rvesponse w ROK) S| as) || [twas | E-ner-sslecthlaime intespereetoRGK) S| ss | | | [it [Input pulse nos tine andjatiime | | P| Ln | Datahoidtime Note) 20s Note 1, The following conditions should beim et for each line access WE “H" level period < 20ms ~ 1152 - twok-WRES ‘L" level period RE “H" level period 2 20ms- 1152 «tRCK- RES ‘L" level period 2, Perform reset operation after turning on power supply. 2tENESAS :

MITSUBISHI (DIGITAL ASSP) 1152 x 8-BIT LINE MEMORY (FIFO) TEST CIRCUIT Vee Qn e S Rl=tka CL=30pF : 1AC, 10H ] Swi Qn Sw2 q CL=5pF : tOEN, ODIs rete | Input pulse level: 0~3V Input pulse rise time and fall time: 3ns Measurement reference level, input: 1.3V Measurement reference level, output:1.3V (Note: topis (LZ) is tested at 10% output amplitude, and tovis (HZ) is tested at 90%. output amplitude Load capacitance CL includes floating capacitance and probe input capacitance. TEST CONDITIONS FOR OUTPUT DISABLE TIME tovis AND OUTPUT ENABLE TIME toEN armmemenmnman Vi ROK 1.3V 1.3V RE topis(Hz) tOENZH) 20% wocoennn= VOH Gn 4.3 toDIS(LZ) tOEN@L) Qn 13V 10% -+--+-+-+ VoL ‘ 2tENESAS

MITSUBISHI (DIGITAL ASSP) M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) TIMING CHARTS + Write Cycles Cyclen | Cycle(nt1)_, Cycle(n+2) Disable cycles Cycle(n+3)_) Cycle(n+4) AveUATAUargeae edna mr ZN NKR K CC LLLL MIRO KKK WRES="H" + Write Reset Cycles Cycle(n—t)_, Cyclen Reset cycles Cycle 0 Cycle 4 Cycle 2 : - ™ ZN ANK & XZZIZZZN OO WEL" ztENESAS .

MITSUBISHI (DIGITAL ASSP) M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) + Matters that needs attention when WCK stops neycle | n+1 cycle neycle Disable cycle WE ce | /—|

0 LLLROKLNLLMNMLLLL ROKPALL 4

Period for writing data (n) Period for writing data (n) into memory into memory WRES = “H” Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of n+1 cycle. The writing operation is complete at the falling edge after n+1 cycle. To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle. When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well : 2tENESAS

MITSUBISHI (DIGITAL ASSP) M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) + Read Cycles Cyclen _, Cycle(n#1) , Cycle(n+2) Disable cycles Cycle(nt3)_ | Cycle(nt4) . avacae lea a tRoKH mi aE Che, tonis. aan Q "LLL Ko XK 08 Kp AKAD RRES="H” + Read Reset Cycles Cycle(n-1y)) Cycle. Reset cycles Cycle 0 Cycle 4 Cycle 2 . aver JN a JN SRES L ™ RAKE RKELRE ADEA AED REL” 2tENESAS ;

MITSUBISHI (DIGITAL ASSP) M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) VARIABLE-LENGTH DELAY BITS. ¢ 14ine (1152-bit) delay Awrite input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output from memory at the first rise edge of RCK in the cycle, so that 14ine delay can be made easily. Cycle 0 | Cycle 1 | Cycle 2 Cycle | CVC | cyte 0° | cycle 1" | Cycle 2° Weck RCK [ey se{] RRES oh tDs|toH » ZOOM OE OEOE OEE RE 1152 cycles | 10H ALLIES © LLLLLLLLLLLLLLL LBP LIEK KKEXY WE, RE="L" * n-bit delay 1 (Making a reset at a cycle corresponding to delay length) Cyde | Cycle Cycle 0 | Cycle 1 | Cycle 2 (n-2) (n-1)_| Cyole 0° | Cycle 1’ | Cycle 2° | Cycle 3” ROK ae =e m=) Wy RRES ‘ OH 1OS}tDH | | TAK OKKEKK EHH AXE KKK m cycles | = © KLLLLLLLLL LE LLL LLL LLOQ OK OXKE , ztENESAS

MITSUBISHI (DIGITAL ASSP) M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) * n-bit delay 2 (Sliding WRES and RRES at a cycle corresponding to delay length) Cycle Cycle MCW). Cydelnet)vM) OjcklnHZ}(W) — Cycatnasi) cycle o(w)|aycle 1(wy|cycle 2¢W)| (n-1,(W)_ | Cycle 0(R) [Cycle 1(R) | Cycle 2(R) | Cycle 3(R) ACK iRESS =TP . Tf 10S)10H tos|toH © LLLIK EKKO XKEIKEXK DK EKKEAKK AKO. mcycles © LLLLLLLLLLLL ALLL Lael KO KKOXK ERK! WE, RE=L" m23 + nbit delay3 (Disabling RE at a cycle corresponding to delay length) Cycle Cycle n(W) Cycke(n+i}(W¥) | Cycle(n+2)W) | Cycle(n+3}(W) Cyde o(w)|Cyde 400Ny [Cycle 2009) (n—1)(W) [Cycle O(R)| Cycle 1(F) | Cydle 2(R) | Cycle 3(R) RCK etl RRES: a f a ‘tositoH tos{tox \\—\\r {v y Ve y /—\\r [ [7 a LL KOKKOKKER ARAKI KAN m cycles Le E AW VA [v oa (LO XKOXKAXKER? WE, RE-"L” m23 ztENESAS ,

MITSUBISHI (DIGITAL ASSP) M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) ¢ Shortest read of data “n’ written in cycle n Cycle n—1 on read side should be started after end of cycle n+1 on write side When the start of cycle n—1 on read side is earlier than the end of cycle n+1 on write side, output Qn of cycle n becomes invalid. In the figure shown below, the read of cycle n-1 Is invalid. i i H Cycle n L_yclen+t L_ Oyde nz |" feydensa | 1 \\ ( ft 1 H i i i i r ) t Cycle n-2 t Cyclen-1 i Cycle n. H ne OF a i { ' ' nex NN YON OR >—K DFE X TS ™K ° (> Xe > + Longest read of data “n’” written in cycle n: 14ine delay Cycle n <1>* on read side should be started when cycle n <2>* on write is started Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1>* and the start of writing side n cycle <2>* over- lap each other. ! Cyclendiyt 4 Cycle 0 (2)* " ! Cycle n(2)* F i ews a } | ) | j | ie SSS ~\\, i H i i i | i Hl 1 i i i i H H i i | H H H i H ' i i t i i i Dn ln aK Tax | coxa | (nxay | 1 t t 1 t t i Cyclendoy* I 1 GCycleodiyt | Cydendiyt 1 ! ! fi fi fi i Qn (n- 1Koy* (nyoy* x (oxay* (nxiy* indicates a line value , RENESAS

MITSUBISHI (DIGITAL ASSP) M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) APPLICATION EXAMPLE Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction. N Me6252 Line n image data Do Q yo “3 aa a Corrected li a orrecte line 32 delay 32 e EES xk ae Hy Mee252 A Do Go | Line (n-1) t 2 | image data oD & : il delay g< 2 direction Sc fs OOOO0O

8 OOWDOOO <— tiem)

OOWOCOO <= linen Wet (sea) QO OOOO twine pawn cov OOO0000 sENESAS .