M66252FP

M66252P MITSUBISHI | Alldatasheet

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MITSUBISHI 〈DIGITAL ASSP 〉 M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) MITSUBISHI 〈DIGITAL ASSP 〉 M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) PIN CONFIGURATION (TOP VIEW) M66252P/FP Q 0 Q 1 Q 2 Q 3 GND RCK Q 4 Q 5 Q 6 Q 7 D 0 D 1 D 2 D 3 VCC WCK D 4 D 5 D 6 D 7 Data output Data output Data input Data input 24P4Y 24P2W-AOutline Read enable input Read reset input Read clock input Write enable input Write reset input Write clock input RE RRES WE WRES BLOCK DIAGRAM 24 23 22 21 16 15 14 13 Input buffer 12349 10 11 12 Output buffer Write control circuit Write address counter Memory array (1152 x 8 bits) Read address counter Read control circuit RE RRES RCK GND WE WRES WCK Vcc Write enable input Write reset input Write clock input Read reset input Read enable input Read clock input D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7   Data input   Data output

DESCRIPTION

The M66252P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 1152-word × 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read and is most suitable as a buffer memory between devices with different data processing throughput.

FEATURES

• Fully independent, asynchronous write and read opera- tions
• Variable-length delay bit APPLICATION Digital photocopiers, high-speed facsimiles, laser beam print- ers.

MITSUBISHI 〈DIGITAL ASSP 〉 M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) When read enable input RE is “L,” data on memory are out- put to Q0 thru Q7 synchronously with read clock input RCK rise edges. At this time, read address counter executes counting. The following read-related operations are also performed synchronously with RCK rise edges. When RE is “H,” reading from memory is inhibited, and read address counter stops counting. The status of Q 0 thru Q7 be- comes high-impedance. When read reset input RRES is “L,” read address counter is initialized. FUNCTION When the status of write enable input WE is “L,” data on D thru D7 are written on the memory synchronously with write clock input WCK rise edges. At this time, write address counter executes counting. The following write-related operations are also performed synchronously with WCK rise edges. When WE is “H,” writing on memory is inhibited, and write ad- dress counter stops counting. When write reset input WRES is “L,” write address counter is initialized. Conditions Reference pin: GND Ta = 25°C Ratings –0.5 ~ +7.0 –0.5 ~ VCC + 0.5 –0.5 ~ VCC + 0.5 550 (Note 1) –65 ~ 150 Symbol VCC VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Storage temperature Unit V V V mW ABSOLUTE MAXIMUM RATINGS (Ta = –20 ~ 70°C unless otherwise noted) Note 1: Ta ≥ 62°C are derated at –8.8mW/°C (24P4Y) Ta ≥ 51°C are derated at –7.5mW/°C (24P2W) RECOMMENDED OPERATIONAL CONDITIONS Symbol VCC GND Topr Parameter Supply voltage Supply voltage Ambient temperature Limits Min. 4.5 –20 Typ. Max. 5.5 Unit V V Symbol VIH VIL VOH VOL IIH IIL IOZH IOZL ICC C I C O Parameter “H” input voltage “L” input voltage “H” output voltage “L” output voltage “H” input current “L” input current “H” output current under “off” condition “L” output current under “off” condition Average supply current during operation Input capacitance Output capacitance under “off” condition ELECTRICAL CHARACTERISTICS (Ta = –20 ~ 70°C, VCC = 5V±10%, GND = 0V) Max. 0.8 0.55 1.0 –1.0 5.0 –5.0 100 Unit V V V V µA µA µA µA mA pF pF Typ.Min. 2.0 VCC – 0.8 LimitsTest conditions IOH = –4mA IOL = 4mA VI = VCC VI = GND VO = VCC VO = GND VI = VIH, VIL, Outputs are open tWCK , tRCK = 100ns f = 1MHz f = 1MHz WE, WRES, WCK, RE, RRES, RCK D 0~D 7 WE, WRES, WCK, RE, RRES, RCK D 0~D 7

MITSUBISHI 〈DIGITAL ASSP 〉 M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) Symbol tAC tOH tOEN tODIS Parameter Access time Output hold time Output enable time Output disable time SWITCHING CHARACTERISTICS (Ta = –20 ~ 70°C, VCC = 5V±10%, GND = 0V) Max. Unit ns ns ns ns Typ.Min. Limits Symbol tWCK tWCKH tWCKL tRCK tRCKH tRCKL tDS tDH tRESS tRESH tNRESS tNRESH tWES tWEH tNWES tNWEH tRES tREH tNRES tNREH tr, tf tH Parameter Write clock (WCK) cycle time Write clock (WCK) “H” pulse width Write clock (WCK) “L” pulse width Read clock (RCK) cycle time Read clock (RCK) “H” pulse width Read clock (RCK) “L” pulse width Input data setup time (in response to WCK) Input data hold time (in response to WCK) Reset setup time (in response to WCK and RCK) Reset hold time (in response to WCK and RCK) Reset non-select setup time (in response to WCK and RCK) Reset non-select hold time (in response to WCK and RCK) WE setup time (in response to WCK) WE hold time (in response to WCK) WE non-select setup time (in response to WCK) WE non-select hold time (in response to WCK) RE setup time (in response to RCK) RE hold time (in response to RCK) RE non-select setup time (in response to RCK) RE non-select hold time (in response to RCK) Input pulse rise time and fall time Data hold time (Note 1) TIMING CHARACTERISTICS (Ta = –20 ~ 70°C, VCC = 5V±10%, GND = 0V) Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Typ.Min. Limits Note 1. The following conditions should be met for each line access: WE “H” level period ≤ 20ms - 1152 · tWCK - WRES “L” level period RE “H” level period ≥ 20ms - 1152 · tRCK - RRES “L” level period 2. Perform reset operation after turning on power supply.

MITSUBISHI 〈DIGITAL ASSP 〉 M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) TEST CIRCUIT SW1 Closed Open Closed Open SW2 Open Closed Open Closed Parameter t ODIS(LZ) tODIS(HZ) tOEN(ZL) tOEN(ZH) Input pulse level: 0 ~ 3V Input pulse rise time and fall time: 3ns Measurement reference level, input:1.3V Measurement reference level, output:1.3V (Note: t ODIS (LZ) is tested at 10% output amplitude, and tODIS (HZ) is tested at 90% output amplitude.) Load capacitance CL includes floating capacitance and probe input capacitance. Qn C L=30pF : tAC , tOH SW1 SW2 R L=1kΩ Vcc C L=5pF : tOEN, tODIS R L=1kΩ Qn TEST CONDITIONS FOR OUTPUT DISABLE TIME t ODIS AND OUTPUT ENABLE TIME t OEN RCK GND GND VOH VOL RE Qn Qn 1.3V 1.3V 1.3V 1.3V 90% 10% tODIS(HZ) tOEN(ZH) tODIS(LZ) tOEN(ZL)

MITSUBISHI 〈DIGITAL ASSP 〉 M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) TIMING CHARTS

• Write Cycles Cycle n Cycle(n+1) Cycle(n+2) Disable cycles Cycle(n+3) Cycle(n+4) tWCK tWCKH tWCKL tWEH tNSES tNWEH tWES tDS tDH tDS tDH WCK WE Dn WRES=“H”
• Write Reset Cycles Cycle(n–1) Cycle n Reset cycles Cycle 0 Cycle 1 Cycle 2 tWCK tNRESH tRESS tRESH tNRESS tDS tDH tDHtDS WCK WRES Dn WE=“L”

MITSUBISHI 〈DIGITAL ASSP 〉 M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) tDS tDH tDS tDH (n) (n) n cycle n+1 cycle n cycle Disable cycle WCK WE D n tWCK Period for writing data (n) into memory tNWES Period for writing data (n) into memory WRES = “H”

• Matters that needs attention when WCK stops Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of n+1 cycle. The writing operation is complete at the falling edge after n+1 cycle. To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle. When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.

MITSUBISHI 〈DIGITAL ASSP 〉 M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO)

• Read Cycles
• Read Reset Cycles Cycle n Cycle(n+1) Cycle(n+2) Cycle(n+3) Cycle(n+4)Disable cycles tRCK tRCKH tRCKL tREH tNRES tNREH tRES tAC tODIS tOEN tOH RCK RE Qn RRES=“H” HIGH-Z Cycle(n–1) Cycle n Cycle 0 Cycle 1 Cycle 2Reset cycles tRCK tNRESH tRESS tRESH tNRESS tAC tOH RCK RRES Qn RE=“L”

MITSUBISHI 〈DIGITAL ASSP 〉 M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) VARIABLE-LENGTH DELAY BITS

• 1-line (1152-bit) delay A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output from memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily.
• n-bit delay 1 (Making a reset at a cycle corresponding to delay length) Cycle 0 Cycle 1 Cycle 2 Cycle (n–2) Cycle (n–1) Cycle 0’ Cycle 1’ Cycle 2’ Cycle 3’ tRESS tRESH tRESS tRESH tDStDS tDHtDH (0) (1) (2) (3) WE, RE=“L” m ≥ 3 m cycles t AC tOH Qn Dn WRES RRES WCK RCK Cycle 0 Cycle 1 Cycle 2 Cycle 1150 Cycle

1151 Cycle 0’ Cycle 1’ Cycle 2’

(0) (1) (2) Dn Qn WRES RRES WCK RCK WE, RE=“L”

MITSUBISHI 〈DIGITAL ASSP 〉 M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO)

• n-bit delay 2 (Sliding WRES and RRES at a cycle corresponding to delay length)
• n-bit delay 3 (Disabling RE at a cycle corresponding to delay length) Cycle 0(W) Cycle 1(W) Cycle 2(W) Cycle (n–1)(W) Cycle n(W) Cycle 0(R) Cycle(n+1)(W) Cycle 1(R) Cycle(n+2)(W) Cycle 2(R) Cycle(n+3)(W) Cycle 3(R) tRESS tRESH tNREH tRES tDS tDH tDS tDH m cycles tAC tOH Dn Qn RE WRES RRES WCK RCK WE, RE=“L” m ≥ 3 Cycle 0(W) Cycle 1(W) Cycle 2(W) Cycle (n–1)(W) Cycle n(W) Cycle 0(R) Cycle(n+1)(W) Cycle 1(R) Cycle(n+2)(W) Cycle 2(R) Cycle(n+3)(W) Cycle 3(R) tRESS tRESH tRESS tRESH tDS tDH tDHtDS (0) (1) (3) (2) m cycles tAC tDH Qn Dn RRES WRES WCK RCK WE, RE=“L” m ≥ 3

MITSUBISHI 〈DIGITAL ASSP 〉 M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO)

• Shortest read of data “n” written in cycle n Cycle n–1 on read side should be started after end of cycle n+1 on write side When the start of cycle n–1 on read side is earlier than the end of cycle n+1 on write side, output Qn of cycle n becomes invalid. In the figure shown below, the read of cycle n–1 is invalid. (n)invalid Cycle n Cycle n+1 Cycle n+2 Cycle n+3 Cycle nCycle n – 1Cycle n – 2 WCK D n RCK Q n (n – 1)〈1〉∗ WCK D n RCK Q n indicates a line value.
• Longest read of data “n” written in cycle n: 1-line delay Cycle n <1>* on read side should be started when cycle n <2>* on write is started Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1>* and the start of writing side n cycle <2>* over- lap each other.

MITSUBISHI 〈DIGITAL ASSP 〉 M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) APPLICATION EXAMPLE Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction. D 0 D 7 M66252 B Line (n+1) image data A Line (n–1) image data N Line n image data Corrected image data 1-line delay Adder A+B Secondary scanning direction ~ Q 0 Q 7 ~ D 0 D 7 M66252 Primary scanning direction Line (n–1) Line n Line (n+1) Subtractor 2N–(A+B) Adder N+K {2N–(A+B)} N' = N+K {(N–A)+(N–B)} = N+K {2N–(A+B)} K : Laplacean coefficient 1-line delay ~ Q 0 Q 7 ~ A N B