M66250FP

M66250P RENESAS | Alldatasheet

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Technical content

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 stENESAS Renesas Technology Corp.

MITSUBISHI < DIGITAL ASSP > 5120 8-BIT LINE MEMORY{FIFO/LIFO)

DESCRIPTION

The M66250P/FP ie a high-speed line memory with a FIFO PIN CONFIGURATION (TOP VIEW) (First In First Out) structure of 5120 -word%8-bit configura- tion which uses high-performance silicon gate CMOS pro- leo Ry [lb cess technology. oatkovtars ee an The M66250 can also be used for LIFO {Last in First Out). Be a ine The start address of reading can be specified sepciine z-f Fy—we | meee It has separate clock, enable and reset signals for write frerec sea rl z El waes “eee and read and is most suitable as a bulfer memory between (oviend 2 Vext5¥) devices with different data processing throughput. rrvonicon cK = fo ty wok tak | a+Bl s fa] — p, | FEATURES ommournns 08 OL neue © Memory configuration of 5120 words X 8 bits (dynamic fou fi] [i] 0, | memory) yom, Ot a c.cox veut = = take net @ High-speed cycle ses: 5Ons (Min) vane ane i 2 a he @ High-speed access seers gOns(Max,) —— foomesserur'e ESRES) RE nee SEE © Output hold essere tceeceeeeecseeeneeneees Bing (Min. _ ogpay mr @ FIFO/LIFO switching function Outline 28P2W-C ® Start address specification function (at reading) © LIFO operation on single chip e itt it i Note 1: SRES sets the system reset mode. SuSE UNOS ele oiin resielor tor eimodlezcontiol ia. Note 2: LAE can switch to a validness or invalidness of start © Write and read operations can be performed separately, address except during instruction cycies ® Variable-length delay bit ©) Qutputstssesssrsrise sessoconvaares “o-3-8tat@ APPLICATION High-speed facsimiles, digital photocopiers, laser beam printers. BLOCK DIAGRAM ___DATAINPUTS DATA CUTPUTS 9B BBO.O-2--DE-DOOAMID—. --—_ : A erry ree ia | | ae WRITE ENABLE = 5 Bovey - Sieur WE ? 5 3 z E LL me apenas 8 35 nr ARRAY de 8 ! INPUT e 5 a sizaxe airs, cor 3g ar ~ i ARES Wout i Fi £ g 2 ' ware crock wok @ E g Ea B b- <@ ack Reaociock é i ineu | | — yo | ( Lenten oo coNTAOL ciRCUIT eee] eh — | GND aa z | Fy FA Fa i . . . hy — 40 4g ee alt ACK _SA_ M/A cE Aopress (SRES) (LAE) COMMAND CLOCKINPUT Senay oe; ENABLE INPUT ABOHESS _ ADDRESS INPUT) SELECTION INPUT 7tENESAS

MITSUBISHI (DIGITAL ASSP> 5120X8-BIT LINE MEMORY(FIFO/LIFO) FUNCTION When RE is high-level, read is prohibited, and the read Write is performed by taking in the content of data inputs address counter stops. The output enters the floating state Do~Dz, in synchronous with the rise of the write clock input (high-impedance state). WC, when write enable input WE is low-level, the write When the read reset input ARES is set to low-level, the address counter incrementing or decrementing simul- read address counter is initialized. taneously. When WE is high-level, write is prohibited and When command enable input CE is low-level, the instruc- the write address counter stops. When the write reset input _tion cycle is enabled. The FIFO/LIFO mode is set by the WRES is set to low-level, the write address counter is in- _ serial address input SA in synchronous with the rise of the itialized, When the read enable input RE is low-level, read address clock input ACK during the Instruction cycle when is performed by outputting the memory content to data out- the mede/address selection input M/A is high-level. The put Qo~Q; in synchronous with the rise of the read clock _ start address is set by the serial address input SA in syn- input RCK, and the read address counter is incremented or _chronous with the rise of the address clock input ACK dur- decremented at same time. ing the instruction cycle when M/A is low-level FUNCTIONAL DESCRIPTION 1. Function Setting (1) Function setting table @® System reset setting se) (8A) | ore H SE | snes | [emes}) iRCK Function H L LT 1 [rire mode, no start eddreas satting, read counter raset = we | §84) |aace we | oe 7 | sae |WRES] wee | _Fuction H L t 1__| FIFO mode, no start address setting, writa counter reset : @ Mode setting ce | M/A SA CE SE ACK | 2x. Function L 4 t H__| FIFO mode seting ee L C__LIFO mode setting ae Xp sia acarens setng (13 bie) xi Lork Note : The above mode becomss effective after the first reset @ Effect of start address setting ae SA_| (M/A) | BW ‘is H H L L t__| Start address setting is effective _. [ow [| H [_H_|_L | _t | Stam address setting is not effective 2ENESAS

MITSUBISHI <DIGITAL ASSP> M66250P/FP $120X8-BIT LINE MEMORY(FIFO/LIFO) (2) FIFO/LIFO mode setting input WRES is low-level, mode setting is completed In syn- When the mode/address selection input M/A is high-level —_chronous with the rise of the write clock input WCK, also and the command enable input CE is tow-level, the FIFO/- provided that the write reset input WRES is low-level, in LIFO mode is selected by the serial address input SA, in synchronous with the rise of the read clock input RCK and synchronous with the address clock input ACK. When the the read reset input RRES is low-level. The address coun- command enable input CE is high-level and the write reset__ter is initialized at the same time. MR ‘twas ea tines (Tae) tC CT _ ES tsa RRES thecr res | ry RCK WCK

1 Mode setting Is completed

In the FIFO mode, the write address counter moves to (3) Start address setting address 0 in synchronous with the rise of the write clock in- When the mode/address selection input M/A is low-level put WCK when the write reset input WRES is set to fow- andthe command enable input CE is low-level, the level. The address of the write address counter increases address that reading starts from is set by serial address in- in synchronous with the rise of the write clock input WCK. Put SA in synchronous with the rise of the address clock in- When the read reset input RRES is low-level, the read put ACK. When the command enable input CE is high-level address counter moves to address 0 if the start address is and the read reset input RRES is low-level, the read not specified, and moves to the start address if the start address counter moves to the specified address in syn- address is specified, in synchronous with the rise of the chronous with the rise of the read clock invut RCK. read clock input RCK. The cycles of the read address counter increases in synchronous with the read clock input RCK. In LIFO mode the write address counter moves to address 0 or 5119 in synchronous with the rise of write clock input WCK, when the write reset input WRES is low-level, and, the read address counter moves to address 0 or 6119 if the start address is not specified or to the start address m or §119-m If the start address is specified, in synchronous with the rise of the read clock input RCK. When the read reset input RRES is low-level. The cycle of the write address counter goes up or down in synchronous with the rise of the write clock input WCK. 2ENESAS

MITSUBISHI <DIGITAL ASSP> 5120 8-BIT LINE MEMORY(FIFO/LIFO) tunes M/A Sas tas | tuaete (TRE) C Peet age & toess teens L__ || Toa teas, fean, Teas tenn Tors " SALA LK, A 786 teann 12 n 10 1 0 ch tuness: tress | Theor tercr RRES ‘a

1 Start address setting is completed

{4} System reset setting (FIFO and address counter reset setting) When the command enable input CE is high-level and SRES is low-level, and if the write reset input WRES and read reset input RRES are set to low-level, then the FIFO mode setting and the address counter are reset in synchro- nous with the rise of WCK and ACK, cE tsness: tsresH SA ‘SRES ae > teesH ex f RCK WRES RRES Lf (Note) To uneffect system reset, SA(SRES) should be set to high-level during WRES and PRES are low-level, 7tENESAS

MITSUBISHI <DIGITAL ASSP>

5120 X 8-BIT LINE MEMORY(FIFO/LIFO)

1. Write address and read address operation in FIFO and LIFO mode FIFO and LIFO Wire address/read address in read | Star adress setting White adress and read address operation __mede setting raseturite raset operation FIFO Ni cH | ° | Wrte aderess ° w A 5g fl F i { | tom = — — — — —- | write address: address counter Is sat to 0 } | ° R i 5119 | Read address : address counter Is set to 0 | feel ren LEI ay ee a LIFO H No a 51g @D Read address AL al write address @__._w BY read the wrta data) | Wie aderoes: the set address of 0 or 5119 is sat mutually | Write address jee We @ ead oddress - BR one op, | Read addross : the set address of 0 or read the write data @ is set mutually wate address Way FIFO. | ~~ Yee. er es ' Write adar | eaamress 9 Ww A 5119 i eo | ST ts asta caer sats 9 j Om RA _ 5119 | Read address ; address counter Is set to m which is read LO | specified by the start sddress ae i ee LiFO Yes 5119-m Sta @ Read address at a, | Ls Wiite address ! the set address of 0 or 5119

1 Write addrase fw ‘= set mutuaily

1@ Read address RY ! read the write data | Write address Ww. ! "1 | Road address : address counter Ia set to address 1 which Is specified as the start @ Read addross pe Bi address 4 read the write data (2) | ' Wiete address | Wy 7tENESAS

MITSUBISHI <DIGITAL ASSP>

5120 X8-BIT LINE MEMORY (FIFO/LiFO)

fT sew KOO lt ( tttC(‘“‘“(‘(‘(‘(CSNNNNNNNNNNNN OQ | i | UFO mode i —_ J | 1 FIFO mode | SA (address) SA (Address) ack ot ack t i a CE oH" teow BRE “HY ae w’ Start address Start address fs not effective: is not effective Start address Start address is effective is effective | |wox 1] [rox +] [wox 1] [ack 1 nek ot} {wor ot} | nck 1) fwow +t Write from | | Read from Write Read trom Read trom} | Write from | {Read from | } Write from start address address start address address 0| | address address 0} | address 0 Gorsit9 | | oorsing | | Sriyer® Dor 119 Start address — ee ge ers Zp FIFO rons LIFO mode Note : Perform write reset and read reset before setting function after power-on. 2tENESAS

MITSUBISHI <DIGITAL ASSP> 5120 8-BIT LINE MEMORY(FIFO/LIFO) ABSOLUTE MAXIMUM RATINGS (Ta=~20+70°, unless otherwise noted) Supply voltage _ PETE | Inout volage =0.5~Vooti5 | V. Output vortege 0. 5~Vec$0.5 v [Pa | Maximim powar dissipation Ta=wt — |. B50(Note 1) mw Tetg __| Storage temperature range 5 ~Fiee e Note 1: Taz68'C are derated at —9, Jmw/"C (28P,W) RECOMMENDED OPERATING CONDITIONS (1,=-2~+70) : Limite | unt Symbol Parameter i a Veo | Suppiy voltage LA | 8 5.5 v peratig ambient temperature range =29 ELECTRICAL CHARACTERISTICS (1a=—20~+70°C, Voo=5V+10%, unless otherwise noted) ‘Symbol Parameter Test conditions on zi Unit 7 . _# ee wins [typ | Max | Vn High-fovel Input voltage . 20 v Vin | Low-level input vatiage . _ _ “it oal Vv Vou. High-level output voltage _. fon=—4mA Neo-0.4 ai v_| You Low-level output voltage to.= 4m ; ~ 056 [Vv WrVoo_| WE, WARES, WOK, RE, RRES, ; ag High-level Input current ROK, CE, 00~D7 ro [#4 . . Wr Vee | AGK, SA(SRES), M/A(LAE) ° 0.27 WSGND | WE, WRES, WOK, RE, RAES, fig, Low-tevel input current BOK AGI BA(SREB), THO) HA WAUHE), Do~07 | . oa 4 Maeno {CE noe aa —0.27| mA loan Off state high-level ouiput current VaVec I 5.0 Voz | Ot state low-loval output eure WosGND — 50 | uA VirVin, Vic Output open i

1 Avere erating suppl it i

cl Input capacitance . f=tMHz _ 10 pF 00 foatat pecan Sg folate : is [opr SWITCHING CHARACTERISTICS (12=-2~+70, voc=5 V+10%, unless otherwise noted) Symbol Parameter i ‘Test conditions aa {Unit rar i est —"" the____| Ascoss time oe I [| ns fon pout hokd me Ue for | Output"L" period whenreasst 5 40 | ns atoen Output enable time co Sf 40 | ns toon Output disable time rs 40 — eS 2tENESAS

MITSUBISHI (DIGITAL ASSP> M66250P/FP 5120 8-BIT LINE MEMORY(FIFO/LIFQ) TIMING REQUIREMENTS (1a=—20~+20', Voo= 5 V10%, unless otherwise noted) Tims a twox | Wile clock (WGK) cyele —_ _ | | se | ns Tunas | Wie clock (WGK) "HY puke wa) 25 ra ‘uci | Wit cok (WOK)AL” pulse width aT Ins Tacx __ | Read clock (RCK) cycle a 50 Tons teow. | Read clock (RCK) *L” pulse width —_ 25 Pn on Bata ota de ater Wok | — so ia] tncau | Reset old tine alter WOK, RK TT et ng Tes WE set up tine hatore WOK —— [os i ns tenn WE hold tne after WK ——_ re twwven | WE nonselect hold time afer WOK Sp LL thes (LAE set up time before RCK 1 i ns “tne | AE hold time after ACK ee s| a Note 1 Fort ine acess, the folowing ahousd be eats ft WE “H? level periods 20ms—5120-twox- WRES "L" level pariod RE "H" level period 20ms-—6120-toer FRES “L" lever period TIMING REQUIREMENTS (19=—20~+70%, Voom 5 V1:10%, untess otherwise noted} tg [WA roe ti ater ACK | ee ee toes GE set up time betore ACK Ts | 25 Ls | tor GE Red time iar ACK —_ 5 i teas | SAsetuptime before ACK a “Ts ns dean ‘SA hold time after ACK es a en ms tLass. LAE setuptimebelore WOK, ACK et [ns Meat [SA Hohl ime site CR ACK aenteiet ae | E — [toew | CE setup time below WICK ACK when system reset ai Ee ee toene Z CE hold time after WOK, ROK when system reset ed 5 i a eee LL toness __| SRES set up lime betore WOK, AGK when system reset a! ns Iycnn | °U" pulse width for ACK ___ so | i | ns_| Thecus __| CE reeoveny timo alter resot a 100; i [ns 7tENESAS

MITSUBISHI <DIGITAL ASSP> 5120 8-BIT LINE MEMORY(FIFO/LIFO) TEST CIRCUIT Veo Aika S Swi ; ssw2 | CL 300 F tec. ton d Ci=5PF ! toon too J AL=1KO 3 ie esate whe Input pulse amplitude 1 O~3¥ Tom Me Swe Input pulse rise and fall time: Sn topaz | Slose "Open Roference voltage Inout nav me + OTe Ouiput 1.3 (However, tooisa.2) fs 10% of output amplitude and tooisinz? 18 30% ot crm ions, Open__| that for decision) fornzm | Open; Close Load capselty Cx includes float capacity of connection and input capacity of probe. tovis, toew Test Condition ack 1.3v 1.3 | evensenenceess GND RE sectetimemente GND tooisinz) aseews Qn L1.3V toorateed toewiau) on 13V 7tENESAS

MITSUBISHI <DIGITAL ASSP> M66250P/FP $120 X8-BIT LINE MEMORY(FIFO/LIFO) OPERATION TIMING 1. FIFO mode © Write cycle (This operation timing is irrelevant to start address setting) noycle ntl oyole nt 2 cycle Disable cycle nt3 cycle nt4 cycle bwor tween | twes, tos | tow tos | tow TUTTE © Kiker Mik NULTTLTITTTLTTLEN 0 KK XD WHES= “H" , TRE= “Lor “HY SRES= “H” © Write reset cycle (Irrelevant to start address setting) (The reset cycle requires a minimum of two cycles. Before the first resat cycle and after the power is turned on WRES should be set to high-level for 1 cycle or more.) f H cycle n cycle Reset cycle O cycle Voycle 2 cycles Wr | tos ton SATE) a) TEASE) | | Wee "U, LRES "U" or “HY ‘BRES “Ht” 2tENESAS

MITSUBISHI (DIGITAL ASSP>

5120 X 8-BIT LINE MEMORY (FIFO/LIFO)

© Matters that needs attetion when WCK stops neyclo att cycle noycle , Disable cyclo . a =a twwee WE a ore aa L| V7 r TIT ° GUY, VM GY » LK © KUL Ke XO ' ' Poriod for writing data Period for writing dsta (n) into memory {n) into memory WRES ="H" Input data of n cycle is read at the rising edge after WCK of n cycle arid writing operation starts in the WGK low-level period of n4+1 cycle, The writing operation Is complete at the falling edge after n+-1 cyole. To stop reading write data at n cycle, enter WCK betore the rising edge after n++1 cycle. When the cycle next tom cycle Is a disable cycle, WCK for & cycle requires to be entered after the disable cyole as well 2tENESAS

MITSUBISHI <DIGITAL ASSP> M66250P/FP 5120X8-BIT LINE MEMORY (FIFO/LIFO) @ Read cycle (This operation timing is Irrelevant to start address setting) noycle n+l cycle +2 cycle Disable cycle n+3 cycle nt4 cycle ° alae LS HIGH-Z » TTT MKD OEY RRES= “H", TAE= “L" or “HD SRES= “H" @ Read reset cycle (The reset cycle requires two cycles at minimum. During the lirst two cycles Qn is low-level, For one cycle or mora, RAES should be set to high-level befor the first reset cycle, and after power Is turned on.) oT eycle neyole Reset cycle Ocycle | oycle 2 cycle ARES lc ~ TTY) De WK [=| Te Ta] RE= “U" ,[AE= “H” ‘SRES= “H” 7tENESAS

MITSUBISHI <DIGITAL ASSP> M66250P/FP 5120X8-BIT LINE MEMORY(FIFO/LIFO) ®@ Read reset cycle (start address is set) (The reset cycle requires two cycles at minimum, During the first two cycles, Qn is tow-leval, For at least one cycle RAES should be set to high-level betore the firat reset cycle, and after power Is turned on.) n-3 n-2 n-I md m+2 m+3 eycte cycle cyole __ neycle Reset cycle meycle cycle cycle eycle theca _ sre ~ | on TDR Ko KX Ke XK) CX Nikon Koi Kors) WA (LAE) trecce cE ACK J \\--f \\ HE= “u" 2ENESAS

MITSUBISHI <DIGITAL ASSP> M66250P/FP 5120X8-BIT LINE MEMORY (FIFO/LIFO) 2. LIFO mode © Start address is not set (The reset cycle requires two cyoles at minimum. During the first two cycles, Qn Is low-level. For at least one cycle, RAES should be set to high-level and WRES should be set to high-level betore the first reset cycle and after power is tured on.) gue oe Reset cycle Gt Sole Doycle Reset cycle | Oeycle cycle ROK Noycle Neyole WES ‘ARES =) ( LK XiKe Kee TTL Ree XK © XZ © XK Kok Kers) AK Xe) (Ko XK N23 RE, WE = "L” TAE ="H" aE =" SRES meg ii i 2tENESAS

MITSUBISHI <DIGITAL ASSP> M66250P/FP

5120 X8-BIT LINE MEMORY(FIFO/LIFO)

® Start address is set (The reset cyote requires two cycles at minimum, and the first two cycles Qn Is low-level. More than ona cycle should be set when RAES is high-level before the first reset cycle after power on.) cycle cycle cycle cycle Reset cycle Ocycle | moycle Reset cycle 5118 cycle 59—m 5119 Bocycte 2 cycle 1 cycle O cycle Reset cycle cycle cycle Reset cycle m eycie taecr Neycle Neyele ARES 4 Ig SS KKM XK MOLLER KS XK EVO EDK XK ROOK) _,, KKK M/A (LAE) 4 gp taecce ce LJ ff Se rr ff = XaXXoY ACK / Yen \\ N23 RE, WE= “L” a 7tENESAS

MITSUBISHI <DIGITAL ASSP> 5120 8-BIT LINE MEMORY(FIFO/LIFO) 3. Variable length delay bits (1) FIFO mode/without setting of start address @ 1-line (5120 bits) delay A write input data is written to memory et the second rise edge of WCK In the cycle, and a read output data is output from memory at the first rise edge of RCK In the cyci6, 60 that 1-line delay can be made easily (A reset cycle requires at least 2 cycles, Qn goes to the “L" level during the first 2 cycles, However, itis necessary to get at least one oycle of ARES="H" and WAES="H" before the frst reset oycle after power Is turned on). Cycle Cycle Cycle Cycle | S120 | sir | sie Reset cycle Cycle d | Cycle 1 5119 (a) ") (2) wcK RCK tRESS| RRES || /—| al On UMMC STOOD ED? Y Ns J 4 4 7) tow | ee eo r r

0 YZ LLL GDL LLL KKK SONY

MITSUBISHI <DIGITAL ASSP> © N-bit delay 4 (Sliding input timing of WRES and RRES at a cycie corresponding to delay length) (A reset cycle requires at least 2 cycles. On goes to the L” level during the first 2 oyctes. However, it Is necessary to set at least one oycle of ARES= “H" and WRES="H" before the first reset cycle after power is tumed on). Reset cycle cycle | Cycle 1 Cycle n-2| cyclen—1} cyclen [Cycle st] WCK - RCK tRESS| ~ i FT | ARES t | KOK IOC IKON df 4, CX KKK ton © LLLLLLLLLLL LLL Lg D ROKK 7 a ve | Nz @ N-bit delay 2 (Disabling RE during the period corresponding to delay length te slide an address) (A reset cycle requires at least 2 cycles. Qn goes to the “L." lavel during the first 2 cyoles. However, it is necessary to set at least one cycle of RRES= "HY and WRES="H" before the first reset cycle after power is turned on) Reset oycle Oyeleo | Cycle 1 Cycle n—1} Cycle n [Cyole nt1|Cycle n+2 RCK tress! WRES RRES RE

0 TZ OOOOH

HIGH-2 Cl, {7 a KKK XA Lf ZI LI N23 2tENESAS

MITSUBISHI <DIGITAL ASSP> M662S50P/FP (2) FIFO mode/with setting of start address @ N-—m bit delay 1 (Slitding input ming ot WRES and ARES at a cycle enrresponicing: to delay fength) _ (aesst ete enue at leat Zones ce aoe fe te E sie aulng the first 2 cycles, However, it is necessary to set at least one cycle of RRES= eke erie WRES trecn. | UT | rt trRECR tress} “ TL La » TET KK YOUN . Imm mee te \\ eo ae x |

8 DS LL

(SRES) toe z2ENESAS

MITSUBISHI <DIGITAL ASSP> M66250P/FP 5120 8-BIT LINE MEMORY(FIFO/LIFQ} @ N-m bit delay 2 {Disabiing FRE during the period corresponding to delay length to slide en address) —, (A rater oyole renilies a eset apres 0 ores eens the first 2 cycles, Howaver, it is necessary to set at feast one cycle of RAES= Reset eyete Cycle 0 Cyclo 1 we ome cae WCK | RCK APY RRES me " 4 4 ETE TT NK Ne NK eo KK ee HIGH-Z Qn {cm (+1) M/A \\ (LAE) pee CE » TX VM ACK iY WE, RE="L" NZS ztENESAS

MITSUBISHI DIGITAL ASSP> M66250P/FP (3) Inter-FIFO delay compensation by setting a start address FIFO1 5 i 5 i we EEEELIEI[s(} —> ome FIFO2 [| EEE [I&II [ask] —> ows FIFO1 Without setting of start address. FIFO2 With setting of start address Address 2 {Areeat croie requires at tenet Fa eee On ores te eal ateaite first 2 cycles. However, It is necessary to set at least one cycle of RAES= Resateyelo Cycle’ Cycle 1 Cg oe ee Rent! 2 rn] rn | iam coors TTD VMS IAOENE coe TTT UVM AIOIE: SS a oe TTT _ eae WEI. 2=RE1, 2="L" LAE! 2="L" SRESt, 2="H" Nz3 7tENESAS

MITSUBISHI <DIGITAL ASSP > 5120 8-BIT LINE MEMORY (FIFO/LIFO) © Shortest read of data n" written In cycle n Cycle n~1 on read side should be started after end of cycle a+1 on write side When the statt of cycle n—1 on read side is earlier than the end of cycle n-+t on write side, output Qn of cycle n becomes Invalid. In the figure shown below, the read of cycle n=1 is invalid t Cyclon = Gyclantt =| Cyclent2 | | Cyclent 3 f y 1 | t s ‘ Cycle n—2 ! Syste nat es 1 Cycle n > nek NIN LYN SY " ED Ge GD, sy © Longest read of data “n” written in cycle n: 1-line delay Cycle n <1>* on read side should be started when cycle n <2)™* on write is started Output Qn of n cycle ¢1>* can be read until the start of reading sido n cycle <1)* and the start of writing side n ayole <2>* overlap each other.

1 Gyolen™ cL ee i yen”

DBn ttnayery? inary \\ X 10) <2>*! ener x (n)<ap"!

1 Cycle n <>* a i Cycle o* 1 i Gyclen* ft

On (nar Kinde XK ) OK {n-DK1>* (pt indicates a line value. 2ENESAS