M66242P

M66242P RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute*any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 stENESAS Renesas Technology Corp.

MITSUBISHI (DIGITAL ASSP) 4-CH 12-BIT PWM GENERATOR

DESCRIPTION

M66242 Integrated Circuit has four 12-bit PWM (pulse width PIN, CONFIGURATION (TOP VIEW) modulation) circuits which are built by using the CMOS (complementary metal oxide semiconductor) process. This IC controls PWM waveform by adjusting the “H” width according to serial data sent from MCU (micro controller unit) CHIPSELECT OS-[7] Voo or other device. Each channel can be independently con- RESET ReL2] @ Fa} pwn) trolled WRITE CONTROL WR>[3] & [f2}>-Pww2 High-resolution digital-analog converter can be formed eas- SERIALDATAINPUT sin=fa@] oS tPwne OUTPUT ily by connecting a low-pass filter circuit to the output pins of WRITE CLOCK Scuk->[5] 5 Fol ewma ths:ctreult OUTPUT CONTROL OC=[E] GB [}>xour cLOck OUTPUT FEATURES GND 8 }— XIN CLOCK INPUT * Built-in four 12-bit high-resolution pulse width modulation circuits Outline 14P4 + Easy digital-analog conversion — Quick output waveform {4P2N-A smoothing Control by 1.22mV possible per step (Vcc =5V) * Serial data input + ‘H” level width setting type + 4 independently controlled channels. APPLICATION + All 4 channels reset by reset input (R) High-impedance sta- + Analog signal control in televisions and audio systems tus after reset __ * Control of lamps, heaters and motors + All4 channels controlled by output control input (OC) + For,software servo in home appliances and industrial ma- + Settings take effect after ongoing cycle is completed chinety * Input: TTL level * Output: CMOS 3-state output Output current lo = +4mA * Voc =5V + 10% BLOCK DIAGRAM (EACH CHANNEL) €4 Voc

1 Upper byte’

register 8.BIT sin@ Ines PWM circuit saxO— registgy PWM 12-bit (9 Pwmi || register PWM circuit I | Lower byte Hy AY bit-rate sep register | multiplier @ Pwma Control Qo] oreut 0 Puma oO ji 1f2 @® xn divider Oscillation [x | circuit 9) Xout To other channels @ eno 2tENESAS

MITSUBISHI (DIGITAL ASSP) M66242P/FP A-CH 12-BIT PWM GENERATOR, FUNCTION subsections t, each of which has this basic waveform. Among The PWM output waveform of each channel is controlled by them, those which are designated by the 4-bit-rate multiplier taking in PWM data from MCU or other device via serial data are conditioned to have a “H” width that is longer by t. The input Sin lower 4 bits of PWM data are used to specify those subsec- Twelve-bit PWM data is input being divided between upper 8 tions (tm). The waveform of other subsections remains un- bits (upper byte) and lower 4 bits. changed. The lower 4-bit data is combined with command data such as A PWM waveform (12-bit resolution) is a combination of two. channel designation and input as 8-bit data (lower byte) types of waveforms which are different in “H” width, as de- The lower byte should be written first, and then the upper scribed above. byte. Even if only the upper byte is to be changed, rewrite When output control input OC is “H”, the output of every from the lower byte. channel turns high-impedance from the next cycle. The PWM waveform changes according to the new setting When reset input R is “L”, the output of every channel turns from the next cycle. high-impedance as soon as the ongoing cycle is completed, One cycle of PWM waveform (4096 divisions; 12-bit resolu-. and PWM data of all channels is reset. If R input is changed tion) are divided into 16 (24) subsections t. Each subsection _from “L” to “H’, the next cycle starts, however, the output of consists of 256 (2°; 8-bit resolution) minimum bits t (=2/ _the channels remains high-impedance fxin™). To enable output, rewrite input data for each channel. One subsection t consists of a 8-bit PWM waveform (basic . waveform). The “H” width of this waveform is determined ac- “hci: Clock XIN repeat frequency cording to the upper 8 bits of PWM data. One cycle has 16 PIN DESCRIPTIONS [A Resstineat | nput__[ Ear changlgpltin igh impedence tae ——————S——id Wo “ie a} data written ee ee Inputs/outputs signals generated by clock signal generation circuit. Oscillation XIN Clock input “Wput frequency is determined by connecting ceramic or quartz resonator between XIN and XOUT, The frequency of intemal clock (PWM timing clock) signals is a Oe the 1/2 divider of the frequency input from clock input XIN. When extemal XOUT Clock output, Output clock signals are used, connect clock generator to XIN pin and leave XOUT open 2tENESAS

MITSUBISHI (DIGITAL ASSP) A-CH 12-BIT PWM GENERATOR, (1) Upper byte resister ee (2) Lower byte resister Se ene are e) uv (Upper 8 bits: b11 thn b4) Write data desigNation bit 0: Lower byte only 1: Both l6werand upper bytes PWM obltput select bit

00 PWM 4

10: PWM 3 11: PWM 4 Output control select bit 0: Output disable (Bits b7~b4 and b0 are ignored.) 4: Output enable PWM output “H” width setting bits (Lower 4 bits: b3 to b0) Fig. 1 Upper and Lower Byte Resister Makeup Table 1 Mode Selection ~~ Input serial data PWM data setting b7 b6 bb bé 4 b2 bi of {output enable) 12-bit data setting b7 b6 bS b4 7 b2 bi i|b7 b6 bS b4 b3 b2 bi bi [oo uiputisabie x te bt xP Table 2 Patterns of Lower 4 Bits and Subsections Whose “H” Width Is Increased PWM register Subsections tm whose H width is Number of b3-b0 increased by ¢(m =0 thn 15) Subsections

0000 Nothing 0

0004 m=8 1 0010 m=4, 12 2 0100 m=2, 6, 10, 14 4 2tENESAS

MITSUBISHI (DIGITAL ASSP) 4-CH 12-BIT PWM GENERATOR, Upper byte register Lower byte register b7 bo b7 bo Perret Ett bee ee eer PWM register bit b4 _b3 bo oo CALI Determines “H” width of basic waveform Determines subsections tm whose (In this case, “H” width is 4A16 = 74) “H” width is increased by the minimum bit width of + (Refer to Table 2.) . (in this case,m =2, 4,6, 10, 12%ndy4.) Basic waveform ag SH . 2 KoA a EN kW (e.g. When fxn is 4MHz, t= 0.5) One subsection Designatéd/subse ction t=tx 256 “in (8-bit resolution) (In this case,rm=,2, 4, 6, 10, 12 and 14.) Output waveform x74 tt Risx74 | HEX ' \\ ' 1 ' tt 1 wo [Al ts | te fim | we | | to | mr | te | one fA] ts Subsection One cycle Fig. 2 PWM Waveform Output Example (Input data: 4A6 16) OPERATION PWM Waveform Output Serial Data Input__ _ (1) 12-bit PWM output When chip select CS is “L” and write control input WR is “L”, One PWM waveform cycle is divided into 16(24) subsec- data input to Sin at the edge where write clock input ScLk sta- tions t, and each subsection is further divided into 256 (2°) tus shifts from “L” to ‘H" is written. (See Fig. 3.) minimum resolution bits t (= 2/fxIn) At the edge where WR rises from “L” to ‘H”, the latest 8-bit The “H” width of subsection t basic waveform is deter- data writing is completed, and input data is stored in lower (or mined by the upper 8 bits of PWM data. upper) byte register. When writing on the lower byte or writing (In Fig. 2 above, “H” width is 4A16 = 74 x t) on both upper and lower bytes is completed, data on the Among these 16 subsections t, subsections tm designated lower byte register or, in the latter case, data on both lower by the lower 4 bits of PWM data have “H” width that is and upper byte registers is written on the PWM register of the longer by «. channel designated by lower bytes b2 and b1_ All setting pro- [In Fig. 2 above, the ‘H” width of designated 6 subsections cess ends with this writing, and PWM waveform changes ac- (m =2, 4, 6, 10, 12 and 14) is 4Bi6 = 75x 7] cording to the setting from the next cycle. 2tENESAS

MITSUBISHI (DIGITAL ASSP) M66242P/FP A-CH 12-BIT PWM GENERATOR, The “H’ width of undesignated subsections remains un- Even when output is in a high-impedance state, data on changed. each PWM register is retained, and data can be rewritten. As explained above, one cycle of waveformis acombina- (3) Reset tion of two waveforms different in the “H” width, When reset input R tums “L”, all operation is reset as soon (In Fig. 2 above, one cycle consists of 10 subsections as the ongoing cycle is completed: The outputs of all 4 whose H width is 74 x t and 6 subsections whose “H” channels turns highimpedance. The PWM register of width is 75 x 7.) each channel is reset Note: It is impossible to set one whole cycle to “H” level When Ris shifted from “L” to “H”, a next cycle starts, and (2)8-bit PWM output data writing becomes possible. However, outputs stay in As can be seen from the 12-bit PWM waveform output the high-impedance state. (See Fig. 6.) process as described above, 8-bit resolution PWM wave- To resume output, write input data for each channel form can be output by fixing the lower 4 bits of PWM data to 00002 Initial State All subsections from t10 to t's have the “H” width as deter- After power-on, outputs and PWM register data are unstable. mined by the upper 8 bits of PWM data (1)Reset Z Note: It is impossible to set one whole cycle to “H” level Reset input Ris kept on ‘LJeVel for more than one cycle (2.048ms when fxiNn is 4.MHz) or more, this integrated cir- Output Control cuit is put in a reset state) (1) Serial data input It stabilization needsymore time, e. g. when a quartz reso- By using data on lower byte register b3 (output control se- nator is used, keep\\P.on “L” level for an adequate period of lection bit), output of each channel can be controlled inde- time. pendently. The state of the selected PWM output changes (2)Serial data‘input after the completion of the ongoing cycle. When starting using this integrated circuit without reset- When b3 is set 0, lower byte register bO (write data desig- ting, input, false lower byte data (b0 =0) to stabilize lower nation bit) is reset. Do not write on upper byte in this case. byte\\register bO data, and then input normal data. (2) Output control input The status of all 4 channel outputs during a cycle is deter- mined depending on the status of output control input OC at the start of the cycle. (See Fig. 6.) WR q SiN DIP IDDID IDK OX bX b2aK 3K b4 KS KE KTR CC ICCC Souk LLL \\LLLLLLLMA PWM output Ongoing cycle Nee ope Fig. 3 Serial Data Write Timing 2tENESAS

MITSUBISHI (DIGITAL ASSP) A-CH 12-BIT PWM GENERATOR, PWM Setting Data 000 ! | 1 Hl f ! ' ! i { f 1 | ' 16 4 tot i i i i i i \\ I i tut i OO1te 4 tt i i i i H H i i ia i i rt * H i i i H H Tos mT i 00216 | Lat H \\ \\ \\ 1 H i Lo 1 003 16 tot i 1 1 tut I —m— i 1 toe t i i | i i i i tt i O0E ! ! OOF 16 ! La ! r ' 1 1 1 i I t er 1 010 16 Tl 1 1 1 1 1 1 1 1 1 hal 1 O11 16 | f IL ai 1 1 1 1 1 1 1 1 1 012 16 Ft nn tt tes t lexis! | _gtsx 160! i ' ' ' ; t i | ' 963 eg at ee f 1x2651 1 ' i { ' ' i i i i it 1 —— ie \\ H i i i \\ i H tat 1 FFD 16 | f 1 1 1 1 1 1 1 al 1 \\ a i i H | \\ \\ | 1 | i Lat \\ FFE te | 1 i 1 1 1 1 1 1 1 tot 1 i ak \\ i i i i i { \\ i i Lat i FFF ie | i H i | I i i H i i my i tw |~| w | 6 | te or | te | to | to | tm | me | te [+] us icycle a2 x 9? Tenn *? Fig. 4 12-bit PWM Waveform Output Example PWM Setting Data 000 16 a Set et set aet Set set apt 01016 txX2 tX2 tx2 tx2 2x2 Bx2 2x2 020 16 ‘ ax264 <x254 x254 4x 254 2x254 <x264 x 254 ee eee ee ——— el FEO 16 2x 265 2x 255 2x 255 2x 255 “4x 255 2x 255 2x 255. ——— ee ee FFO 16 to tt t2 8 113 tia 15 joyce od Fig. 5 8-bit PWM Waveform Output Example 2tENESAS

MITSUBISHI (DIGITAL ASSP) A-CH 12-BIT PWM GENERATOR, R S “ pee . | if { SIN im [ | Intermal signal “9” t | Li | (cycle start signal) High-impedance eycle High-impedance Fig. 6 Output Control Timing Chart <> aml =. ° Setting complete? YES OC ="L", Change “YES _| Repeat series settings? of operation NO Fig. 7 PWM Setting Flow Chart 2tENESAS

MITSUBISHI (DIGITAL ASSP) M66242P/FP A-CH 12-BIT PWM GENERATOR, ABSOLUTE MAXIMUM RATINGS (Ta = ~20’C ~ 75°C unless otherwise noted) [ves | Sumeiyvonage SSCS OY [vi [inputvotage SSS Oe P| [io fOuputcument mak [pa Powerdissipation Pm [Tay [Storage temperature Pesto RECOMMENDED OPERATIONAL CONDITIONS Jvx | wrinpuvotage PR oven [NGF vee fe [Otherinput [20 ST veo [| Jv, | atrmvotage PR oats Te [Otherinput | OPT os Tv | a cd fe rosonen [es SY oD fm] [Ter [Ambient temperature [am 20 To ELECTRICAL CHARACTERISTICS (Ta 5-20'C ~ 75°C, Voc = 5V+10% unless otherwise noted) [vor [Hr Outputyotiegsyyy [Pwei-s —[ioe—ama ooo | 47 [|v | [va Ounpuiliotiage ——[Pweti-a [oustma TT e T os T v | [iw Perinat vos Pt [mr inpiitgafrent wena TT tT | [ica [Hr outputourrentunder off condition [vo=veo | TT 50k | [ican [output currentunderottcondition ——[vozano | TT 80 | [icc | Powerdissipation | WieVoo.@ND,to-wa | | | 40|ua | [acc | Maximum quiescent power dissipation [Wise 4 o4viNotet) | | 04 [29 | ma | Note 1: Only one input (excluding XIN) should be set to this voltage. Other inputs should be connected to VOC or GND. 2tENESAS

MITSUBISHI (DIGITAL ASSP) M66242P/FP A-CH 12-BIT PWM GENERATOR, SWITCHING CHARACTERISTICS (Ta =~20'C ~ 75°C, Voc = 5V+10% unless otherwise noted) [ime dw [2s || we | Oupuhl XN ee 8 t00 | woe?) a Standard values are measured under conditions of Voc =5V and Ta =25°C TIMING CHARACTERISTICS (Ta = -20°c ~ 75°C, Vcc = 510% unless otherwise noted) a [326 20 [ns | [ 30 ([g io [ns | ayp es fT ns | [aces [ns | A Lp os ns | i Q Ce [io Te fs | > es @ [ so [se [ns | (?) ee ee ee [x [inputtatitime ee ‘Standard values are measured under conditions of Voc =5V and RS NOTE 2: TEST CIRCUIT & Input Vi \\ potion 9 6 9 (1) Pulse generator (PG) characteristics: tr=tt=6ns [es (2)Capacitance CL includes connection floating capacitance PG clement and probe input capacitance 5023 cL il GND I 2ENESAS

MITSUBISHI (DIGITAL ASSP) A-CH 12-BIT PWM GENERATOR, TIMING CHARTS teu(©3) thos). av L ov twRH WR 13 13v 13V C ov a tw(S)_ | tw(S) thewry | thscu _ , SOLK 1.3V- 13V 1.3V ov tus) | the) /—— sy SN i ov 004) XIN 50% 50% ov (Intemal clock) tPLH PHL VoH PWM1-4 50%: 50% VoL Note 3 (1) Shaded portions indicate that switching is possible during those periods (2) PWM outputs 1 to 4 change synchronously with intemal clock signals §. The frequency of these signals is the 1/2 divider of the frequency input from Xin APPLICATION EXAMPLE (Combination with electronic control M5283P for amplifier system) Electronic control M5283P Power amplifier co eaker c LR FM Graphic 5 pat? equalizer Zz c{| AV | Control microcomputer Buffer/Low-pass filter meseazryep [EWM | > 2tENESAS