M65665SP

M65665SP RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 7tENESAS Renesas Technology Corp.

PICTURE-IN-PICTURE SIGNAL PROCESSING DESCRIPTION APPLICATION The M65665SP/FP is a PIP (Picture in Picture) signal NTSC, PAL-M, PAL-N color TV processing LSI, whose sub-picture input is composite signal or component signals(Y/C or Y/U/V) for NTSC, RECOMMENDED OPERATING CONDITIONS high quality PIP system low cost and small size. Input voltage {émos interface) hy =P x Cope v * Internal V-chip data slicer (for sub-picture) . * Vertical filter for sub-picture ( Y signal ) NOTICE cert acitance (7 BE) between VDD and VSS pirs. * Base band comb filter (2 Line) = Pp P p * Single sub-picture ( selectable picture size : 1/9 , 1/16 ) *“ Sub-picture processing specification ( 1/9 , 1/16 size) : Quantization bits Y, B-Y, R-Y : 7 bits Horizontal sampling 229 pixels (Y), 57 pixels (B-Y, R-Y) Vertical lines 69/ 52 lines * Frame ( sub-picture ) on/off * Built-in analog circuits Two 8-bit A/D converter (for sub-picture signal) Three 8-bit D/A converters (for Y, U and V of sub-picture) Sync-tip-clamp, VCXO,OSD switch ... etc. i icatic * 11C BUS control ( parallel/serial control) : Block ‘diagram & Application examples PIP on/off , Frame on/off ( programmable luma level), Shown next pages Sub-picture size ( 1/9, 1/16 ), PIP position ( free position ), Picture freeze , Y delay adjustment, Chroma level, Tint, Black level, Contrast - etc. PIN CONFIGURATION (TOP VIEW) swm (J [= }y(R)OUT OSD_SEL [2] 7~ [= Josp_RIN SDATA ) [= ]AGndDA scik [J ~~ |= JujjouT Dvdd [=JOsD_GIN Dvss [2] [a vz BGPS [= ]V(B)OUT sck [2] = [= ]OSD_BIN BGPM [2] [o>] | |vddDA Fsc =] ol [=]vb Tests [i] oOo [= ]HD ESTEN <x oO [2-JAVss(vexo) swe Ce] <a [= 1xttal(P-N) RESET [2] < ” [=IxtaiP-mp csyncs [s| < J [= ]xtal(NT) \\Wad(ad) Ls | < = [= ]BIAS fintad 7 = (ad) [a | < [= JFilter Jin(ad) Ge vU | = JAVdd(vexo) Vib [a] [= Icvesin(ad) ‘in(ad) [= [= JAvss(ad) Vit |= Iciniaa) Outline 42 Pin SDIP Package (M65665SP) Outline 0.8mm pitch 42 Pin SOP Package (M65665FP) Te) 2tENESAS

PICTURE-IN-PICTURE SIGNAL PROCESSING BLOCK DIAGRAM 5 5 5 5 a a a ira 5 5 5 eee ce HP eC $ 2 a 33 'B = y & Q a a 2888 Y ery 2 > a6 2 >a IH ° ) o (\\ © @) a a a 2 a 2 3 aloe} CO) a a ki © Q Q EE 38 © wy 53 a aS O60" 2 °F ©) y = 8 6 3 i] 2. 22 Fi S| [4a] S© wy pe os a gs ay xO a 9 5 5 ® Ht _ g % Q ge OI g J © OH = || 2 Jz 86 HAR aM dé O-® OOOO® OO-~O-O-O OKO) a IS 3g TT IITs Tf tT %2 egeseeo" = RoE or ise 228 QQG a= ane H 8 g@ 888 DBAS ztENESAS 2

PICTURE-IN-PICTURE SIGNAL PROCESSING ABSOLUTE MAXIMUM RATINGS (Vss=0V) 'y m bol Parameter Conditions [wn] mee | nit Supply votage av) | | os | ae | | vo [output votage [os [versio | | fe fospacnens [owes f nme | | [Po |powerissipation | | 1200 Operating temperate | | 10.70 | ee | Tstg Storage temperature ; -50 125 | dea. | (*1) Output current per output terminal. But Pd limits all current. TYPICAL CHARACTERISTICS THERMAL DERATING (MAXIMUM RATING) 2000 ee z é S 3 g00 i eee ee i 2 oof 1 ie) t) 25 50 7075 100 125 AMBIENT TEMPERATURE Ta (deg.) NN 2tENESAS

PICTURE-IN-PICTURE SIGNAL PROCESSING DC CHARACTERISTICS (Ta = 25 deg. unless otherwise noted) (Vss=0V) yan bol ei " Conditi | timits | Unit ym bol arameter ondition nit | win [typ | ox | Input votage Je [orzo | lot | (23V CMOS intertace) Voo= 36V | 22 [| - | se | Input current | t |vo-sevveov | +o [| - [| wo |, {vr input vottage schmitt = |_- | | os |. | 165 | (GoV.CMOS intertace) | + Noo=3.av Pou | - far ly Dos | Input current | & |voo=sevweov | oo [ - [ o |, vou _| a ere ioe av, jojetoa |} = | 005 | | oz | - | - | | t [vo=sevvuzoav | 2 | - | - | CMOS output current mA Vorsavivonszev | - [ - | 2 | Output leakage current DA vorsevivorsev | so | - | 10 | Input pin capacitance | - fo 7 | is | [co [output pin capacitance team viosov = | | 7 a5 | oe Te) 2tENESAS

PICTURE-IN-PICTURE SIGNAL PROCESSING PIN DESCRIPTION PinNo| Name | vO | Function Remarks | | 2 |OSD_SEL__[CMOS input__[Output OSD select | 3 [SDATA [CMOS 1/0(5V)*1_[12C SDA input/output | 4 [scuk CMOS input(5v)*7]12C SCLinput | 5 [Dvddi [Digital vad _—[Vdd fordigitalpat_ = | 6 [DVssi_ [Digital Vss_[Vss fordigitalpat_ PT | 7 [BGPS [CMOS output__[Testoutput_ | 9 [BGPM [CMOS output__[Testoutput | io [FSC [cmos input _[Test input Conntect to GND | } 13 [swmG_ [cwosinout [connect to Vdd | | 14 [RESET [CMOS input___[Poweronresetinput PT | 15 [csyNcs [cmos input___| Sub picture external C-sync input | [16 [Avad (ADG) Analog Vdd | Vddfor internal ADC SSS CS | 17 [vin (ADc) Analog | Sub picture Vinputof ADC | is [UIN (ADC) [Analog [Sub picture Uinputof ADC TT | 19 IvRB_ [Analog [ Lowlevel reference voltage outputof ADC [ | 20 [YIN (ADC) Analog [Sub picture Y inputof ADC TT 22 |cin [Analog [Sub picture C inputofADC | 23 |AVss (ADC) |[AnalogVss____[VssforinteralADC | | 25 |AVdd (VCXO) [Analog Vdd [Vdd forvexO | 26 [FILTER [Analog | VCXO filter voltage connection | | 28 [Xtal (NTSC) [Analog [Xtal of NTSC connection | | 32 [HD [CMOS input(5v)*4] Main picture HD input | 33 [vp CMOS input(5V)*1] MAIN picture VD input PT | 34 |AVdd (DAC) [Analog Vdd__[VddforDAC 1-35 |OSDBIN [Analog [OSD inputof BOP [36 [vouT [Analog | Sub picture V or B output _—+| Sd 137 [vz Analog [Voltage reference outputof DAC | | 38 |OSDGIN [Analog [OSD inputofG | 40 [AVss (sub) _|AnalogVss__[VssforDAC 141 [OSDRIN [Analog [OSD inputofR_ [42 [YouT _JAnalog | Sub picture Y or Routput_______| J *1 ) (5V)means 5V I/F torelant NN 2tENESAS .

PICTURE-IN-PICTURE SIGNAL PROCESSING Dig. BASIC APPLICATION EXAMPLE “} Digital +3.3V power supply < NTSC only application example > zr Digital GND ati oot S Analog +3.3V power supply Sub C(Y/C) input. >———} He -& Analog GND f) Ee} f--<Sub Y(YUV) input sub CVBS and Y(Y/C) input. D—*4} | for] fis] FY 20" seceeeeees 0.220 HY hwy sb | [= fe 7<iSub U input o.covimax} 1.0vimax) 0.088: a re FE bgqtSub Vinput (eres aire fed fom exo al sort 12-9 Il | [= ov X1:1431818MHz boo o x [4] p ov > o x< DE 10K 4 10 8 (63v econmenies) [| f wm xX a mS Main HD input oOo *K co (83 recommended) | \\ Main VD input Xe) fo} ov or o al f=] le} . PIP Vor B output <J = al fu Thaw H of [at SUT} (yp) 00) fe] vy PIP UorG output < =| [4 IIC BUS Clock input f fo] IIC BUS DATA input /output r fe] CC» tt] Jorn PIPY or Routput < LY | aav w | \\ PIP SW output < NTSC / PAL-M/ PAL-N application example > 0.01 0.01 Sub C(YIC) input >} fm | Ht f] = Fz k<iSub Y(YUY) input ub CVBS and Y(Y/C) input. >——— [e} rh Ufo cova oz tly & Tor SS U nest 45 pin input when CSYNC tovimax) 0.0381] : [=H FagctSub Vinput (are ttre etd rem exten oz dE ay pee tHt— a x E+ — ial X1:14.31818MHz 129% HH] ] a < ov X2:14.30244MHz 19% HHS | ox {=} GH wv X3 : 14.328MHz se HHI —~ fa] oO x< mE Oe 10K 4 oS (83V recommended) [ \\ al lo x< 8 ws Main HD input | oO x*K , (83V recommended) / \\ Main VD input =| i lc} ov : OSD B input Lon fx | 2 le . PIP Vor B output < {= | [7] PUT owe oon 4 { seeeead SD G input onl fs | Fs PIP Uor G output < f=] [4 IIC BUS Clock input {0 | IC BUS DATA input /output = DSD R input onl {a | a OSD selection input tT Joven PIP Y or R output Not cn 3.3V 3.3V ow SL PIP SW output wl 7tENESAS

PICTURE-IN-PICTURE SIGNAL PROCESSING M65665SP/FP TV SYSTEM BLOCK DIAGRAM <BASIC > Composite CG Mi —a al y Video Signal [Separatio cee ; oem R Be ¢ oe eu | vet lo Processing Lee pH bo 3E M65665SP/FP vies apy Hite cwy Yoke ited [O Video coral Glo Jr signa || nt yt Processing YIUIV oy. sw _| Component ol Video Signal [Qt Composite © IC —a al Y Video Signal Separatio ee Ro R he oe 19 0 O l M65665SP/FP | ee BE iit Ro CVvly Deflection| | Yoke YIC Separated [GY a | Unit Video Signal ee ee PIP Signal = [Processing [” vp YIu/V ow. 7 Component ol Video Signal [Qt OSD_RGB 7tENESAS

PICTURE-IN-PICTURE SIGNAL PROCESSING cE TOSTSTSE OTTO OO [<7>_[DISP_T t [Sub picture display : [OJ off, [iJon |<e> |sizev 0 | 0 [Sub picture vertical size [Ova [116 [<5> [Size | 0 0 [Sub picture horizontal size [0] 1/9, [1] 1/16 [<4> [WENT 1 [Sub picture : [0] Still, [1] Moving [<g> [Bec | 0 | 0 [Back ground display :[O]off. {Jon [<2>_ [pecs dT 0 0 Sub picture mute [OJ off, [iJon [<i> [FREE RUN [|| 0 [VCXO oscilation : [0] Lock, [1] Freerun_ [<a> [Rvs 0g [HD/VD input synchronous mode selection : [0] sync., [1] async] loin [<7.0>|vxacro> | | 20n]Sub picture vertical postion |02h |<7:0> [HXA<7:0> | 20h] Sub picture horizontal position 03h [<7>_[DECODE | 0 _-| 0 [Sub picture color decoder reset [i] reset 0% [o> [conTRASTasts —|-—faanlaub picture ¥ oF R DAC ouput amottude commer | ae [<6:0>|U_DAC<6:0> | 32h|Sub picture U or G DAC output amplitude control [<7>_ [orc dT 1 [Frame display < [0] off, [1] on |<6>_|YUVN_RGB_SEL__ | 0 | 0 [PIP output mode selection: [OJ YUV.[4]RGB_ <7:6> | EXT_SC_SEL<1:0> Oh | Oh |Sub picture C-Sync sep. input selection : See renee eT lotsa nt ut see exam (18 pn] aaa | [<5:4> [DCONT<1:0> [0 | 0 [Sub picture sync sep.threshold setting (analog/digital) | [<3:0> [HT<3:0> Ah [Sub picture display timing adjust O7h [s7:6> JINPUT_SEL<1:0> || 2h [Sub picture input selection = [0] YC, [1] N.A., [2]CVBS, [3] YUV | [07 esr |e. sratt-so>—[— [oeh|sub beture GSP positon satng [<7:4>[ADJ<3:0> | 2h [Main/Sub switch delay control [<3:0>]YDL<3:0> Sh [Sub picture Y/C delay adjust 09h |<4:0>|Y_OFFSET<4:0> | [OFh[Sub picture Y bright control dan [=7> _[VEHIP_ONLY_—| 0] 0 [V-chip decode mode -(0] off. [iL on [<3:0> [BGY<3:0> || Ch [Back ground Y level setting |<3:0> [PEDESTU<3:0>____|_Oh_| oh [Sub picture U pedestal level (2's comp) och|sz>_JUV_FILTER_OFF | 0_| 0 [Sub picture U, V output filter: [Ojon [1Joff_ x<e> [SeT ACC | (0 _| 0 [Address ODh, OEh setting mode = [O]default, [1] enable to set__| xg>_[SeT size 0 TT 0 [Address 11h - 14h setting mode : [O]default, [1] enable to set__| |k2>_ [SET vcHIP___—i[|_-o_[ 0) [Address 15h - 17h setting mode : [O]default , [1] enable to set__| pie rnc cease [oo Perse oh <a> [C_GAIN'SEL_ | 9 _ [0 [Sub picture chroma: [0] xt, [i]x20 Sub picture killer on when its vert. sync lost : [0] on, [1] off kQ> [Cyr fh _ Oh internal chroma comb filter: [O] on: [t]off f° ee —arcairee 618 etwas cone ee fa |<6>_JAFCBITSEL | 0. | -0_[Sub picture AFC time constant [0] x2,[i]xi_ <5:0> [ACC LEVEL<5:0> |__| 15h[Sub picture color decoder amplitude OFh |[s7>_ JAUTO ENABLE | -0_| 0 [System automatic judgment : [0] off, [f]on |xe>__|BURST CLOCK MODE 0 | 0 [VCXO mode selection : [0] 1H based [1] 2H based [<5>__[PALN_DISABLE _|_ 0 | 0 [Main picture PAL-N : [0] enable, [1] disable [xa> [INV WFF TT 0 _[ 0 [invert sub picture field definition : [0] normal, [1linvert |kg> [INVIRFF | 0 [0 invert main picture field definition : [0] normal, [1] invert Kea —[vwope | 9 [0 Vertical cisplay modewhen PAL-N input 0] normal [1] wide | [<i> [RFF_FIX ———S&Y|_o_| 0 [Main picture field fix : [0] not fix, [1]fix [ko> [AUTO RFF FIX | 0 [1 [Automatic 50/60Hz Judgment : [0] enable, [1] disable 7tENESAS .

PICTURE-IN-PICTURE SIGNAL PROCESSING Internal register information (continuing) (preliminary ) [eases] pit [symbol [Resetvafvoee [remarks 10h [<7:6>|[NO_BSTLEVEL [| o [o [fortest [es:4> [BW_DET LEVEL | 0 | 0 [SW det. thresho(d setting : [0] off, [1] Tomv, [2] aomV, [a] 6am a [<6:0>[HYA<6:0> | [37h [Sub picture horizontal display pixel [12h [<7:0>[vvas70> || 44h [Sub picture vertical display line number )19n [ete fexcsig= | Th Sub picture horizontal capture position (coarse) —___ 14h | <7:6> |MVC<1:0> Oh | oh | Sub picture C-sync input mask period : a a aa a bee [<5:0>|VxS<5.0> | 29h [Sub picture sample startline SSS EEE [<6> [Pus CT 0 [0 fortest: Osetonly [<e> [7 To 0 fortest: Osetonly [<4:0> LINE NUM<4:0> | [11h [Data slicer line selection [16h |<7:0>[sTB_DLY<7:0> |__| 40h [Data slicer start bit detection parameter firearm [Yay [oeesterate sspears | 18n [<7> [EDGE ON | o_| 0 [Frame data independent control : [0] disable, [t]enable | |<3.0>|BGY_EDGE<3:0> |_| 0h [Frame data independent Y data setting Th [<a> [HPFoFF | (0. | 0 Subpicture Y output HPF : [OJon, [tJoff_ 1Bh [<3:0>[HADJ<3:0> | h_[ Oh [Parameter setting for PAL-M judgment Fae [vpacwo for [oan test Sub picture V or B DAC output amplitude control [4Dh]<7:0>|PINOE<7:0> | egh|fortest il AG 1Fh [<7:6>|system sTATE<t:0>| | __|Color state : [0] NTSC, [1] PAL-M, [2] PAL-N, [3]N.A.(Read only } [<5> [MAIN PALN | | |Mainis :[O[not PAL-N, [1] PAL-N(Readonly) [<a> [suB_uNLocK [| |vcxo is : fol Lock. [1] Unlock (Read only) [<3 [suB_PALN || [Subs : [0] not PAL-N, [1] PAL-N (Read only) [<2> [RDOF | [Main picture V sync is : [0] present, [1] not present (Read only) | [<1> [MAINBW | | [Test use; Always '1' when 10h<5:4> = "00" (Read only) [<o> [woor | | Sub picture V sync is : [0] present, [1] not present (Read only) | 20h [<7:6>[NoIsE<t:0> | | Test use (Readonly) [<5> |woor | Sub picture vertical syne detection (Read only) [<4> eps ack2 | | EDS data flag of even field : [0] no EDS, [1] EDS (Read only) _| [<3>_ [EDS ACki__——i{| | —_[EDS data flag of odd field : [0] no EDS, [1] EDS (Read only) _| [<2>_|SIGNAL_OK | | [Test use (Read only) [<i> |READ_REQB __—«{|__|__|Read request of even field : [0] no, [1] requesting (Read only) [<o> [READ_REQA | | | Read request of odd field : [0] no, [1] requesting (Read only) [2th |<7:0>|ppB<15:8> | | Even field Sliced data upper 8 bit (Read only) [22h [<7:0>]PpoB<7:0> || Even field Sliced data lower 8 bit (Read only) f2an [<7.0>]PDA<15;8> | | Od Feld Sliced data upper & bit (Read only) | [24n [<7:0>[ppa<70> TT [dd field Sliced data lower 8 bit (Readonly) Te) 2tENESAS °

PICTURE-IN-PICTURE SIGNAL PROCESSING The relation of input signal 32-pin (Main-HD) and 33-pin (Main-VD) is shown below rrr prohibition time of changing 33-pin signal 32-pin : : input f : Mag HD a eS Bsr hp -——?% (Main-VD)— ~10usec A : [Even to Odd] ; : 33-pin input : 7 . (Main-VD) > |.._A '+21.75usec +41.75usec : Even [| [Odd to Even] +53.5usec + be ia PAE POs POE is us 20us = = = = op = —— wpinput 4H 4H end of vertical equalization pulse 37.5us (hoe “Thos “Ton “Te “TT = = | = cK os VD input Driving Method and Operating Specification for Serial Interface Data (1) Serial data transmission completion and start A low-to-high transition of the DATA (serial data) line while the CLK (serial clocy) is high, that completes the serial transmission and makes the bus free. A high-to-low transition of the DATA line while the CLK is high, that starts the serial transmission and waits for the following CLK and DATA inputs. (2) Serial data transmission The data are transmitted in the most significant bit (MSB) first by one-byte unit on the DATA line successively. One-byte data transmission is completed by 9 clock cycles, the former 8 cycles are for address/data and the latter one is for acknowledge detection. (In reading state, ACK is 'H’ under these two conditions ; 1) the coincidence of two address data for the address data transmission, 2) the completion of 8-bit setting data transfer. In writing state, ACK is 'H' with the address coincidence and ACK is 'L' for detecting acknowledge input from the master (micro processor) after sending &-bit setting data.) For address/data transmission, DATA must change while CLK is 'L’. (The data change while CLK is 'H' or the simultaneous change of CLK and DATA, that will be a false operation because of undistinguished condition from the completion/start of serial data transfer). After the beginning of serial data transmission, the total number of data bytes that can be transferred are not limited, (3) The byte format of data transmission (The sequence of data transmission) a. The byte format during data setting to M65665FP are shown as follows. In right after the forming of serial data transmitting state, the slave address 24h (00100100b) is transferred. Afterwards, the internal register address (1 byte) and setting data (by 1 byte unit) are transferred successively. Several bytes of setting data can be handled in the one transmission. In this operation, the setting data are written into the address register whose address is increased one in initially transferred internal register address. b. The byte format during data reading from M65665FP are shown as follows. Before data reading from M65665FP, whose internal address need to be set by the data reading/transmitting. After the data reading/transmitting, the operation of "serial data transmission completion and start" (described in (1)) is necessary. Continuously, the slave address 25h (00100101b) is sent, and then the inverted read out data are available on ACK. Several bytes of writing data can be handled in the one transmission, too. In this operation, the setting data also are written into the address register whose address is increased one in initially transferred internal register address. Ge ——_ 2tENESAS

PICTURE-IN-PICTURE SIGNAL PROCESSING <The examples of serial byte transmission format> (1) The writing operation of the setting data (AAh) into M65665FP internal address of 00h [ Transmisson \\ Confirmation | yes ivati | of bus free IS| 24h |A| 00h |A) AAh |A/DE \\ Activation J (DATA='H') no “Li, . S : Operation of serial transmission start is applied A: Acknowledge detection on CLk for the D : Dummy clock feed for the release of release of acknowledge output state output state E : Operation of serial transmission completion (2) The writing operation of the setting data (FFh, 80h, EEh) into M65665FP internal address of 04h ~ 06h Ae Confi ti ( peenicae ) onfirmation | yes | activation of bus free S| 24h |A} 04h |A| FFh JA) 80h |A) EEh |ADIE \\ Z (DATA='H') no ‘Uis applied on CLk for the release of output state (3) The reading operation of the setting data from M65665FP internal address of 00h ( ‘ Confirmation T Mite | | Activation of bus free S) 24h /A) 00h |ADIE|S| 25h |A $$h A Xe TS (DATA="'H') no “Llis applied on CLk for the A: Bus free operation by the release of master (micro processor) output state 7tENESAS "

PICTURE-IN-PICTURE SIGNAL PROCESSING (4) The reading operation of the setting data from M65665FP internal address of 04h ~ 06h (Transmission | Confirmation | yes \\eieation of bus free S| 24h|A| 04h |A/DIE'S| 25h |A] $$h A"| $$h A"| $Sh A Ne yy, (DATA='H') no is applied on CLk for the A": Output 'L' operation by the release of master (micro processor) output state <Timing Diagram> 1 2 3 4 5 6 7 8 9 1 SDA \\ | Bitz \\ Bits | Bits | Bits \\ Bits |} Bit2 | Bitt | Bito | ACK | Bit7 y @pin | | fase J ese (ete) casey SDA (Read data) Bit7 I Bit6 ) Bits Bit4 | Bits | Bit2 Bit1 Bito Tae \\ (3 pin) (MSB) | | | | \\ \\ (LSB) \\(MSB)/\\ ACK | (2 pin) : ACK (Read data) | Bit7 | Bité | Bits Bit4 | Bits / Bit2 | Bitt | Bito | | aw i (2 pin) | (MsB)| \\ | | \\ —iass)| fs (sy) 7tENESAS ®

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PICTURE-IN-PICTURE SIGNAL PROCESSING Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials @These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. @A\\l information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www. mitsubishichips.com) @When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. @The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. @If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. @Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein Te) 2tENESAS %