M62055FP RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 10

Technical content

Features

  • Power-on reset
  • Watchdog timer
  • High accuracy voltage source of 3 V ± 5% (Max)
  • Over current protection circuit
  • The voltage detection accuracy of ±5% (Max)
  • Output power (VO) cutoff function at erroneous conditions
  • Backward voltage protection circuits for inputs and outputs Application
  • Handy information terminal equipment, CD-ROM, Portable audio equipment Pin Arrangement

8 VCC1

(Top view) M62055FP GND CLMWD VDTC

5 VO4RESET

Rev.2.00 Mar 10, 2006 page 2 of 9 Block Diagram Vref ≈0.9V Vref ≈1.5V S Q RQ S Q RQ R Q SQ R Q SQ S Q RQ Set priority Reset priority Reset priority Reset priority Set priority Vref =1.25V VCC VCC VD VO RESET TC WD Note: It indicates V O, unless otherwise noted. GND CLM VCC VCC VCC 40k 56k Vref ≈1.5V Vref ≈1.25V The input and output reversal conservation circuit Start circuitVoltage detector (Current limiter) Rise delay (300µs) Pin Functional Description Pin No. Symbol Functional Description

1 GND Ground

2 WD Input for watchdog timer

3 TC Setting up reset timer and watchdog timer

4 RESET Reset signal output

5 V O Feedback to a power supply for a MCU

6 V D Controlling the stability of an output voltage with a PNP transistor connected

7 CLM Current limiting

8 V CC Power supply voltage

Rev.2.00 Mar 10, 2006 page 3 of 9 Absolute Maximum Ratings (Ta = 25°C, unless otherwise noted) Item Symbol Ratings Unit Conditions Supply voltage V CC 13 V Output voltage V RM 10 V Reset pin Output current I RM 10 mA Watchdog pin input voltage V WDM 3 V Thermal derating K θ 4.0 mV/°C Ta ≥ 25°C Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C

Electrical Characteristics

(Ta = 25°C, unless otherwise noted) DC Characteristics Item Symbol Min Typ Max Unit Test Conditions Supply voltage V CC 3.5 — 13 V Circuitry current I CC — 500 900 µA Output voltage V O 2.85 3.00 3.15 V Bias current I Bmax — 10 — mA Listing short-circuit bias current IBSC — 1 — mA Input voltage regulation Reg-in — 0.02 — %/V V CC = 3.5V to 13V Loading voltage regulation Reg-lo — 20 — mV I O = 10mA to 100mA Output voltage thermal coefficient ∆VO/∆T — 0.02 — %/T Battery backup regulator CLM threshold voltage V THCLM — 200 — mV VTH1(H) 2.68 2.82 2.96 V VTH1(L) 2.58 2.72 2.86 V VO detection voltage ∆VTH1 — 0.1 — V Output voltage V OL(RST) — 0.2 0.4 V Isink = 4mA Output leakage current Reset pin Ileak — — 5 µA VTH2(H) 2.28 2.40 2.52 V Watchdog timer threshold voltage VTH2(L) 0.95 1.00 1.05 V WD input current I WD — — 1 µA V IN = 3V WD input threshold voltage V TH(WD) — 1.5 — V TC output current Itco — — –1 µA V IN = 0.8V Itc1 — 2.0 — mA V IN = 2.4V TC input current Itc2 8.0 — — mA In the output cutoff transmission mode Reset, watchdog timer VCC min operating voltage V CCMIN — — 2.0 V *1 Note: 1. The V CC minimum operating voltage at which the RESET output is low. AC Characteristics Item Symbol Min Typ Max Unit Test Conditions Watchdog timer t WD 0.5 1.2 1.7 ms C = 0.1 µF, R1 = 10kΩ Reset timer (1) t RST(1) 0.2 0.5 1.1 ms C = 0.1 µF, R1 = 10kΩ Reset timer (2) t RST(2) — — 10 ms C O = 10µF, R1 = 10kΩ , IL = 0 Input pulse width t WDIN 3 — — µs Transmission delay time t d — 20 — µs

Rev.2.00 Mar 10, 2006 page 4 of 9 Timing Chart VO+VCE(sat) VTH1(H) VTH2(H) tRST(1) tWD tRST(2) VTH2(L) VCC VO VTH1(L) Tick deactivation output cutoffoutput cutoff ↑ ≈0.9V ≈0.9V ↑ TC RESET WD 4 6 7 9 10 11 12 13 14 1 : 3 , 4 When VO rises to 0.5 V, RESET becomes low. Then, charging to a capacitor C connected to TC will be started at the VO of 2.82 V (VTH1(H)). When VCC rises to 3 V + VCE(sat), VO becomes stable. When TC voltage rises to 1 V (VTH2(L)), RESET becomes high. When it rises to 2.4 V (VTH2(H)) further, the capacitor C is switched to discharge and RESET becomes low. At the same tome of a change-over to the discharge from the capacitor C, V O is intercepted. Then, TC will be discharged completely at VO of 2.72 V (VTH1(L)). VO returns to 3 V right after it has fallen down to 0.9 V. RESET repeats above operation till a normal clock signal is input to WD pin. 10,11 8 , 7 , 9 12, In the case of a sudden power interruption, VO falls down according to a decrease of VCC. When it falls down to 2.72 V, the capcitor C is discharged and RESET will be low. In the case of a reversion from the power interruption, VO rises according to a increase of VCC. When it rises to 2.82 V, the charging to the capacitor C is started and RESET will be high right after TC voltage reaches 1 V. In the case of a clock signal for discharging the capacitor C is applied to pin WD before TC voltage reaches to 2.4 V, a reset signal to RESET is canceled. In the case of an abnormal clock signal is input, TC repeats charging / discharging alternately between 1 V and 2.4 V, so that RESET also repeats high / low till a normal clock signal is input. When V O falls down to 2.72 V, RESET becomes low. Description of Terms tRST(1) : Time from when TC begins to charge until it reaches to V TH2(L). tWD : Time from when TC is V TH2(L) until it reaches to VTH2(H). tRST(2) : Time from when TC is V TH2(H) until TC starts charging.

Rev.2.00 Mar 10, 2006 page 6 of 9 2. Pin (2) (WD pin) Input Frequency, Input Pulse Width, Charge/Discharge Time When input of (2) WD is normal, TC waveform (3) is as shown in figure 3. xV VTH2(H) = 2.4V Pin (3) Pin (2) VTH2(L) = 1.0Vt1 tWDIN t1 = C ⋅ R1 ⋅ ln 2 3 – X t2 = 1000 ⋅ C ⋅ R1 ⋅ ln X– 3 + 1R1 1000 – 2R1 1000 Figure 3

  • Conditions of an input to pin (2) (WD pin) (1) Input period should be tWD or less. (Pin discharge is completed before the arrival of VTH2(H) = 2.4 V) < f1 1.2 ⋅ C ⋅ R1 (2) Input pulse width tWDIN should be t2 or less.

Rev.2.00 Mar 10, 2006 page 8 of 9 Application Circuit Example 8 7 65 VCC VCC CIN 10µF +CO 10µF CTC CLM WD VD VO GND TC M62055FP GND CLOCK RESET MCU/MPU V DD RESET 1 2 3 4 RTC RRST

Rev.2.00 Mar 10, 2006 page 9 of 9 Package Dimensions DO NOT INCLUDE MOLD FLASH. NOTE) DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp HE y 0.1 e 1.27 c 0° 10° L 0.2 0.4 0.6 0.05 A 1.9 5.9 6.2 6.5 A2 1.5 E 4.2 4.4 4.6 D 4.8 5.0 5.2 Reference Symbol Dimension in Millimeters Min Nom Max 0.35 0.4 0.5 0.13 0.15 0.2 P-SOP8-4.4x5-1.27 0.07g MASS[Typ.] 8P2S-APRSP0008DA-A RENESAS CodeJEITA Package Code Previous Code 1.12 1.42 Detail F L A1A2 F Index mark y bpe A c E HE D

Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Renesas Technology Singapore Pte. Ltd.

1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632

Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 RENESAS SALES OFFICES © 2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .6.0