M61540FP

M61540FP RENESAS | Alldatasheet

Document overview

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Technical content

Features

• Electric Volume 6 channel independent Electronic Volume with High Voltage Transistor. (0 to –99dB/1dBstep, – ∞ dB)
• Gain Control 6 channel independent Gain Control (0, 6, 12, 18dB)
• Input Selector L/R channel 5 Input Selector
• Multi Channel Input 6 channel Input
• Tone Control Bass: –14 to + 14dB(2dB step), Treble: –14 to + 14dB(2dB step)
• REC Output Can use 2 Input for REC Output
• ADC Out Built-in ADC out Recommended Operating Condition Supply Voltage Range AVCC = 7.0V(typ), AVEE = –7.0V(typ), DVDD = 3.0 to 5.5V System Block Diagram MCU I/F CLOCK DATA Lout REC OUT Lch Rout Cout SLout SRout SWout Input ATT Out L for ADC REC OUT rotceles tupnI Input ATT Tone Gain Control VOL GND GND LchTone RchTone Bass& Treble Bass& Treble (4) (5) (4) (5) Multi Cin Multi SWin Multi SLin Multi SRin Gain Control Gain Control Gain Control Gain Control Gain Control Volume Volume Volume Volume Volume Volume Out R for ADC Rch rotceles tupnI AVCCAVEEDVDD DGND Multi Rin Multi Lin

Rev.1.0, May.31.2004, page 2 of 16 Block Diagram and Pin Configuration SLIN AGND SRIN RIN CIN LIN AGND LCDA RCDA SWIN TRER AGND 2RSAB 1RSAB INR2 INL2 INR3 5RNI )2RCER( CCVA 3LNI TUOL DNGD KCOLC ATAD TUOR TUOC EEVA INL1 INR1 5LNI )2LCER( 4RNI )1RCER( 4LNI )1LCER( TUOWS SLOUT SROUT TREL DNGA BASL2 BASL1 DDVD 1720 19 18 16 12 15 14 13 11 31 3532 33 34 36 40 37 38 39 Gain Control MCU I/F Cch Vol Gain Control Gain Control Gain Control Gain Control Rch Input ATT Input ATT Lch Lch Vol AVCCAVEE Bass /T r e Logic 25K SWch Vol 25K SLch Vol 25K SRch Vol 25K 50K Rch Vol 50K 50K 50K 50K 50K 50K 50K 50K 50K DVDD 50K Bass /T r e Gain Control 50K 50K 50K +++ + - --- +-+ - +- +- (Top View)

Rev.1.0, May.31.2004, page 3 of 16 Pin Description Pin No. Name Function 1, 8, 25, 32 AGND Analog Ground

2 LIN Input pin of L channel (Multi)

3 RIN Input pin of R channel (Multi)

4 CIN Input pin of C channel (Multi)

5 SWIN Input pin of SW channel (Multi)

6 SLIN Input pin of SL channel (Multi)

7 SRIN Input pin of SR channel (Multi)

9 SROUT Output pin of SR channel

10 SLOUT Output pin of SL channel

11 SWOUT Output pin of SW channel

12 COUT Output pin of C channel

13 DVDD Power supply to internal logic circuit

14 DATA Input pin of control data

15 CLOCK Input pin of control clock

16 DGND Ground of internal logic circuit

17 ROUT Output pin of R channel

18 LOUT Output pin of L channel

19, 20 BASR1, BASR2 Frequency characteristic setting pin of R channel tone control (BASS) 21, 22 BASL1, BASL2 Frequency characteristic setting pin of L channel tone control (BASS)

23 TRER Frequency characteristic setting pin of R channel tone control (Treble)

24 TREL Frequency characteristic setting pin of L channel tone control (Treble)

26, 28, 30 INR1, 2, 3 Input pin of R channel (Input Selector) 27, 29, 31 INL1, 2, 3 Input pin of L channel (Input Selector) 33, 35 INL4, 5/ RECL1, 2 Input pin of L channel (Input Selector) can use REC output pin 34, 36 INR4, 5/ RECR1, 2 Input pin of R channel (Input Selector) can use REC output pin

37 AVEE Negative power supply to internal analog circuit

38 AVCC Positive power supply to internal analog circuit

39, 40 ADCR, ADCL Output pin for ADC

Rev.1.0, May.31.2004, page 4 of 16 Absolute Maximum Ratings Parameter Symbol Ratings Unit Condition Power Supply Supply Voltage 16 V AVCC-AVEE

6 DVDD-DGND

Power dissipation Pd 1.46 W Ta ≤25°C Thermal derating K 85.3 mW/°C Ta>25°C Operating temperature Topr –20 to +75 °C Storage temperature Tstg –40 to +125 °C Note: AVEE ≤DGND<DVDD≤AVCC THERMAL DERATINGS (MAXIMUM RATING) )W( dp NOITAPISSID REWOP AMBIENT TEMPERATURE Ta ( C ) 1.46W 0.88 02 5 5 0 7 5 1 0 0 125 150 0.5 1.0 1.5 2.0 Recommended Operating Conditions (Ta=25°C, unless otherwise noted.) Parameter Symbol Min Typ Max Unit Condition Analog Supply Voltage (Positive) AVCC 4.5 7.0 7.5 V Analog Supply Voltage (Negative) AVEE −7.5 −7.0 −4.5 V Digital Supply Voltage DVDD 3.0 3.3 5.5 V Logic “H” level Input Voltage VIH DVDD ×0.7  DVDD V DGND reference Logic “L” level Input Voltage VIL DGND  DVDD×0.2 V DGND reference Note: AVEE ≤DGND<DVDD≤AVCC

Rev.1.0, May.31.2004, page 5 of 16 Relationship Between Data and Clock D0 D1 D2 D3 D21 D22 D23DATA Data signal is read at the rising edge of CLOCK. Make "H" at the timing which DATA of D0-D23 make latch. When DATA is "H", latch signal is created at the falling edge of CLOCK. CLOCK Clock and Data Timings tWHC tcr 25% 75% LATCH tWLC tftr tHLD tSHD tHHD tSLD tHLD (D0 D23) tSLD DATA CLOCK 50% 25% 75% tSC to Timing Definition of Digital Block Limits Parameter Symbol Min Typ Max Unit CLOCK cycle time tcr 8   CLOCK pulse width ("H" level) tWHC 3.2   CLOCK pulse width ("L" level) tWLC 3.2   Rising time of clock and data tr   0.8 Falling time of clock and data tf   0.8 DATA setup time (Rising time of clock) tSHD 1.6   DATA setup time (Falling time of clock) tSLD 1.6   DATA hold time ("H" level) tHHD 1.6   µs DATA hold time ("L" level) tHLD 1.6   CLOCK setup time tSC 1.6  

Rev.1.0, May.31.2004, page 6 of 16 Power on Reset This IC built-in the power on reset function. The voltage of DVDD (13 pin) -DGND (16 pin) less than 2.6V, the serial DATA can not accept. 2.6 V (V) (S) Reset time Release of reset. After reset is canceled, the serial DATA can accept. DVDD(3pin) - DGND(6pin) Note: AVEE ≤DGND<DVDD≤AVCC Data Control Specification Initialize all data of the 4 formats when Digital Power supply (DVDD) turns on. Prohibit using except specified Data code as follows. 01(8) Lch Volume 0 D0b D1b D2b D3b D4b D5b D6b D7b D8b D9b D10b D11b D12b D13b D14b D15b D16b D17b D18b D19b D20b D21b D22 D23 (7 ) Lch Gain Control (8) Rch Volume (7) Rch Gain Control 000 D0a D1a D2a D3a D4a D5a D6a D7a D8a D9a D10a D11a D12a D13a D14a D15a D16a D17a D18a D19a D20a D21a D22 D23 (1) Input Selector (2) REC Output 000(5) Bass/ Tone control Bypass (6) Treble (3 ) ADC Input ATT (4 ) L/R Vol Input 10(8) Cch Volume 0 D0c D1c D2c D3c D4c D5c D6c D7c D8c D9c D10c D11c D12c D13c D14c D15c D16c D17c D18c D19c D20c D21c D22 D23 (7 ) Cch Gain Control (8) SWch Volume (7 ) SWch Gain Control 000 11(8) SLch Volume 0 D0d D1d D2d D3d D4d D5d D6d D7d D8d D9d D10d D11d D12d D13d D14d D15d D16d D17d D18d D19d D20d D21d D22 D23 (7 ) SLch Gain Control (8) SRch Volume (7 ) SRch Gain Control 000 Slot2 Slot1 Slot3 Slot4 Note: No guarantee except for these codes.

Rev.1.0, May.31.2004, page 7 of 16 Setting Code It’s initial setting when power is turned on. (1) Input Selector Setting D0a D1a D2a ALL OFF 0 0 0 IN1 0 1 0 IN2 1 0 0 IN3 1 1 0 IN4* 0 0 1 IN5* 0 1 1 Note: *No guarantee except for these codes. (2) REC Output REC Output REC1 REC2 Setting D3a D4a OFF 0 0 ON 1 *1 1 *2 *1: When IN4 selected, REC1 can not use. IN4 REC1 D0a D1a D2a D3a ON OFF 0 0 1 1 *2: When IN5 selected, REC2 can not use. IN5 REC2 D0a D1a D2a D4a ON OFF 0 1 1 1 (3) ADC Input ATT ATT Setting D5a D6a 0dB 0 0 –6dB 0 1 –12dB 1 0 –18dB 1 1 (4) L/R Volume Input Setting D7a Selector In 0 Multi In 1

Rev.1.0, May.31.2004, page 8 of 16 It’s initial setting when power is turned on. (5) Bass/Bypass ATT Setting D8a D9a D10a D11a +14dB 1 1 1 1 +12dB 1 1 1 0 +10dB 1 1 0 1 +8dB 1 1 0 0 +6dB 1 0 1 1 +4dB 1 0 1 0 +2dB 1 0 0 1 0dB 1 0 0 0 −2dB 0 0 0 1 −4dB 0 0 1 0 −6dB 0 0 1 1 −8dB 0 1 0 0 −10dB 0 1 0 1 −12dB 0 1 1 0 −14dB 0 1 1 1 Bypass*3 0 0 0 0 *3: Tone control is bypass. (6) Treble ATT Setting D12a D13a D14a D15a +14dB 1 1 1 1 +12dB 1 1 1 0 +10dB 1 1 0 1 +8dB 1 1 0 0 +6dB 1 0 1 1 +4dB 1 0 1 0 +2dB 1 0 0 1 0dB 1/0 0 0 0 −2dB 0 0 0 1 −4dB 0 0 1 0 −6dB 0 0 1 1 −8dB 0 1 0 0 −10dB 0 1 0 1 −12dB 0 1 1 0 −14dB 0 1 1 1 (7) Gain Control Lch D0b D1b Rch D9b D10b Cch D0c D1c SWch D9c D10c SLch D0d D1d ATT Setting SRch D9d D10d 0dB 0 0 6dB 0 1 12dB 1 0 18dB 1 1

Rev.1.0, May.31.2004, page 9 of 16 (8) 6ch Volume It’s initial setting when power is turned on. Lch D2b D3b D4b D5b D6b D7b D8b Rch D11b D12b D13b D14b D15b D16b D17b Cch D2c D3c D4c D5c D6c D7c D8c ATT SWch D11c D12c D13c D14c D15c D16c D17c SLch D2d D3d D4d D5d D6d D7d D8d SRch D11d D12d D13d D14d D15d D16d D17d 0dB 0 0 0 0 0 0 0 –1dB 0 0 0 0 0 0 1 –2dB 0 0 0 0 0 1 0 –3dB 0 0 0 0 0 1 1 –4dB 0 0 0 0 1 0 0 –5dB 0 0 0 0 1 0 1 –6dB 0 0 0 0 1 1 0 –7dB 0 0 0 0 1 1 1 –8dB 0 0 0 1 0 0 0 –9dB 0 0 0 1 0 0 1 –10dB 0 0 0 1 0 1 0 –11dB 0 0 0 1 0 1 1 –12dB 0 0 0 1 1 0 0 –13dB 0 0 0 1 1 0 1 –14dB 0 0 0 1 1 1 0 –15dB 0 0 0 1 1 1 1 –16dB 0 0 1 0 0 0 0 –17dB 0 0 1 0 0 0 1 –18dB 0 0 1 0 0 1 0 –19dB 0 0 1 0 0 1 1 –20dB 0 0 1 0 1 0 0 –21dB 0 0 1 0 1 0 1 –22dB 0 0 1 0 1 1 0 –23dB 0 0 1 0 1 1 1 –24dB 0 0 1 1 0 0 0 –25dB 0 0 1 1 0 0 1 –26dB 0 0 1 1 0 1 0 –27dB 0 0 1 1 0 1 1 –28dB 0 0 1 1 1 0 0 –29dB 0 0 1 1 1 0 1 –30dB 0 0 1 1 1 1 0 –31dB 0 0 1 1 1 1 1 –32dB 0 1 0 0 0 0 0 –33dB 0 1 0 0 0 0 1 –34dB 0 1 0 0 0 1 0 –35dB 0 1 0 0 0 1 1 –36dB 0 1 0 0 1 0 0 –37dB 0 1 0 0 1 0 1 –38dB 0 1 0 0 1 1 0 –39dB 0 1 0 0 1 1 1 –40dB 0 1 0 1 0 0 0

Rev.1.0, May.31.2004, page 10 of 16 Lch D2b D3b D4b D5b D6b D7b D8b Rch D11b D12b D13b D14b D15b D16b D17b Cch D2c D3c D4c D5c D6c D7c D8c ATT SWch D11c D12c D13c D14c D15c D16c D17c SLch D2d D3d D4d D5d D6d D7d D8d SRch D11d D12d D13d D14d D15d D16d D17d –41dB 0 1 0 1 0 0 1 –42dB 0 1 0 1 0 1 0 –43dB 0 1 0 1 0 1 1 –44dB 0 1 0 1 1 0 0 –45dB 0 1 0 1 1 0 1 –46dB 0 1 0 1 1 1 0 –47dB 0 1 0 1 1 1 1 –48dB 0 1 1 0 0 0 0 –49dB 0 1 1 0 0 0 1 –50dB 0 1 1 0 0 1 0 –51dB 0 1 1 0 0 1 1 –52dB 0 1 1 0 1 0 0 –53dB 0 1 1 0 1 0 1 –54dB 0 1 1 0 1 1 0 –55dB 0 1 1 0 1 1 1 –56dB 0 1 1 1 0 0 0 –57dB 0 1 1 1 0 0 1 –58dB 0 1 1 1 0 1 0 –59dB 0 1 1 1 0 1 1 –60dB 0 1 1 1 1 0 0 –61dB 0 1 1 1 1 0 1 –62dB 0 1 1 1 1 1 0 –63dB 0 1 1 1 1 1 1 –64dB 1 0 0 0 0 0 0 –65dB 1 0 0 0 0 0 1 –66dB 1 0 0 0 0 1 0 –67dB 1 0 0 0 0 1 1 –68dB 1 0 0 0 1 0 0 –69dB 1 0 0 0 1 0 1 –70dB 1 0 0 0 1 1 0 –71dB 1 0 0 0 1 1 1 –72dB 1 0 0 1 0 0 0 –73dB 1 0 0 1 0 0 1 –74dB 1 0 0 1 0 1 0 –75dB 1 0 0 1 0 1 1 –76dB 1 0 0 1 1 0 0 –77dB 1 0 0 1 1 0 1 –78dB 1 0 0 1 1 1 0 –79dB 1 0 0 1 1 1 1 –80dB 1 0 1 0 0 0 0 –81dB 1 0 1 0 0 0 1 –82dB 1 0 1 0 0 1 0 –83dB 1 0 1 0 0 1 1 –84dB 1 0 1 0 1 0 0

Rev.1.0, May.31.2004, page 11 of 16 Lch D2b D3b D4b D5b D6b D7b D8b Rch D11b D12b D13b D14b D15b D16b D17b Cch D2c D3c D4c D5c D6c D7c D8c ATT SWch D11c D12c D13c D14c D15c D16c D17c SLch D2d D3d D4d D5d D6d D7d D8d SRch D11d D12d D13d D14d D15d D16d D17d –85dB 1 0 1 0 1 0 1 –86dB 1 0 1 0 1 1 0 –87dB 1 0 1 0 1 1 1 –88dB 1 0 1 1 0 0 0 –89dB 1 0 1 1 0 0 1 –90dB 1 0 1 1 0 1 0 –91dB 1 0 1 1 0 1 1 –92dB 1 0 1 1 1 0 0 –93dB 1 0 1 1 1 0 1 –94dB 1 0 1 1 1 1 0 –95dB 1 0 1 1 1 1 1 –96dB 1 1 0 0 0 0 0 –97dB 1 1 0 0 0 0 1 –98dB 1 1 0 0 0 1 0 –99dB 1 1 0 0 0 1 1 –∞ dB 1 1 1/0 1/0 1 1/0 1/0 Note: No guarantee except for these codes.

Electrical Characteristics

Unless otherwise noted, Ta = 25°C, AVCC = 7V, AVEE = –7V, DVDD = 5V, f = 1kHz, Volume = 0dB, Input Selector = IN1, Gain Control = 0dB, ADC Input ATT = 0dB, Tone = Bypass (1) Power supply characteristics Limits Parameter Symbol Min Typ Max Unit Test condition Analog positive power circuit current AIcc  32 42 mA With AVCC = 7V and AVEE = –7V 38pin current, when no signal is provided Analog negative power circuit current AIee –42 –32  mA With AVCC = 7V and AVEE = –7V 37pin current, when no signal is provided Digital power circuit current DIdd  2 3 mA With DVDD = 3.3V, 13pin current, when no signal is provided

Rev.1.0, May.31.2004, page 12 of 16 (2) Input/Output characteristics (OVER ALL) Limits Parameter Symbol Min Typ Max Unit Test condition Input resistance Rin 17 25 33 Ω 2 to 7, 26, 27 pin Maximum output voltage VOM 3.8 4.4 — Vrms 2 to 7pin input, 9 to 12,17,18pin output, THD = 1%, RL = 10kΩ , Output Gain Control = +6dB Pass gain Gv –2.0 0 2.0 dB 2 to 7,26,27 pin input, 9 to 12,17,18pin output, Vi = 0.3Vrms, FLAT THD1 — 0.002 0.008 2 to 7pin input, 9 to12, 17,18 pin output, BW: 400Hz to 30kHz, f = 1kHz, Vo = 0.3Vrms, RL=10k Ω Total harmonic distortion THD2  0.01 0.1 2 to 7pin input, 9 to 12, 17,18pin output, BW: 400Hz to 30kHz, f = 1kHz, Vo = 2Vrms, RL = 10k Ω Balance of mutual channels CBAL –0.5 0 0.5 dB 26,27pin input, 17,18pin output, Vi = 0.3Vrms  1 3 Output Gain Control = 0dB Vono1  5 15 JIS-A, Rg = 0Ω , 17,18pin output, Volume = –∞ dB setting Output Gain Control = +12dB  1.5 4.5 Output Gain Control = 0dB Vono2  7.2 22 JIS-A, Rg = 0Ω , 17,18pin output, Volume = 0dB setting Output Gain Control = +12dB  1 3 Output Gain Control = 0dB Output noise voltage Vono3  5 15 µVrms JIS-A, Rg = 0Ω , 9 to 12pin output, Volume = 0dB setting Output Gain Control = +12dB SS1 — –90 –70 < Input Selector> Vo = 1Vrms, Rg = 0Ω , RL = 10kΩ , JIS-A Selector separation SS2 — –90 –70 < Multi Input Selector > Vo = 1Vrms, Rg = 0Ω , RL = 10kΩ , JIS-A Channel separation CS — –90 –70 dB Vo = 1Vrms, Rg = 0Ω , RL = 10kΩ , JIS-A (3) 6 channel Volume characteristics Limits Parameter Symbol Min Typ Max Unit Test condition Maximum attenuation ATTmax — –100 –95 dB Vi = 2Vrms, JIS-A, VOL = – ∞ dB Volume gain gang error of mutual channels Dvol –0.5 0 +0.5 dB Volume = 0dB (4) Tone control characteristics Unless otherwise noted, Tone ON/OFF = ON Limits Parameter Symbol Min Typ Max Unit Test condition Tone control voltage gain (Boost/Bass) G (BASS) B +12 +14 +16 dB f = 100Hz Bass +14dB setting Tone control voltage gain (Cut/Bass) G (BASS) C –16 –14 –12 dB f = 100Hz Bass –14dB setting Tone control voltage gain (Boost/Treble) G (TRE) B +12 +14 +16 dB f = 10kHz Treble +14dB setting Tone control voltage gain (Cut/Treble) G (TRE) C –16 –14 –12 dB f = 10kHz Treble –10dB setting Balance of mutual channels BALT –2 0 +2 dB Bass setting +14, –14dB Treble setting +14, –14dB

Rev.1.0, May.31.2004, page 13 of 16 Tone Control (1) Bass C1 C2 R2R3 IN OUT < Boost > f0 = Q = Gv =

2 R1(R2+R3)C1C2

(R2+R3)R1C1C2 R1(C1+C2)+R3C1 20log R1(C1+C2)+(R2+R3)C1 R1(C1+C2)+R3C1 (Hz) (dB) R3R2 IN OUT < Cut > f0 = 1 (Hz) Q = Gv = (R2+R3)R1C1C2 R1(C1+C2)+R3C1 20log R1(C1+C2)+(R2+R3)C1 R1(C1+C2)+R3C1 (dB) 0.047 0.15 4.7K 0.15 0.047 4.7K π µµ + + π µ µ

Rev.1.0, May.31.2004, page 14 of 16 (2) Treble IN OUT RC IN OUT RC < Boost > <Cut > Gv = 20 log (dB) R42+RC2 (R4+R5) + RC Gv = 20 log (dB) (R4+R5) + RC +RC 0.022 0.022 µ µ Curve of characteristics Tone gain Gv (dB) Frequency f(Hz)

Rev.1.0, May.31.2004, page 15 of 16 Application Example 4LNI )1LCER( 2.2 2.2 2.2 2.2 2.2 2.2 2.2 ADC MCU DVDD 100 0.1 R 4.7 LIN RIN CIN SWIN SLIN SRIN C 4.7 AVEE -7V 100 0.1 4RNI )1RCER( 2.2 5LNI )2LCER( 2.2 INL1 2.2 INR1 2.2 3LNI 2.2 INR3 INR2 INL2 AVCC 100 0.1 5RNI )2RCER( 2.2 L 4.7 SW 4.7 SL4.7 SR4.7 1720 19 18 16 12 15 14 13 11 31 3532 33 34 36 40 37 38 39 2.2 2.2 2.2 Gain Control MCU I/F Cch Vol Gain Control Gain Control Gain Control Gain Control Rch Input ATT Input ATT Lch Lch Vol AVCCAVEE Bass /T r e Logic 25K SWch Vol 25K SLch Vol 25K SRch Vol 25K 50K Rch Vol 50K 50K 50K 50K 50K 50 K 50K 50K 50K DVDD 50K Bass /T r e Gain Control 50K 50K 50K 0.0470.15 4.7 K 4.7 K 0.047 0.15 0.022 0.022µ µ µ µ µ µµ µµ µµ µµ µ µ µ µ µ µ µ µ µ µ µ µ µµ µ µ µ µ µ µ µ ++- - + +-- +- +-

Rev.1.0, May.31.2004, page 16 of 16 Package Dimensions Package Code JEDEC JEITA Mass (reference value) FP-40B Conforms 0.2 g *Dimension including the plating thickness Base material dimension 9.0 ± 0.2 7.0 *0.25 ± 0.05 0.13 30 21 11 0 0.65 9.0 ± 0.2 0.10 0° – 8° 0.50 ± 0.10 *0.17 ± 0.05

1.70 Max

M 1.0 0.22 ± 0.04 1.40 + 0.09 – 0.050.13 0.15 ± 0.04 0.575 0.575 As of January, 2003 Unit: mm

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