M61532FP

M61532FP RENESAS | Alldatasheet

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Rev.1.0, Sep.19.2003, page 1 of 14 M61532FP 8ch Electronic Volume with 9 Input Selector REJ03F0041-0100Z Rev.1.0 Sep.19.2003 Feature FUNCTION FEATURE Electric Volume 8channel independent Electric Volume with High Voltage Transistor. (0~-99.0dB/0.5dBstep,-∞ dB) Twin Input Selector Front L/R channel has twin 9 Input Selector.(Main & Sub) Multi Channel Input Selector Every channel has 2 Input Selector and Input Gain Control Input Gain Control Input Gain Control (0/+6/+12/+18dB) REC Output 2 Lines REC Output (Both L and R channels) Output Gain Control Output Gain Control (0/+6/+12/+18dB) Output for ADC Built-in Single-end output (for ADC) Input ATT Input ATT (for ADC:0/-6/-12/-18dB) Application Receiver,AV Amp,Mini Stereo etc. Recommended Operating Condition Supply Voltage Range AVCC=7.0V(typ) , AVEE=-7.0V(typ) , DVDD=2.7~5.5V System Block Diagram MCU I/FCLOCK DATA Lout REC OUTL Rout SBLout GND Input ATT (for ADC) Output Gain Control Output Gain Control Output Gain Control Multi FRin Multi FLin REC OUTR Multi SBLin SBRout Output Gain Control Cout Output Gain Control SRout Output Gain Control Input ATT (for ADC) SUB OUTL Lch Rch SUB OUTR SLout Output Gain Control SWRout Output Gain Control Multi SBRin Multi Cin Multi SRin Multi SLin Multi SWin DVDD DGND ADOUTL ADOUTR LATCH AVCCAVEE

Rev.1.0, Sep.19.2003, page 2 of 14 Block Diagram and Pin Configuration (Top View) SBLVIN 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 414243444546474849505152535455565758596061626364 242322212019181716151413121110987654321 SBLSBRSWCSLSRRL SLVIN SLSELOUT SROUT SRVIN SRSELOUT LSELOUT LVIN LOUT ROUT RVIN RSELOUT SBRIN1 SBLIN1 SRIN1 SLIN1 CIN1 SWIN1 LIN1 RIN1 GND GND SUBOUTR SUBOUTL REC R1 REC L1 AVEE INR8 INL8 INR7 INL7 INR6 INL6 INR5 INL5 INR4 INL4 INR3 INL3 INR2 INL2 REC R2 REC L2 AROUT ALOUT RIN2 LIN2 SWIN2 CIN2 SLIN2 SRIN2 SBLIN2 SBRIN2 CVIN CSELOUT COUT SWOUT SWSELOUT SBRSELOUT SBRVIN SBROUT SBLOUT SBLSELOUT GND AVCC GND CLOCK DGND DVDD LATCH DATA MCU I/F SWVIN SLOUTINR9 INL9 INL1 INR1 GND GND GND

Rev.1.0, Sep.19.2003, page 3 of 14 Pin Description PIN No. Name Function 2,80,78,76,74,72,70,68,66, INL1,2,3,4,5,6,7,8,9 Input pin of L channel (Input Selector) 1,79,77,75,73,71,69,67,65 INR1,2,3,4,5,6,7,8,9 Input pin of R channel (Input Selector) 3,8,23,25,50,59,64 GND1,2,3,4,5,6,7, Analog Ground 63,4,62,5 REC L1/L2/R1/R2 Output pin of REC L/R

6 ALOUT Output pin of L channel for ADC(Single ended)

7 AROUT Output pin of R channel for ADC(Single ended)

9 RIN2 Input pin of R channel

10 LIN2 Input pin of L channel

11 SWIN2 Input pin of SW channel

12 CIN2 Input pin of C channel

13 SLIN2 Input pin of SL channel

14 SRIN2 Input pin of SR channel

15 SBLIN2 Input pin of SBL channel

16 SBRIN2 Input pin of SBR channel

17 DGND Ground of internal logic circuit

18 DATA Input pin of Control Data

19 LATCH Input pin of Control Trigger

20 CLOCK Input pin of Control Clock

21 DVDD Power supply to internal logic circuit

22 AVCC Positive power supply to internal analog circuit

24 AVEE Negative power supply to internal analog circuit

26 SBLSELOUT Output pin of SBL channel volume input selector

27 SBLVIN Input pin of SBL channel volume

28 SBLOUT Output pin of SBL channel

29 SBROUT Output pin of SBR channel

30 SBRVIN Input pin of SBR channel volume

31 SBRSELOUT Output pin of SBR channel volume input selector

32 SWSELOUT Output pin of SW channel volume input selector

33 SWVIN Input pin of SW channel volume

34 SWOUT Output pin of SW channel

35 COUT Output pin of C channel

36 CVIN Input pin of C channel volume

37 CSELOUT Output pin of C channel volume input selector

38 SLSELOUT Output pin of SL channel volume input selector

39 SLVIN Input pin of SL channel volume

40 SLOUT Output pin of SL channel

41 SROUT Output pin of SR channel

42 SRVIN Input pin of SR channel volume

43 SRSELOUT Output pin of SR channel volume input selector

44 LSELOUT Output pin of L channel volume input selector

45 LVIN Input pin of L channel volume

46 LOUT Output pin of L channel

47 ROUT Output pin of R channel

48 RVIN Input pin of R channel volume

49 RSELOUT Output pin of R channel volume input selector

51 SBRIN1 Input pin of SBR channel

52 SBLIN1 Input pin of SBL channel

53 SRIN1 Input pin of SR channel

54 SLIN1 Input pin of SL channel

55 CIN1 Input pin of C channel

56 SWIN1 Input pin of SW channel

57 LIN1 Input pin of L channel

58 RIN1 Input pin of R channel

60 SUBOUTR Sub Output pin of R channel

61 SUBOUTL Sub Output pin of L channel

Rev.1.0, Sep.19.2003, page 4 of 14 Absolute Maximum Ratings Symbol Parameter Condition Ratings Unit Supply voltage AVCC-AVEE ±8.0 Power supply DVDD-GND 6.0 V Pd Power dissipation Ta ≤25°C 1250 mW Kθ Thermal derating Ta>25 °C 12.5 mW/ °C Topr Operating temperature -20~+55 °C Tstg Storage temperature -40~+125 °C 0.5 1.0 1.5 0 25 50 75 100 125 150 THERMAL DERATINGS (MAXIMUM RATING) POWER DISSIPATION pd (W) AMBIENT TEMPERATURE Ta ( C)

Rev.1.0, Sep.19.2003, page 5 of 14 Recommended Operating Conditions (Ta=25°C, unless otherwise noted) Parameter Symbol Condition MIN TYP MAX Unit Analog supply voltage (Positive) AVCC 4.5 7.0 7.5 V Analog supply voltage (Negative) Digital supply voltage DVDD 2.7 3.3 5.5 V Logic “H ” level input voltage VIH DGND reference DVDD x 0.7  DVDD V Logic “L” level input voltage VIL DGND reference DGND  DVDD x 0.2 V Note:VEE≤DGND ≤VDD ≤VCC Relationship Between Data and Clock D0 D1 D21 D22 D23 D0 LATCH SIGNALH L H L H L DATA CLOCK LATCH DATA signal is read at the rising edge of CLOCK. Serial data (D0 – D23) is loaded at the rising edge of the LATCH signal.

Rev.1.0, Sep.19.2003, page 6 of 14 Clock and Data Timings CLOCK DATA 25% 75% tr tf tcr tWHC tWLC tSD tHD LATCH tSL tr tf 25% 75% 25% 75% tr tWHC tf tSC 25% Timing Definition of Digital Block Limits Symbol Parameter Min typ Max Unit tcr Clock cycle time 4   tWHC Clock pulse width (“H” level) 1.6   tWLC Clock pulse width (“L” level) 1.6   tr Rising time of clock,data and latch   0.4 tf Falling time of clock,data and latch   0.4 tSD Data setup time 0.8   tHD Data hold time 0.8   tSL Latch setup time 1   tWHL Latch pulse width 1.6   tSC Clock setup time 4   µsec

Rev.1.0, Sep.19.2003, page 7 of 14 Data Control Specification Initialize all data of the 5 formats when Digital Power supply (DVDD) turn on. D23 D23 D23 D23 D23 D22 D22 D22 D22 D22 D21 D21 D21 D21 D21 D20a D20b D20c D20c D20c D19a All ch Output Mute D19b D19c D19c D19c D18a D18b D18c D18c D18c D17a D17b D17c D17c D17c D16a D16b D16c D16c D16c D15a D15b D15c D15c D15c D14a FL/FR VOL Control D14b D14c D14c D14c D13a Multi Input MuteD13b D13c D13c D13c D12a Multi Input Selector D12b D12c D12c D12c D11a REC Output D11b D11c D11c D11c D10a REC Output D10b D10c D10c D10c D9a D9b D9c D9c D9c D8a D8b D8c D8c D8c D7a D7b D7c D7c D7c D6a D6b D6c D6c D6c D5a D5b D5c D5c D5c D4a D4b D4c D4c D4c D3a D3b D3c D3c D3c D2a D2b D2c D2c D2c D1a D1b D1c D1c D1c D0a D0b D0c D0c D0c Input Selector (Main) SBRch VolumeSBLch Volume FRch Volume SWch VolumeCch Volume SRch VolumeSLch Volume FLch Volume Input ATTInput Selector (Sub) Output Gain Control Input Gain Control

Rev.1.0, Sep.19.2003, page 8 of 14 Setting Code (1) Input Selector (4) Multi Input Main D0a D1a D2a D3a D12a Sub D4a D5a D6a D7a 0 0000 1 0001 0 0 1 0 (5) Multi Input Mute (Except For FL/FR) 0 0 1 1 D13a 0100 0101 0110 1 0111 1 0 0 0 (6) FL/FR VOL Input 1 0 0 1 D14a (2) Input ATT 1 D8a D9a 0 0 (7) Input Gain Control 0 1 D15a D16a 10 00 11 01 (3) REC Output 1 1 REC1 REC2 D10a D11a (8) Output Gain Control 0 0 D17a D18a 11 00 (9) All Ch Output Mute D19a It's initial setting when power is turned on. +6dB Setting Mute off Mute on Setting 0dB +6dB +12dB +18dB +12dB Mute OFF Mute ON Setting 0dB Multi Input Setting Bypass IN7 IN9 -12dB ON -18dB REC Output Setting OFF IN8 Setting ALL OFF IN1 IN2 Setting Setting Multi In1 Multi In2 +18dB depend on (4) Multi Input0 IN3 IN4 IN5 IN6 Setting 0dB -6dB

Rev.1.0, Sep.19.2003, page 9 of 14 (9)6 channel Volume FLch D0b D1b D2b D3b D4b D5b D6b D7b FRch D8b D9b D10b D11b D12b D13b D14b D15b Cch D0c D1c D2c D3c D4c D5c D6c D7c SWch D8c D9c D10c D11c D12c D13c D14c D15c SLch D0d D1d D2d D3d D4d D5d D6d D7d SRch D8d D9d D10d D11d D12d D13d D14d D15d SBLch D0e D1e D2e D3e D4e D5e D6e D7e SBRch D8e D9e D10e D11e D12e D13e D14e D15e - 0 . 0 d B00000000 - 0 . 5 d B00000001 - 1 . 0 d B00000010 - 1 . 5 d B00000011 - 2 . 0 d B00000100 - 2 . 5 d B00000101 - 3 . 0 d B00000110 - 3 . 5 d B00000111 - 4 . 0 d B00001000 - 4 . 5 d B00001001 - 5 . 0 d B00001010 -5 . 5 d B 0 0 0 0 1 0 1 1 - 6 . 0 d B00001100 - 5 0 . 0 d B01100100 - 5 0 . 5 d B01100101 - 5 1 . 0 d B01100110 - 5 1 . 5 d B01100111 - 5 2 . 0 d B01101000 - 9 5 . 0 d B10111110 - 9 5 . 5 d B10111111 - 9 6 . 0 d B11000000 - 9 6 . 5 d B11000001 - 9 7 . 0 d B11000010 - 9 7 . 5 d B11000011 - 9 8 . 0 d B11000100 - 9 8 . 5 d B11000101 - 9 9 . 0 d B11000110 - ∞ d B11111111 It's initial setting when power is turned on. ATT

Rev.1.0, Sep.19.2003, page 10 of 14

Electrical Characteristics

Unless otherwise noted, Ta=25°C,AVCC=7V,AVEE=-7V,DVDD=3.3V,f=1kHz, Volume=0dB, Input Selector=IN1,Input ATT=0dB,Input Gain Control=0dB,Output Gain Control=0dB, L/R Volume Input=Bypass,Multi Input Selector=Multi IN1 setting (1) Power supply characteristics Limits Parameter Symbol Test condition min typ max Unit Analog positive power circuit current AIcc With AVCC=7V and AVEE=-7V Pin22 pin current, when no signal is provided  50 70 mA Analog negative power Circuit current AIee With AVCC=7V and AVEE=-7V Pin24 pin current, when no signal is provided -70 -50  mA Digital power circuit current Dldd With DVDD=3.3V, Pin21 pin current, when no signal is provided  3 6 mA (2) Input/Output characteristics (OVER ALL) Limits Parameter Symbol Test Condition min typ max Unit Input resistance Rin 65-80pin when each selector chooses a terminal concerned 35 47 65 kΩ Maximum output voltage VOM (1,2,51,5253,54,55,56) pin input, THD=1%, RL=10k Ω Output Gain Control =+12dB setting 3.6 4.2  Vrms Pass gain Gv (1,2,51,5253,54,55,56) pin input, Vi=0.3Vrms,FLAT -2.0 0 2.0 dB THD1 (1,2,51,5253,54,55,56) pin input, BW:400Hz~30kHz f=1kHz , Vo=0.3Vrms , RL=10kΩ  0.00 0.05 % Distortion THD2 (1,2,51,5253,54,55,56) pin input, BW:400Hz~30kHz f=1kHz , Vo=2Vrms , RL=10kΩ  0.03 0.1 % Channels balance CBAL (1,2)pin input,(47,46)pin output, Vi=0.3Vrms , JIS-A -0.5 0 0.5 dB Output Gain Control=0dB  1.5 6 µVrms Vono (VOL =-∞ dB) Rg=0 Ω , output, Volume=-∞ dB setting Output Gain Control=+12dB  9 20 µVrms Output Gain Control=0dB  2.5 8 µVrms Vono (VOL=0dB) JIS-A , (1,2)pin : Rg=0 Ω , (47,46)pin output, Volume=0dB setting Output Gain Control=+12dB  12 25 µVrms Output noise voltage Vonodac (dac out) JIS-A , (1,2)pin:Rg=0Ω (5.4)pin output  3 9 µVrms

Rev.1.0, Sep.19.2003, page 11 of 14 Limits Parameter Symbol Test Condition min typ max Unit CS1 <Input selector> (47,46)pin output, Vo=1Vrms , Rg=0Ω , RL=10kΩ , JIS-A  -90 -70 dB Input/Multi selector channel separation CS2 <Multi channel selector> Vo=1Vrms , Rg=0Ω , RL=10kΩ , JIS-A, FL/FR VOL Input=Multi input  -90 -70 dB CT1 (L/R) (1,2) pin input, (47,46) pin output, Vo=1Vrms , Rg=0Ω , RL=10kΩ , JIS-A  -90 -70 dB Cross talk between channels CT2 (Multi Input) Vo=1Vrms , Rg=0Ω , RL=10kΩ , JIS-A, L/R VOL Input=Multi input  -90 -70 dB (3) 8 channel Volume characteristics Limits Parameter Symbol Test condition min typ max Unit Maximum attenuation ATTmax (47,46,29,28,41,40,35,34) pin output, Vi=2Vrms,JIS-A,VOL=-∞  -100 -95 dB Volume gain Between channels Dvol (47,46,29,28,41,40,35,34) pin output, Volume=0dB setting -0.5 0 +0.5 dB

Rev.1.0, Sep.19.2003, page 12 of 14 Internal Block Diagram 30 36 DVDD +5.0V AVCC +7V DGND AVEE -7V Input ATT 0/-6/-12/-18dB Input Selector (Main) INL1 47k80INL2 47k78INL3 47k76INL4 47k74INL5 47k72INL6 47k70INL7 47k68 61 4 47k 47k Input Selector (Sub) 60 5 47k 62 47k Input ATT 0/-6/-12/-18dB INL8 66 47k 47k2 Input Selector (Main) INR1 47k79INR2 47k77INR3 47k75INR4 47k73INR5 47k71INR6 47k69INR7 47k67 Input Selector (Sub) INR8 65 47k 47k1 57LIN1 LOUT Input Gain Control 0/+6/+12/+18dB47k 44 45 46Lch VOL Output Gain Control0~-99dB,mute 10LIN2 47k 58RIN1 ROUT Input Gain Control 0/+6/+12/+18dB47k 49 48 47Rch VOL Output Gain Control0~-99dB,mute 9RIN2 47k SLIN1 SLIN2 SLOUT Input Gain Control 0/+6/+12/+18dB 47k 38 39 40SLch VOL Output Gain Control0~-99dB,mute 13 47k SRIN1 SRIN2 SROUT Input Gain Control 0/+6/+12/+18dB 47k 43 42 41SRch VOL Output Gain Control0~-99dB,mute 14 47k CIN1 CIN2 COUT Input Gain Control 0/+6/+12/+18dB 47k 37 36 35Cch VOL Output Gain Control0~-99dB,mute 12 47k SWIN1 SWIN2 SWOUT Input Gain Control 0/+6/+12/+18dB 47k 32 33 34SWch VOL Output Gain Control0~-99dB,mute 11 47k SBLIN1 SBLIN2 SBLOUT Input Gain Control 0/+6/+12/+18dB 47k 26 27 28SBLch VOL Output Gain Control0~-99dB,mute 15 47k SBRIN1 SBRIN2 SBROUT Input Gain Control 0/+6/+12/+18dB 47k 31 30 29SBRch VOL Output Gain Control0~-99dB,mute 16 47k INL9 INR9

Rev.1.0, Sep.19.2003, page 13 of 14 Application Example SBLVIN SLVIN SLSELOUT SROUT SRVIN SRSELOUT LSELOUT LVIN LOUT ROUT RVIN RSELOUT SBRIN1 SBLIN1 SRIN1 SLIN1 CIN1 SWIN1 LIN1 RIN1 GND GND SUBOUTR SUBOUTL REC R1 REC L1 AVEE INR8 INL8 INR7 INL7 INR6 INL6 INR5 INL5 INR4 INL4 INR3 INL3 INR2 INL2 REC R2 REC L2 AROUT ALOUT RIN2 LIN2 SWIN2 CIN2 SLIN2 SRIN2 SBLIN2 SBRIN2 CVIN CSELOUT COUT SWOUT SWSELOUT SBRSELOUT SBRVIN SBROUT SBLOUT SBLSELOUT AVCC GND CLOCK DGND DVDD LATCH DATA M C U + 2.2u + 2.2u + 2.2u + 2.2u + 2.2u + 2.2u + 2.2u + 2.2u 4.7u +4.7u 4.7u +4.7u 4.7u 4.7u 2.2u 2.2u 2.2u 2.2u 2.2u 2.2u 2.2u 2.2u 4.7u 4.7u SLOUT SLOUT 4.7u4.7u 4.7u 4.7u SLOUT 4.7u 4.7u 4.7u 4.7u 4.7u 4.7u 4.7u 4.7u 4.7u 4.7u SWVIN SLOUTINR9 INL9 INL1 INR1 2.2u 2.2u 4.7u 4.7u 0.1u100u 0.1u100u +100u 0.1u GND GND GND GND 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 414243444546474849505152535455565758596061626364 242322212019181716151413121110987654321 SBLSBRSWCSLSRRL MCU I/F

Rev.1.0, Sep.19.2003, page 14 of 14 Package Dimensions QFP80-P-1420-0.80 1.58 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 80P6N-A Plastic 80pin 14✕ 20mm body QFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.5 ——I2 1.3 ——M D 14.6 ——M E 20.6 10˚0˚ 0.1 1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.8 20.220.019.8 14.214.013.8 0.20.150.13 0.450.350.3 2.8 3.05 ee e E c HE 80 65 H D D M D ME A F A1A2 L y Recommended Mount Pa d Detail F x —— 0.2 b x M MMP

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