M61530FP

M61530FP RENESAS | Alldatasheet

Document overview

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Technical content

Features

Main volume control 0 to −87 dB in 1-dB steps, −∞ Four independently controlled volumes (SL, SR, C, LFE) Low pass filter (LPF) On-chip operational amplifiers for configuration of post-filters through the addition of external C and R elements AGC AGC circuit is included to prevent clipping <SW ch> Bass boost HPF type, with on/off switch <SL/SR ch> Output gain control 0, +6, +9, or +12 dB (four steps) <SW ch> Input gain control 0, +5, +10 dB (three steps) <FL/FR ch> Microcomputer I/F Two-line serial data control Application Mini-component systems, micro-component systems, etc. Recommended Operating Conditions Power-supply voltage range: Vcc = 8 to 10 V Rated power-supply voltage: Vcc = 9 V

Rev.1.0, Sep.19.2003, page 2 of 18 System Block Diagram L-LPF R-LPF FL-LPF FR-LPF SL-LPF SR -LPF C-LPF SW -LPFAGC 0,+5,+10dB 0,+5,+10dB +6dB +6dB +6dB SLchVOL SR chVOL Cch VOL LFEchVOL 0,+6, +9, +12dB VOL VOL LIN RIN LOUT ROUT SLOUT SROUT COUT SWOUT FLIN FRIN SLIN SRIN CIN LFEIN SWIN SL_EXTIN SR _EXTIN M6151 9FPM61530FP Bass booster Bass booster Tone Tone Surround or DPL buffer Input selector Input selector Bass booster Bass booster

Rev.1.0, Sep.19.2003, page 3 of 18 Block diagram with pin connections FR_LPFOUT FR_LPFIN SL_EXTIN SL_VOLIN SL_LPFOUT SL_LPFIN SR _EXTIN SR _VOLIN SR _LPFOUT SR _LPFIN C_VOLIN C_LPFOUT C_LPFIN LFE_VOLIN SW_IN VCC DATA CLOCK FL_LPFOUT FL_LPFIN R_LPFIN R_LPFOUT L_LPFOUT L_LPFIN REFIN REFOUT FL_OUT FR_IN FR_OUT SL_BB1 SL_BB2 SL_OUT SR _BB1 SR _BB2 SR _OUT C_OU T GND TEST AGC SW_OUT SW_LPFIN SW_LPF OUT 0 to-87dB,- ∞ 0 to -87dB,-∞ 0 to -87dB ,-∞ 0 to -87dB,-∞ AGC Microcomputer I/F Lch LPF amp Rch LPF amp FLch LPF ampFRch LPF amp FR input gain control 0,+5,+10dB FL input gain control 0,+5,+10dB SW output-gain control 0,+6,+9,+12dB SLch LPF amp SRch LPF amp Cch LPF amp SL ch volume SRch volume Cch volume LFEch volume +6dB +6dB +6dB FL output SW FR output SW ON OFF SRVOL input SW SLVOLXY input SW LFEMIX SW SW MIX SW ON/OFF ON/OFF VREF amp SWch LPF amp Bass booster Bass booster Bass booster Bass booster

Rev.1.0, Sep.19.2003, page 4 of 18 Pin description Pin No. Pin Name Description

1 FR_LPFOUT

2 FR_LPFIN

Configure a low-pass filter by adding external C and R elements to the input of the FR channel

3 SL_EXTIN SL channel external input pin

4 SL_VOLIN SL channel volume input pin

5 SL_LPFOUT

6 SL_LPFIN

Configure a low-pass filter by adding external C and R elements to the input of the SL channel

7 SR_EXTIN SR channel external input pin

8 SR_VOLIN SR channel volume input pin

9 SR_LPFOUT

10 SR_LPFIN

Configure a low-pass filter by adding external C and R elements to the input of SR channel

11 C_VOLIN C channel volume input pin

12 C_LPFOUT

13 C_LPFIN

Configure a low-pass filter by adding external C and R elements to the input of the C channel

14 LFE_VOLIN LFE channel volume input pin

15 SW_IN SW channel input pin

16 VCC Power-supply pin for internal analog and digital circuitry (VCC = 9 V)

17 DATA DATA input pin for serial data transfer

18 CLOCK CLOCK input pin for serial data transfer

19 GND GND pin for internal analog and digital circuitry

20 TEST Pin for setting the test mode (normally fixed low)

21 AGC C connection pin for setting attack/recovery time for AGC

22 SW_LPFOUT

23 SW_LPFIN

Configure a low-pass filter by adding external C and R elements to the input of the SW channel

24 SW_OUT SW channel output pin

25 C_OUT C channel output pin

26 SR_OUT SR channel output pin

27 SR_BB2

28 SR_BB1

Pin for connecting external components that set bass-boost frequency characteristics for the SR channel

29 SL_OUT SL channel output pin

30 SL_BB2

31 SL_BB1

Pin for connecting external components that set bass-boost frequency characteristics for the SL channel

32 FR_OUT FR channel output pin

33 FR_IN Pin for interfacing with the M61519FP surround circuit

34 FL_OUT FL channel output pin

35 REFOUT Internal reference output pin

36 REFIN Internal reference input pin

37 L_LPFI N

38 L_LPFOUT

Configure a low-pass filter by adding external C and R elements to the input of the L channel

39 R_LPFOUT

40 R_LPFIN

Configure a low-pass filter by adding external C and R elements to the input of the R channel

41 FL_LPFIN

42 FL_LPFOUT

Configure a low-pass filter by adding external C and R elements to the input the of FL channel

Rev.1.0, Sep.19.2003, page 5 of 18 Absolute Maximum Ratings Parameter Symbol Ratings Unit Conditions Power-supply voltage VCC 10.5 V Internal power dissipation Pd 850 mW Ta ≤25°C Thermal reduction rate K θ 8.6 mW/°C Ta>25°C Ambient operating temperature Topr -20 to +75 °C Storage temperature Tstg -40 to +125 °C 0.5 1.0 0. 75 150125100755025 0.25 0.42 0.85W Thermal derating curve Internal power dissipation pd [W] Ambient temperature Ta [°C] Recommended Operating Condition (Unless otherwise noted, Ta = 25°C) Limits Item Symbol Min. Typ. Max. Unit Condition Power-supply voltage VCC 8 9 10 V Logical high level input voltage VIH 2.2  5.5 V VCC=9V Logical low level input voltage VIL 0  0.6 V VCC=9V

Rev.1.0, Sep.19.2003, page 6 of 18 Relation between DATA and CLOCK The data signal is read on the rising edges of the CLOCK signal D0 D1 D2 D3 D13 D14 D1 5 Latch condition CLOCK DATA 1. Data transmission The DATA signal is read on the rising edges of the CLOCK signal. The DATA line must always be low on the falling edge of the CLOCK signal during transmission of the DATA signal. 2. Data Latch Data for this IC is in 16-bits (D0 to D15) words. Latch the transmitted data by driving the DATA line high on the falling edge of the CLOCK signal after the transmission of D15. The DATA line is driven high to latch D0 to D15 at this time CLOCK and DATA timing tWHC tcr 25% 75% DATA CLOCK (D15) L ATCH signal tWLC tftr tH LD tS H D tH HD tS LD tH LD (D0 to D15) tS LD

Rev.1.0, Sep.19.2003, page 7 of 18 Digital module timing Limits Item Symbol Min. Typ. Max. Unit Clock: Cycle time tcr 4   µS Clock: Pulse width (high) tWHC 1.6   Clock: Pulse width (low) tWLC 1.6   Clock: Rising time tr   0.4 Clock: Falling time tf   0.4 Data: Setup time (high), clock rising tSHD 0.8   Data: Setup time (low), clock falling tSLD 0.8   Data: Hold time (high) tHHD 0.8   Data: Hold time (low) tHLD 0.8  

Rev.1.0, Sep.19.2003, page 8 of 18 Data input format (Set all data shown below to the initial values every time power is turned on.) (1) D0a D1a D2a D3a D4a D5a D6a D7a D8a D9a D10a D11a D12a D13a D14 D15 (8) SLch trim potentiometer (8) SRch trim potentiometer (1) FL/FR input gain control (2) FL/FR output SW (3) Input SW for SL/SR volume (4) LFEMIX SW (5) SWMIX SW (2) D0b D1b D2b D3b D4b D5b D6b D7b D8b D9b D10b D11b D12b D13b D14 D15 (8) Cch trim potentiometer (8) LFEch trim volume (6) Bass boost (7) SW output gain control (3) D0c D1c D2c D3c D4c D5c D6c D7c D8c D9c D10c D11c D12c D13c D14 D15 (9) SLch master volume (9) SRch master volume (4) D0d D1d D2d D3d D4d D5d D6d D7d D8d D9d D10d D11d D12d D13d D14 D15 (9) Cch master volume (9) LFEch master volume Code settings : Initial setting (1) FL/FR input gain control (3) Input switch for SL/SR volume (5) SW MIX SW (6) Bass boost Setting D8a D9a Setting D11a Setting D13a Setting D8b 0dB 0 0 SL/SRch input 0 ON 0 OFF 0 +5dB 0 1 External input 1 OFF 1 ON 1 +10dB 1 0 (2) FL/FR output SW (4) LFE MIX SW (7) SW output gain control Setting D10a Setting D12a Setting D9b D10b ON 0 ON 0 0dB 0 0 OFF 1 OFF 1 +6dB 0 1 +9dB 1 0 +12dB 1 1 Note: Do not use data codes other than those specified above.

Rev.1.0, Sep.19.2003, page 9 of 18 (8) SL/SR/C/LFEch trim volume (9) SL/SR/C/LFEch master volume SLch D0a D1a D2a D3a SLch D0c D1c D2c D3c D4c SRch D4a D5a D6a D7a SRch D5c D6c D7c D8c D9c Cch D0b D1b D2b D3b Cch D0d D1d D2d D3d D4d Attenu ation LFEch D4b D5b D6b D7b Attenu ation LFEch D5d D6d D7d D8d D9d 0dB 0 0 0 0 0dB 0 0 0 0 0 -1dB 0 0 0 1 -2dB 0 0 0 0 1 -2dB 0 0 1 0 -4dB 0 0 0 1 0 -3dB 0 0 1 1 -6dB 0 0 0 1 1 -4dB 0 1 0 0 -8dB 0 0 1 0 0 -5dB 0 1 0 1 -10dB 0 0 1 0 1 -6dB 0 1 1 0 -12dB 0 0 1 1 0 -7dB 0 1 1 1 -14dB 0 0 1 1 1 -8dB 1 0 0 0 -16dB 0 1 0 0 0 -9dB 1 0 0 1 -18dB 0 1 0 0 1 -10dB 1 0 1 0 -20dB 0 1 0 1 0 -11dB 1 0 1 1 -22dB 0 1 0 1 1 -12dB 1 1 0 0 -24dB 0 1 1 0 0 -13dB 1 1 0 1 -26dB 0 1 1 0 1 -14dB 1 1 1 0 -28dB 0 1 1 1 0 -15dB 1 1 1 1 -30dB 0 1 1 1 1 -32dB 1 0 0 0 0 -34dB 1 0 0 0 1 -36dB 1 0 0 1 0 -38dB 1 0 0 1 1 -40dB 1 0 1 0 0 -42dB 1 0 1 0 1 -44dB 1 0 1 1 0 -48dB 1 0 1 1 1 -52dB 1 1 0 0 0 -56dB 1 1 0 0 1 -60dB 1 1 0 1 0 -64dB 1 1 0 1 1 -68dB 1 1 1 0 0 -72dB 1 1 1 0 1 -76dB 1 1 1 1 0 -∞ dB 1 1 1 1 1 Note: When the sum of the trim potentiometer and master volume settings is –87 dB or less, the overall level is –87 dB (e.g. when the trim potentiometer is –15 dB and master volume is -76 dB, the total level becomes -87 dB). Note: Do not use data codes other than those specified above.

Rev.1.0, Sep.19.2003, page 10 of 18

Electrical characteristics

Unless otherwise noted, Ta = 25°C, Vcc = 9 V, f = 1 kHz, input gain control = 0 dB, bass boost = off, trim/master volume = 0 dB, FL/FR output SW = on, SL/SR VOL input SW = SL/SR input, LFE MIXS SW = on, SW MIX= off, output gain control = 0 dB Limits Item Symbol Min. Typ. Max. Unit Condition Power supply Circuit current IACC  14 25 mA When no signal is detected, current flows to pin 16 I/O Max. input voltage VIM1 1.6 2.0  Vrms Pins 2, 37, 40, and 41: Input, pins 1, 38, 39, and 42: Output, RL = 10 kΩ , THD = 1% VIM2 0.8 1.0  Vrms Pins 6, 10, and 13: Input, pins 5, 9, and 12: Output, RL = 10 kΩ , THD = 1% VIM3 1.6 2.0  Vrms Pin 14: Input, pin 22: Output, RL = 10 kΩ , THD = 5%, f = 100 kHz Absolute max. input voltage AVIM   2.0 Note Vrms Pins 3, 7, 14, and 15: Input Max. output voltage VOM1 1.8 2.4  Vrms Pins 6 and 10: Input, pins 29 and 26: Output, RL = 10 kΩ , THD = 5%, bass boost = on, f = 100 Hz VOM2 1.6 2.0  Vrms Pin 13: Input, pin 25: Output, RL = 10 kΩ , THD = 5% VOM3 1.4 1.8  Vrms Gain between pins 14 and 22, Vi = 0.5 Vrms, FLAT, f = 100 Hz Bypass gain GV1 +2.3 +4.3 +6.3 dB Gain from pins 6 to 29, pin 10 to 26, and pins 13 to 25, Vi =

0.5 Vrms, FLAT

GV2 -2 0 +2 dB Gain from pins 2 to 32 and 41 to 34, Vi = 0.5 Vrms, FLAT GV3 -2 0 +2 dB Gain from pin 14 to 22, Vi = 0.5 Vrms, FLAT, f = 100 Hz Vno1  6.0 12.0 µVrms  Output noise voltage  2.5 8.0 µVrms DIN-Audio, when no signal is present, Rg = 0 for pins 6 and 10, pins 29 and 26 are outputs SL/SR ch volume = -∞ dB Vno2  6.0 10.0 µVrms C ch volume = 0 dB  2.0 4.0 µVrms DIN-Audio, when no signal is present, Rg = 0 for pin 13, pin 25 is an output C ch volume = -∞ dB Vno3  6.5 16.0 µVrms LFE ch volume = 0 dB  6.5 16.0 µVrms DIN-Audio, when no signal is detected, Rg = 0 for pin 14, pin 22 is an output, SW ch LPF: fc=300 Hz LFE ch volume = -∞ dB THD1  0.003 0.2 % Pins 6 and 10: input, pins 29 and 26: output, bandwidth: 400 Hz to 30 kHz, Vo = 0.5 Vrms, RL = 10 kΩ Total harmonic distortion rate THD2  0.003 0.1 % Pin 13: input, pin 25: output, bandwith: 400 Hz to 30 kHz, Vo = 0.5 Vrms, RL = 10 kΩ THD3  0.008 0.2 % Pin 14: input, pin 22: output, 30-kHz low-pass filter, Vo =

0.5 Vrms, RL = 10 kΩ , output gain control = 0 dB, when

AGC is not operating, f = 100 Hz THD4  2  % Pin 14: input, pin 22: output, 30-kHz low-pass filter, RL = 10 kΩ , Vi = 700 mVrms, f = 100 Hz, when AGC is operating, output gain control = + 12 dB Volume max. attenuation ATT  -100 -87 dB Vo = 1 Vrms, pins 22, 25, 26, and 29 are outputs, JIS-A, volume = -∞

Rev.1.0, Sep.19.2003, page 11 of 18 Limits Item Symbol Min. Typ. Max. Unit Condition I/O Max. gain GVM1 +8 +10 +12 dB Gain from pin 2 to 32 and 41 to 34, Vi = 0.1 Vrms, FLAT, input gain control = + 10 dB GVM2 +10 +12 +14 dB Gain between pins 14 and 22, f = 100 Hz Vi = 0.1 Vrms, FLAT, output gain control = + 12 dB Crosstalk between channels CT  -90 -55 dB Gain from pins 6 to 29, pins 10 to 26, pins 13 to 25, and pins 14 to 22, Vi = 0.5 Vrms, JIS-A, RL = 47 kΩ , Rg = 0 Ω , input on a channel other than the measurement target AGC Attack time TAGCAT  40  ms Pin 14: input, pin 22: output, RL = 10 kΩ , output gain control = +12 dB Recovery time TAGCRE  850  ms Pin 14: input, pin 22: output, RL = 10 kΩ , output gain control = +12 dB Note: The voltage on pins 3, 7, 14, and 15 must not exceed the the absolute maximum input-voltage range (2 Vrms).

Rev.1.0, Sep.19.2003, page 12 of 18 System block diagram M61530FP + M61519FP application example 0, +5,+10dB 0, +5,+10dB 0, +6,+9,+12dB AGC 17 18 36 35 19 16 REFLOGIC M61519FP MIC IN RE CB1 RE CB2 RE CA1/INex1RE CA2/INex2 4-ch input selector + mute 4-ch input selector + mute MIC SW RE CA SW Pre-tone-control attenuator Tone control (bass/mid/treble) Tone control (bass/mid/treble) Pre-tone control attenuator Spectrum analyzer Bypass Bypass Master volume Bass booster Bass booster Master volume MD TAPE TUNER CD DVD Surround PL Buff M61530FP SWch OUT Cch OUT Rch Lch SRch OUT SLch OUT DATA CLOCK 0 to -87dB,-∞ 0 to -87dB,-∞ 0 to -87dB,-∞ 0 to -87dB,-∞ SW-IN Cch S-Rch S-Lch FRch FLch MIC IN LFEch LchRch +6dB +6dB +6dB SLchVOL SRchVOL CchVOL LFEchVOL LFEMIX SW SWMIX SW FL output SW FR output SW SLVOL input SW SRVOL input SW LPF fc =300Hz TEST max:2Vrms M61519FP Max. output voltage 2Vrms Vocal cut Bass booster Bass booster SW ch output noise (values for reference) (DIN-Audio) Output gain 0dB : 8 µ µ µ Vrms +6dB : 15 Vrms +12dB: 30 Vrm s Note: In the above application, the voltage input to pin 14 (LFE ch) must not exceed the absolute maximum input voltage (2 Vrms).

Rev.1.0, Sep.19.2003, page 13 of 18 Functional description (1) Equivalent circuit of the bass-boost circuit Output 0dB Q=4 (G=10dB) Input K=1R2 C2C1 VO VIN Note: Resistor R2 is within the IC. (R2 214kΩ ± 30%) fo = 2 π R1R2C1C2

1 Hz Q = R1(C1+C2)+(1-K)R2C2

Amplitude characteristics of the second-order high-pass filter (reference) Q G0 1 0 to1dB 2 6dB 4 10dB 5 13dB 10 20dB

Rev.1.0, Sep.19.2003, page 14 of 18 Bass-boost characteristic curve R1 =680Ω ,R 2 = 2 1 4 kΩ ,C 1 = C 2 = 0 . 2 2 Fµ (f0 60Hz,Q 8.9) (2) AGC circuit -26dB Waveform detector circuit LFEch S When C for setting the times = 1.0 µF, attack time = 40 ms, and recovery time = 850 ms W ch MAX 2Vrms MAX 2Vrms L volume FEch SW ch output gain control +26 dB (total: 0 dB) to +38 dB (total: +12 dB) SWOUT AGC circuit C for setting the attack and recovery times AGCin AGCout The input voltage range for AGC operation is from the input voltage at which AGC operation starts (taking the output gain into consideration, LFEin + SWin when the output voltage is

1.8 Vrms) to the same

voltage x 10 dB. Precaution on inputting the same phase to LFE ch and SW ch

Rev.1.0, Sep.19.2003, page 15 of 18 Diagrams AGC input/output characteristics AGCout:SWout(dBV) AGCin: LFEin+SWin(dBV) -20 -10 0 +10 -20 -10 +10 Output gain :0dB Output gain :+9dB Output gain :+6dB Output gain :+12dB +5.1dBV (1.8Vrms:TYP) +5.1dBV (1.8Vrms) -20 -10 0 +10 -20 -10 +10 +5.1dBV (1.8Vrms:TYP) -3.9dBV (0.64Vrms) +6.1dBV (2.02Vrms) AGCin: LFEin+SWin(dBV) -20 -10 0 +10 -20 -10 +10 +5.1dBV (1.8Vrms:TYP) -0.9dBV (0.90V rms) + 9. 1dBV (2.85Vrms) -20 -10 0 +10 -20 -10 +10 +5.1dBV (1.8Vrms:TYP) -6.9dBV (0.45Vrms) +3.1dBV (1.43Vrms) 10dB 10dB 10dB AGCin: LFEin+SWin(dBV) AGCin: LFEin+SWin(dBV) AGCout:SWout(dBV) AGCout:SWout(dBV)AGCout:SWout(dBV) System reset (a) Power-on operation Immediately after power is supplied, this IC generates a reset signal.

• Generation of the reset signal is governed by the time constant for the rise in power voltage when power is supplied.
• When VCC rises above roughly 5.5 V (1), the reset signal is transmitted (logic circuit is turned on).
• (1) The reset operation takes place in the period from reset signal transmission to (2) reset signal cancellation.
• Trst = “Timing A + about 20 µs” is the time up to reset cancellation (Timing A is time until VCC reaches 5.5 V)

Rev.1.0, Sep.19.2003, page 16 of 18 Reset timing diagram (1) Reset signal transmission Reset operation (2) Reset signal cancellation VDD (internal power supply) VCC VSS (internal power supply) t Reset cancellation (normal operation) 5.5V V Trst About 20 µs A As is shown in the above figure, the reset is cancelled after time Trst after the power-supply voltage has started to rise. The chip is then able to receive serial data. (b) Power-off operation (for reference)

• The internal VDD and VSS voltages fall as VCC falls (the opposite trend to that in the above figure).
• When the logic circuits are turned off, all setting data becomes invalid.

Rev.1.0, Sep.19.2003, page 17 of 18 Application Examle FR_LPFOUT FR_LPFIN SL_EXTIN SL_VOLIN SL_LPFOUT SL_LPFIN SR _EXTIN SR _VOLIN SR _LPFOUT SR _LPFIN C_VOLIN C_LPFOUT C_LPFIN LFE_VOLIN SW_IN VCC DATA CLOCK SRch IN Cch IN LFEch IN SWch IN GND TES T AGC FL_LPFOUT FL_LPFIN R_LPFI N R_LPFOUT L_LPFOUT L_LPFIN REFIN REFOUT FL_OUT FR_IN FR_OUT SL _BB1 SL _BB2 SL_OUT SR_BB1 SR_BB2 SR _OUT OUT SW_OUT SW_LPFIN SW_LPFOUT SW Note: The voltage input to pins 3, 7, 14, and 15 must not exceed the absolute maximum input voltage (2 Vrms). ch OUT 0 to -87dB,-∞ 0 to -87dB,-∞ 0 to -87dB,-∞ 0 to -87dB,-∞ AGC Microcomputer I/F Lch LPF amp Rch LPF amp FLch LPF ampFRch LPF amp FR input gain control 0,+5,+10dB FL input gain control 0,+5,+10dB SW output gain control 0,+6,+9,+12dB SLch LPF amp SRch LPF amp Cch LPF amp SLch volume SRch volume Cch volume LFEch volume +6dB +6dB +6dB FL output SW FR output SW ON OFF SRVOL input SW SLVOL input SW LFEMIX SW SWMIX SW ON Bass booster Bass booster Bass booster Bass booster /OFF ON/OFF VREF amp SWch LPF amp FLch IN Rch IN Lch IN Rch OUT Lch OUT FLch OUT SRch OUT Cch OUT SLch OUT to M61519FP to M61519FP FRch IN SLch IN SL_EXTIN SR _E XTIN from M61519FP from M61519FP from M61519FP 10µ 10µ 10µ 2.2k 4.7k 10µ 10µ 2.2k 4.7k 10µ 10µ 10µ 10k 2.2k 4.7k 1000p 1000p 10µ 10µ 47k 470 10k 220p 220p 10µ 220p 10k 220p 470 47k 10µ 1000p 2.2k 2.2k 47k 2200p 10µ 10µ 10µ 1000p 1000p 1000p 1000p 1000p 2.2k 2.2k 47k 2200p 10µ 100µ 100µ FR ch OUT 10µ 10µ 10k 10k 0.047µ 0.22µ 0.22µ 680 10µ 10µ 10µ 0.22µ 0.22µ 680 0.22µ 0.1µ 2.2k 10µ Max:2Vrms Max:2Vrms Max:2Vrms 47k 47k 47k VREF out Max:2Vrms 10k 10k Microcomputer

Rev.1.0, Sep.19.2003, page 18 of 18 Package Dimensions SSOP42-P-450-0.80 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Cu Alloy+42 Alloy 42P2R-E Plastic 42pin 450mil SSOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters H E .250 .050 .130 .317 .28 .6311 .30 .271 .02 .30 .150 .517 .48 .80 .9311 .50 .7651 .4311 .42 .40 .20 .717 .68 .2312 .70 .150 b2 — 0.5 — 0° 10 ° e e b2 Recommended Mount Pad —Z1 0.75 0.9 z MMP 42 22 211 HE E e y F A A2 A1 L c Detail F G b D Detail G z

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